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From: jkratoch@sourceware.org
To: archer-commits@sourceware.org
Subject: [SCM] archer: Merge commit 'origin/archer-jankratochvil-misc' into archer
Date: Thu, 05 Mar 2009 21:49:00 -0000 [thread overview]
Message-ID: <20090305214915.27895.qmail@sourceware.org> (raw)
The branch, archer has been updated
via a02ff1c049b55fae6e887eb4130e82aba3b4f897 (commit)
via 940c193de37706e1745719caefcb95d31d452fbc (commit)
via 76fccb9ce587c83f5d74c6f1ac8923c78f784341 (commit)
via f167d06f1917ae5474507153f672747077b7c4a6 (commit)
via af5f84e0d7400aed8217429f3159ffc424c78274 (commit)
via 83add4249d214f9fa385af953d9d2ad1e6b16ebd (commit)
from ace5ac468d6708dd9d078fe264e38cf8ba5ebc37 (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit a02ff1c049b55fae6e887eb4130e82aba3b4f897
Merge: 76fccb9ce587c83f5d74c6f1ac8923c78f784341 940c193de37706e1745719caefcb95d31d452fbc
Author: Jan Kratochvil <jan.kratochvil@redhat.com>
Date: Thu Mar 5 22:48:59 2009 +0100
Merge commit 'origin/archer-jankratochvil-misc' into archer
commit 76fccb9ce587c83f5d74c6f1ac8923c78f784341
Merge: ace5ac468d6708dd9d078fe264e38cf8ba5ebc37 f167d06f1917ae5474507153f672747077b7c4a6
Author: Jan Kratochvil <jan.kratochvil@redhat.com>
Date: Thu Mar 5 22:45:05 2009 +0100
Merge commit 'origin/archer-jankratochvil-misc' into archer
-----------------------------------------------------------------------
Summary of changes:
gdb/rs6000-tdep.c | 52 +++++++++++++++--------------
gdb/testsuite/gdb.arch/powerpc-power7.exp | 10 -----
opcodes/ChangeLog | 5 +++
opcodes/ppc-opc.c | 20 +++++-----
4 files changed, 42 insertions(+), 45 deletions(-)
First 500 lines of diff:
diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c
index 1c59a42..926d0b6 100644
--- a/gdb/rs6000-tdep.c
+++ b/gdb/rs6000-tdep.c
@@ -117,9 +117,6 @@ static const char *powerpc_vector_strings[] =
NULL
};
-/* The configurable `disassemble_info.disassembler_options' string. */
-static char *disassembler_options;
-
/* A variable that can be configured by the user. */
static enum powerpc_vector_abi powerpc_vector_abi_global = POWERPC_VEC_AUTO;
static const char *powerpc_vector_abi_string = "auto";
@@ -2996,17 +2993,15 @@ find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
}
static int
-gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info_pointer)
+gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
{
- disassemble_info info = *info_pointer;
+ if (!info->disassembler_options)
+ info->disassembler_options = "any";
- if (disassembler_options && disassembler_options[0])
- info.disassembler_options = disassembler_options;
-
- if (info.endian == BFD_ENDIAN_BIG)
- return print_insn_big_powerpc (memaddr, &info);
+ if (info->endian == BFD_ENDIAN_BIG)
+ return print_insn_big_powerpc (memaddr, info);
else
- return print_insn_little_powerpc (memaddr, &info);
+ return print_insn_little_powerpc (memaddr, info);
}
\f
static CORE_ADDR
@@ -3331,6 +3326,7 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
enum bfd_architecture arch;
unsigned long mach;
bfd abfd;
+ asection *sect;
enum auto_boolean soft_float_flag = powerpc_soft_float_global;
int soft_float;
enum powerpc_vector_abi vector_abi = powerpc_vector_abi_global;
@@ -3379,6 +3375,26 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
arch = info.bfd_arch_info->arch;
mach = info.bfd_arch_info->mach;
+ /* For e500 executables, the apuinfo section is of help here. Such
+ section contains the identifier and revision number of each
+ Application-specific Processing Unit that is present on the
+ chip. The content of the section is determined by the assembler
+ which looks at each instruction and determines which unit (and
+ which version of it) can execute it. In our case we just look for
+ the existance of the section. */
+
+ if (info.abfd)
+ {
+ sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo");
+ if (sect)
+ {
+ arch = info.bfd_arch_info->arch;
+ mach = bfd_mach_ppc_e500;
+ bfd_default_set_arch_mach (&abfd, arch, mach);
+ info.bfd_arch_info = bfd_get_arch_info (&abfd);
+ }
+ }
+
/* Find a default target description which describes our register
layout, if we do not already have one. */
if (! tdesc_has_registers (tdesc))
@@ -4042,18 +4058,4 @@ _initialize_rs6000_tdep (void)
_("Show the vector ABI."),
NULL, powerpc_set_vector_abi, NULL,
&setpowerpccmdlist, &showpowerpccmdlist);
-
- /* Arches list is taken from opcodes/ppc-dis.c powerpc_init_dialect. */
- disassembler_options = xstrdup ("any");
- add_setshow_string_cmd ("disassembler-options", class_support,
- &disassembler_options, _("\
-Pass the text on to disassembler."), _("\
-Show the text passed on to disassembler."), _("\
-This is the objdump option -M to specify the PowerPC model. The possible\n\
-(sub)strings are: ppcps, booke, e500mc, e500, efs, e300, 440, 464, power4,\n\
-power5, cell, power6, power7, vsx, any, 32 and 64. Unlike objdump GDB uses\n\
-the default value `any'."),
- NULL,
- NULL,
- &setpowerpccmdlist, &showpowerpccmdlist);
}
diff --git a/gdb/testsuite/gdb.arch/powerpc-power7.exp b/gdb/testsuite/gdb.arch/powerpc-power7.exp
index e1fc23f..d9c48f9 100644
--- a/gdb/testsuite/gdb.arch/powerpc-power7.exp
+++ b/gdb/testsuite/gdb.arch/powerpc-power7.exp
@@ -37,16 +37,6 @@ gdb_reinitialize_dir $srcdir/$subdir
gdb_load ${objfile}
-# Setup the disassembler. With the default `any' flavor the instruction:
-# 0x20: xxmrghd vs3,vs4,vs5
-# (incl. many others) would get disassembled as:
-# 0x20: stfq f3,10320(r4)
-
-gdb_test "set powerpc disassembler-options power7"
-gdb_test "show powerpc disassembler-options power7" \
- "The text passed on to disassembler is \"power7\"."
-
-
# Disassemble the function.
set test "disass func"
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 34230ec..0a81ca4 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2009-03-03 Peter Bergner <bergner@vnet.ibm.com>
+
+ * ppc-opc.c (powerpc_opcodes): Reorder the opcode table so that
+ instructions from newer processors are listed before older ones.
+
2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
* score7-dis.c: New file.
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index c872db5..5e70395 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -4560,8 +4560,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"lhbrx", X(31,790), X_MASK, COM, PPCNONE, {RT, RA0, RB}},
-{"lfqx", X(31,791), X_MASK, POWER2, PPCNONE, {FRT, RA, RB}},
{"lfdpx", X(31,791), X_MASK, POWER6, POWER7, {FRT, RA, RB}},
+{"lfqx", X(31,791), X_MASK, POWER2, PPCNONE, {FRT, RA, RB}},
{"sraw", XRC(31,792,0), X_MASK, PPCCOM, PPCNONE, {RA, RS, RB}},
{"sra", XRC(31,792,0), X_MASK, PWRCOM, PPCNONE, {RA, RS, RB}},
@@ -4638,8 +4638,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"sthbrx", X(31,918), X_MASK, COM, PPCNONE, {RS, RA0, RB}},
-{"stfqx", X(31,919), X_MASK, POWER2, PPCNONE, {FRS, RA, RB}},
{"stfdpx", X(31,919), X_MASK, POWER6, PPCNONE, {FRS, RA, RB}},
+{"stfqx", X(31,919), X_MASK, POWER2, PPCNONE, {FRS, RA, RB}},
{"sraq", XRC(31,920,0), X_MASK, M601, PPCNONE, {RA, RS, RB}},
{"sraq.", XRC(31,920,1), X_MASK, M601, PPCNONE, {RA, RS, RB}},
@@ -4801,12 +4801,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"psq_l", OP(56), OP_MASK, PPCPS, PPCNONE, {FRT,PSD,RA,PSW,PSQ}},
+{"lfdp", OP(57), OP_MASK, POWER6, POWER7, {FRT, D, RA0}},
+
{"lfqu", OP(57), OP_MASK, POWER2, PPCNONE, {FRT, D, RA0}},
{"psq_lu", OP(57), OP_MASK, PPCPS, PPCNONE, {FRT,PSD,RA,PSW,PSQ}},
-{"lfdp", OP(57), OP_MASK, POWER6, POWER7, {FRT, D, RA0}},
-
{"ld", DSO(58,0), DS_MASK, PPC64, PPCNONE, {RT, DS, RA0}},
{"ldu", DSO(58,1), DS_MASK, PPC64, PPCNONE, {RT, DS, RAL}},
{"lwa", DSO(58,2), DS_MASK, PPC64, PPCNONE, {RT, DS, RA0}},
@@ -4921,10 +4921,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"fcfidus", XRC(59,974,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
{"fcfidus.", XRC(59,974,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}},
-{"stfq", OP(60), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}},
-
-{"psq_st", OP(60), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}},
-
{"xxsldwi", XX3(60,2), XX3SHW_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, SHW}},
{"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, XC6}},
{"xxspltd", XX3(60,10), XX3DM_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S, DMEX}},
@@ -5067,12 +5063,16 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"xvcvsxddp", XX2(60,504), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
{"xvnegdp", XX2(60,505), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}},
-{"psq_stu", OP(61), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}},
+{"stfq", OP(60), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}},
-{"stfqu", OP(61), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}},
+{"psq_st", OP(60), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}},
{"stfdp", OP(61), OP_MASK, POWER6, PPCNONE, {FRT, D, RA0}},
+{"stfqu", OP(61), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}},
+
+{"psq_stu", OP(61), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}},
+
{"std", DSO(62,0), DS_MASK, PPC64, PPCNONE, {RS, DS, RA0}},
{"stdu", DSO(62,1), DS_MASK, PPC64, PPCNONE, {RS, DS, RAS}},
{"stq", DSO(62,2), DS_MASK, POWER4, PPCNONE, {RSQ, DS, RA0}},
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