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From: jkratoch@sourceware.org
To: archer-commits@sourceware.org
Subject: [SCM] master: Merge remote branch 'gdb/master'
Date: Mon, 27 Sep 2010 09:48:00 -0000 [thread overview]
Message-ID: <20100927094854.5534.qmail@sourceware.org> (raw)
The branch, master has been updated
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- Log -----------------------------------------------------------------
commit 0e71db4d2ee3a8c168c6ef5476a36fabd58c7c11
Merge: 537e20c 7bf5255
Author: Jan Kratochvil <jan.kratochvil@redhat.com>
Date: Mon Sep 27 11:48:38 2010 +0200
Merge remote branch 'gdb/master'
commit 7bf5255da5694eff7632e8464e44f3299217034d
Author: gdbadmin <gdbadmin@sourceware.org>
Date: Mon Sep 27 00:00:33 2010 +0000
*** empty log message ***
commit 5e8450e4a974ea0d04bb46dadd4cac674e374d22
Author: Alan Modra <amodra@bigpond.net.au>
Date: Mon Sep 27 00:00:05 2010 +0000
daily update
commit aa639c6329ec493e3e9f123a4a845bed859507e8
Author: gdbadmin <gdbadmin@sourceware.org>
Date: Sun Sep 26 00:00:33 2010 +0000
*** empty log message ***
commit ee293fdd5ff3486bef65e4f872b463f6d92932d9
Author: Alan Modra <amodra@bigpond.net.au>
Date: Sun Sep 26 00:00:05 2010 +0000
daily update
commit acc8af847d83213abc69174e5a2cdc9b5b9eeecf
Author: gdbadmin <gdbadmin@sourceware.org>
Date: Sat Sep 25 00:00:33 2010 +0000
*** empty log message ***
commit 52dbb162613f7cb7cf4e414b86d507052c63bc21
Author: Alan Modra <amodra@bigpond.net.au>
Date: Sat Sep 25 00:00:05 2010 +0000
daily update
commit 567c55d94fe7bce0dd3d82618b3ee7f910319e1a
Author: Jan Kratochvil <jan.kratochvil@redhat.com>
Date: Fri Sep 24 18:35:20 2010 +0000
gdb/
Fix lost siginfo_t for inferior calls.
* infrun.c
(struct inferior_thread_state) <siginfo_gdbarch, siginfo_data>: New.
(save_inferior_thread_state): New variables regcache, gdbarch and
siginfo_data. Initialize SIGINFO_DATA if gdbarch_get_siginfo_type_p.
Move INF_STATE allocation later, pre-clear it. Initialize REGISTERS
using REGCACHE.
(restore_inferior_thread_state): New variables regcache and gdbarch.
Restore SIGINFO_DATA for matching GDBARCH. Restore REGISTERS using
REGCACHE. Free also SIGINFO_DATA.
gdb/testsuite/
Fix lost siginfo_t for inferior calls.
* gdb.base/siginfo-infcall.exp: New file.
* gdb.base/siginfo-infcall.c: New file.
commit b2bdd4ec26d7368c66530c89e0e9d04584f23ac2
Author: Tom Tromey <tromey@redhat.com>
Date: Fri Sep 24 16:11:44 2010 +0000
* dwarf2read.c (dw2_expand_symtabs_matching): Add missing
MAYBE_SWAPs.
(dw2_map_symbol_names): Likewise.
commit 5ce5693ba8da81ee0afa7b743e80daf4b735abe4
Author: swagiaal <swagiaal>
Date: Fri Sep 24 14:47:52 2010 +0000
Fix find_oload_champ_namespace_loop memory leak.
2010-09-24 Sami Wagiaalla <swagiaal@redhat.com>
* valops.c (find_oload_champ_namespace_loop): replace incorrect
discard_cleanups do_cleanups.
commit 6aceb3f76551c9332a1fc12a7ba4cbb6fbd9a52e
Author: Pedro Alves <pedro@codesourcery.com>
Date: Fri Sep 24 13:44:00 2010 +0000
PR gdb/11842
gdb/
* amd64-linux-nat.c (compat_siginfo_from_siginfo)
(siginfo_from_compat_siginfo): Also copy si_pid and si_uid when
si_code is < 0. Check for si_code == SI_TIMER before checking for
si_code < 0.
gdb/gdbserver/
* linux-x86-low.c (compat_siginfo_from_siginfo)
(siginfo_from_compat_siginfo): Also copy si_pid and si_uid when
si_code is < 0. Check for si_code == SI_TIMER before checking for
si_code < 0.
commit c35d4b17866d95f88dfec12539acd6714bdb7061
Author: Pedro Alves <pedro@codesourcery.com>
Date: Fri Sep 24 13:41:42 2010 +0000
gdb/
* amd64-linux-nat.c (compat_siginfo_from_siginfo)
(siginfo_from_compat_siginfo): Also copy si_pid and si_uid when
si_code is < 0. Check for si_code == SI_TIMER before checking for
si_code < 0.
gdb/gdbserver/
* linux-x86-low.c (compat_siginfo_from_siginfo)
(siginfo_from_compat_siginfo): Also copy si_pid and si_uid when
si_code is < 0. Check for si_code == SI_TIMER before checking for
si_code < 0.
commit 31754a9dc78c7d283677b7e5e3d68dff891371b6
Author: tschwinge <tschwinge>
Date: Fri Sep 24 12:14:23 2010 +0000
2010-09-24 Thomas Schwinge <thomas@codesourcery.com>
* elf32-arm.c, elf32-cris.c, elf32-hppa.c, elf32-i370.c, elf32-m32r.c,
elf32-m68k.c, elf32-microblaze.c, elf32-ppc.c, elf32-score.c,
elf32-score7.c, elf32-sh.c, elf32-vax.c, elf32-xtensa.c, elf64-alpha.c,
elf64-hppa.c, elf64-mips.c, elf64-ppc.c, elf64-sparc.c, elfcode.h,
elflink.c, elfxx-ia64.c, elfxx-mips.c: Use STN_UNDEF when referring to
the zero symbol index.
commit 475c0e4dc2b66e2025dbc862155a55fd8b04466c
Author: tschwinge <tschwinge>
Date: Fri Sep 24 11:59:18 2010 +0000
2010-09-24 Thomas Schwinge <thomas@codesourcery.com>
* elflink.c (bfd_elf_reloc_symbol_deleted_p): Compare the symbol index
to STN_UNDEF, not SHN_UNDEF.
commit 328d04710b395061e65b4c9d3e063ff4ff9d5117
Author: Pedro Alves <pedro@codesourcery.com>
Date: Fri Sep 24 11:15:51 2010 +0000
* objfiles.h (ALL_OBJSECTIONS): Handle breaks in the inner loop.
commit 120873b176cfac0958e0378feec2c46139890545
Author: Kevin Buettner <kevinb@redhat.com>
Date: Fri Sep 24 05:18:23 2010 +0000
* rx.c (decode_opcode): Add cycle information for RXO_smovu.
commit d53f48c3a270300ec7a3620e2270d9c7d6a0fca4
Author: Kevin Buettner <kevinb@redhat.com>
Date: Fri Sep 24 04:45:08 2010 +0000
Fix typo in ChangeLog entry.
commit bceafcae973da3cf59458e425f39c46fac613997
Author: gdbadmin <gdbadmin@sourceware.org>
Date: Fri Sep 24 00:00:33 2010 +0000
*** empty log message ***
commit fa51fc3bc5c3b8781a058b5917e15ca09c5ff2db
Author: Alan Modra <amodra@bigpond.net.au>
Date: Fri Sep 24 00:00:05 2010 +0000
daily update
commit 1c2ae3626f38f87861a6f0eb0fb3063023cb3fd7
Author: Kevin Buettner <kevinb@redhat.com>
Date: Thu Sep 23 23:42:53 2010 +0000
* cpu.h (reset_decoder): Declare.
* load.c (rx_load): Call `reset_decoder'.
* rx.c (reset_decoder): New function.
commit 5c7709b71724f8b8371506d280a07660d58ca8cf
Author: Kevin Buettner <kevinb@redhat.com>
Date: Thu Sep 23 23:26:42 2010 +0000
* rx.c (decode_opcode): Declare `rx' as unsigned.
commit 6fcc496fec7b750793c85da4fd70470e8d176cfa
Author: Kevin Buettner <kevinb@redhat.com>
Date: Thu Sep 23 23:05:27 2010 +0000
* fpu.c, gdb-if.c, load.c, misc.c, syscalls.c (config.h): Include.
commit 56b89e1f162465abef29b960fd88b7ae574e70fa
Author: Bernd Schmidt <bernd.schmidt@analog.com>
Date: Thu Sep 23 16:16:37 2010 +0000
bfd/
* elf32-tic6x.c (elf32_tic6x_fake_sections): New function.
(elf_backend_fake_sections): Define.
ld/testsuite/
* ld-tic6x/pcrel-reloc-local-r-rel-rela.d: New test.
commit 23c304e2a4ba1b02530f4cc2d5da8c17a5bec27f
Author: mgretton <mgretton>
Date: Thu Sep 23 15:52:19 2010 +0000
* bfd/bfd-in2.h (BFD_RELOC_ARM_HVC): New enum value.
* gas/config/tc-arm.c (arm_ext_virt): New variable.
(arm_reg_type): Add REG_TYPE_RNB for banked registers.
(reg_entry): Allow registers to be larger than a byte.
(reg_alias): Fix type warning.
(parse_operands): Parse banked registers when appropriate.
(do_mrs): Add support for Virtualization Extensions.
(do_hvc): New function.
(do_t_mrs): Add support for Virtualization Extensions.
(do_t_msr): Likewise.
(do_t_hvc): New function.
(SPLRBANK): New define.
(reg_names): Add banked registers.
(insns): Add support for Virtualization Extensions.
(md_apply_fixup): Likewise.
(arm_cpus): -mcpu=cortex-a15 implies the Virtualization Extensions.
(arm_extensions): Add 'virt' extension.
(aeabi_set_public_attributes): Add support for Virtualization
Extensions.
* gas/doc/c-arm.texi: Document 'virt' extension.
* gas/testsuite/gas/arm/armv7-a+virt.d: New test.
* gas/testsuite/gas/arm/armv7-a+virt.s: Likewise.
* gas/testsuite/gas/arm/attr-march-all.d: Update for Virtualization Extensions.
* gas/testsuite/gas/arm/attr-march-armv7-a+sec+virt.d: New test.
* gas/testsuite/gas/arm/attr-march-armv7-a+virt.d: Likewise.
* include/opcode/arm.h (ARM_EXT_VIRT): New define.
(ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
(ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
Extensions.
* opcodes/arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support.
(thumb32_opcodes): Likewise.
(banked_regname): New function.
(print_insn_arm): Add Virtualization Extensions support.
(print_insn_thumb32): Likewise.
commit 6febdbdd2647bf02802d4f051d37dd312ffdda85
Author: mgretton <mgretton>
Date: Thu Sep 23 15:37:45 2010 +0000
* gas/config/tc-arm.c (arm_ext_adiv): New variable.
(do_div): New function.
(insns): Accept UDIV and SDIV in ARM state.
(arm_cpus): The cortex-a15 option has all current v7-A extensions.
(arm_extensions): Add 'idiv' extension.
(aeabi_set_public_attributes): Update Tag_DIV_use values for the
Integer Divide extension.
* gas/doc/c-arm.texi: Document the idiv extension.
* gas/testsuite/gas/arm/armv7-a+idiv.d: New test.
* gas/testsuite/gas/arm/armv7-a+idiv.s: Likewise.
* gas/testsuite/gas/arm/attr-march-all.d: Update for Integer divide extension.
* gas/testsuite/gas/arm/attr-march-armv7-a+idiv.d: New test.
* include/opcode/arm.h (ARM_AEXT_ADIV): New define.
(ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
* opcodes/arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in
ARM state.
commit 07d01a4532b79e258289dc72905ac3725d420baf
Author: mgretton <mgretton>
Date: Thu Sep 23 15:31:34 2010 +0000
* config/tc-arm.c (arm_ext_v6m): New variable.
(arm_ext_m): Add support for OS extension.
(arm_ext_os): New variable.
(do_t_swi): In v6-M ensure we have the OS extension.
(arm_cpus): The cortex-m1 and cortex-m0 options have the OS
extension by default.
(arm_archs): Add armv6s-m.
(arm_extensions): Add 'os' extension.
(cpu_arch_ver): Add support for v6S-M.
* gas/doc/c-arm.texi: Document the OS Extension, and v6-m and v6s-m
architecture options.
* gas/testsuite/gas/arm/archv6s-m-bad.d: New test.
* gas/testsuite/gas/arm/archv6s-m-bad.l: Likewise.
* gas/testsuite/gas/arm/archv6s-m.d: Likewise.
* gas/testsuite/gas/arm/archv6s-m.s: Likewise.
* gas/testsuite/gas/arm/attr-march-armv6-m+os.d: Likewise.
* gas/testsuite/gas/arm/attr-march-armv6s-m.d: Likewise.
* include/opcode/arm.h (ARM_EXT_OS): New define.
(ARM_AEXT_V6SM): Likewise.
(ARM_ARCH_V6SM): Likewise.
commit b61a5fe0940352717a42426aec70e4844e8654fc
Author: mgretton <mgretton>
Date: Thu Sep 23 15:26:23 2010 +0000
* gas/config/tc-arm.c (arm_ext_v6z): Remove.
(arm_ext_sec): New variable.
(do_t_smc): In Thumb state SMC requires v7-A.
(insns): Make SMC depend on Security Extensions.
(arm_cpus): All -mcpu=cortex-a* options have the Security Extensions.
(arm_extensions): Add 'sec' extension.
(cpu_arch_ver): Reorder.
(aeabi_set_public_attributes): Emit Tag_Virtualization_use as
appropriate.
* gas/doc/c-arm.texi: Document Security Extensions.
* gas/testsuite/gas/arm/attr-march-all.d: Update for Security Extensions..
* gas/testsuite/gas/arm/attr-march-armv6k+sec.d: New test.
* gas/testsuite/gas/arm/attr-march-armv6z.d: Update for Security Extensions.
* gas/testsuite/gas/arm/attr-march-armv6zk.d: Likewise.
* gas/testsuite/gas/arm/attr-march-armv6zkt2.d: Likewise.
* gas/testsuite/gas/arm/attr-march-armv6zt2.d: Likewise.
* gas/testsuite/gas/arm/attr-march-armv7-a+sec.d: New test.
* gas/testsuite/gas/arm/attr-mcpu.d: Update for Security Extensions.
* gas/testsuite/gas/arm/thumb32.d: Likewise.
* gas/testsuite/gas/arm/thumb32.s: Likewise.
* include/opcode/arm.h (ARM_EXT_V6Z): Remove.
(ARM_EXT_SEC): New define.
(ARM_AEXT_V6Z): Use Security Extensions.
(ARM_AEXT_V6ZK): Likeiwse.
(ARM_AEXT_V6ZT2): Likewise.
(ARM_AEXT_V6ZKT2): Likewise.
(ARM_AEXT_V7_ARM): Base v7 does not have Security Extensions.
(ARM_ARCH_V7A_SEC): New define.
(ARM_ARCH_V7A_MP): Rename...
(ARM_ARCH_V7A_MP_SEC): ...to this and add Security Extensions.
* ld/testsuite/ld-arm/attr-merge-6.attr: Update for Security Extensions.
* ld/testsuite/ld-arm/attr-merge-7.attr: Likewise.
* opcodes/arm-dis.c (arm_opcodes): SMC implies Security Extensions.
(thumb32_opcodes): Likewise.
commit c6fa80a910f4e2c12c70869510b04356a93cc009
Author: mgretton <mgretton>
Date: Thu Sep 23 15:18:18 2010 +0000
* gas/config/tc-arm.c (arm_ext_mp): Add.
(do_pld): Update comment.
(insns): Add support for pldw.
(arm_cpus): Update cortex-a5, cortex-a9, and cortex-a15 to support
MP extension.
(arm_extensions): Add 'mp' extension.
(aeabi_set_public_attributes): Emit correct build attribute when
MP extension is enabled.
* gas/doc/c-arm.texi: Update for MP extensions.
* gas/testsuite/gas/arm/arch7a-mp.d: Add.
* gas/testsuite/gas/arm/arch7ar-mp.s: Likewise.
* gas/testsuite/gas/arm/arch7r-mp.d: Likewise.
* gas/testsuite/gas/arm/armv2-mp-bad.d: Likewise.
* gas/testsuite/gas/arm/armv2-mp-bad.l: Likewise.
* gas/testsuite/gas/arm/attr-march-all.d: Update for MP extension.
* gas/testsuite/gas/arm/attr-march-armv7-a+mp.d: Add.
* gas/testsuite/gas/arm/attr-march-armv7-r+mp.d: Likewise.
* include/opcode/arm.h (ARM_EXT_MP): Add.
(ARM_ARCH_V7A_MP): Likewise.
* opcodes/arm-dis.c (arm_opcodes): Add support for pldw.
(thumb32_opcodes): Likewise.
commit ba4510b656b08751f72d4741b93c4596ad8eeaff
Author: Alan Modra <amodra@bigpond.net.au>
Date: Thu Sep 23 11:55:00 2010 +0000
* cpu-d10v.c: Make bits_per_address 18 for all arch_info entries.
commit 09f7409a10f0506560e3567be4c15b49ac5396fa
Author: Alan Modra <amodra@bigpond.net.au>
Date: Thu Sep 23 11:40:05 2010 +0000
ld/
* ldlang.c (lang_add_section): Don't copy SEC_RELOC from input
to output section on a final link.
bfd/
* elf.c (_bfd_elf_init_private_section_data): Allow for SEC_RELOC
difference between input and output section.
commit 0b6be011a6eaa679b9a25f623c98f72c625807c4
Author: gdbadmin <gdbadmin@sourceware.org>
Date: Thu Sep 23 00:00:33 2010 +0000
*** empty log message ***
commit ae35288a9e046b50754df56422e61ca7179e325c
Author: Alan Modra <amodra@bigpond.net.au>
Date: Thu Sep 23 00:00:04 2010 +0000
daily update
commit 9f3ac352623ece6d170a6f94b3413ee532528c29
Author: Joel Brobecker <brobecker@gnat.com>
Date: Wed Sep 22 22:50:52 2010 +0000
[Ada] Do not compute task ptid when debugging core file
After thread support over core files was added for GNU/Linux was added,
we started noticing the following type of crash when trying to perform
task switches (this is a bit accademic, since task switching is not
supported when debugging core files - this is what our testcase was
verifying).
(please check out the comment inside ada-tasks.c:task_command for
more details on this topic)
The reason for the crash comes from the fact that the GNU/Linux thread
layer now gets pushed on the target stack, causing the associated
to_get_ada_task_ptid target method to be activated. This routine
makes the assumption that, for all threads, the private area is not
NULL. This is incorrect in the case of core files, as the core layer
creates some threads with no private data.
But, taking a step back, we don't need to try to compute the task ptid,
as we'll never be using it anyways (we only use it for task switching).
So the fix is to avoid the ptid computation altogether when debugging
a core file.
gdb/ChangeLog:
* ada-tasks.c (read_atcb): Do not compute the task ptid when
debugging a core file.
commit c6a5f5560402451d3ebd0f559d4f891151cc96a6
Author: Mike Frysinger <vapier@gentoo.org>
Date: Wed Sep 22 21:55:17 2010 +0000
opcodes: blackfin: fix decoding of 32bit addresses on 64bit systems
The Blackfin ISA is very exact with regards to address truncation when
under/over flowing its 32bit range. On a 32bit system, things work the
same and so addresses are decoded properly. On a 64bit system though,
the decoded addresses may include the bits that are supposed to have
been truncated. So force a 32bit truncation after the address has been
calculated.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
commit cd120c49a12d5ea43939991a64438b337d9e5c7e
Author: Mike Frysinger <vapier@gentoo.org>
Date: Wed Sep 22 21:54:33 2010 +0000
opcodes: blackfin: fix decoding of all register move insns
Many register move insns were not being decoded properly, so rewrite
the whole function to be a bit more manageable in terms of valid
combinations.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
commit 405e18f17fbc5a62ce6c17b0d2749883de095673
Author: Mike Frysinger <vapier@gentoo.org>
Date: Wed Sep 22 21:53:46 2010 +0000
opcodes: blackfin: fix decoding of many invalid insns
The Blackfin disassembler was originally based on the premise of parsing
valid opcodes all the time, so some of the opcode checking can be a bit
fuzzy. This is exemplified in decoding of parallel insns where many
times things are decoded as invalid when in reality, they may not be
used in parallel combinations. So add parallel checking to most insn
decoding routines so we see ILLEGAL and not just whatever insn happens
to be close to a valid mnemonic, as well as some additional sub-opcode
checks.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
commit 8f8c824eac3c205b015bc4a4c3bd4b6e4f17d57c
Author: Mike Frysinger <vapier@gentoo.org>
Date: Wed Sep 22 21:53:14 2010 +0000
opcodes: blackfin: mark push/pop insns with a P6/P7 range as illegal
The push/pop multiple insn has a 3 bit field for the P register range,
but only values of 0...5 are valid (P0 - P5). There is no such P6 or
P7 register, so mark these insns as illegal.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
commit 5a239fd6b354ceb8a4883cadb007b10ea2996065
Author: Mike Frysinger <vapier@gentoo.org>
Date: Wed Sep 22 21:41:39 2010 +0000
opcodes: blackfin: fix decoding of vector shift insn w/saturation
The saturation bit was missed when decoding a vector shift insn
leading to the output looking the same as the non-saturating insn.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
commit 9df2cd6d9d166bc17e3251e41b1118b76976336a
Author: Mike Frysinger <vapier@gentoo.org>
Date: Wed Sep 22 21:39:08 2010 +0000
opcodes: blackfin: decode all ASTAT bits
All ASTAT bits work in the hardware even though they aren't part of the
official Blackfin ISA. So decode every ASTAT field to make the output
a bit nicer when working with hand generated opcodes.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
commit 365f0a0b6b629c3f8e5001d10b55c83963f08d35
Author: Mike Frysinger <vapier@gentoo.org>
Date: Wed Sep 22 21:38:20 2010 +0000
opcodes: blackfin: decode insns with invalid register as illegal
Sometimes the encoding in the opcode is a 4 bit field which defines a
register number. However, register numbers are only 0-7, so make sure
we call illegal for when the opcode register number is greater than 8.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
commit 0cc328604bb680d93e600926a5da3797e93f41d0
Author: Mike Frysinger <vapier@gentoo.org>
Date: Wed Sep 22 21:26:13 2010 +0000
gas: blackfin: fix DBG/DBGCMPLX insn encoding
Some extended registers when given to the DBG/DBGCMPLX pseudo insns are
not encoded properly. So fix them, fix the display of them when being
disassembled, and add testcases.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
commit df0e1413b3a179a86e8e207174902999acdafbb2
Author: Mike Frysinger <vapier@gentoo.org>
Date: Wed Sep 22 21:05:03 2010 +0000
opcodes/gas: blackfin: handle more ASTAT flags
Support a few more ASTAT bits with the standard insns that operate on
ASTAT bits directly.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
commit 713e5270b64c38eec2661edd46ac9b29443e21d8
Author: Mike Frysinger <vapier@gentoo.org>
Date: Wed Sep 22 20:59:00 2010 +0000
opcodes/gas: blackfin: support OUTC debug insn
The disassembler has partial (but incomplete/broken) support already for
the pseudo debug insn OUTC, so let's fix it up and finish it. And now
that the disassembler can handle it, make sure our assembler can output
it too.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
commit 016bf22e98cd670562662c2917badf3ba0517f1d
Author: Mike Frysinger <vapier@gentoo.org>
Date: Wed Sep 22 20:37:23 2010 +0000
opcodes: blackfin: fix decoding of LSHIFT insns
The Blackfin ISA does not have a "SHIFT" insn, it has either LSHIFT,
ASHIFT, or BXORSHIFT. So be specific when disassembling.
As fall out of this change, we need to update some assembler tests.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
commit da5fd72707e1f19dab343c9de9c51d4cf48eba61
Author: Mike Frysinger <vapier@gentoo.org>
Date: Wed Sep 22 20:32:40 2010 +0000
opcodes: blackfin: constify formatting related structures
No need for these local structures related to formatting of output to
be writable, so constify the whole shebang.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
commit 5911a53fbef58ea324bac00ffc64dc9d6deb8df7
Author: Joel Brobecker <brobecker@gnat.com>
Date: Wed Sep 22 20:08:04 2010 +0000
Fix order of ChangeLog entries.
(entry added at wrong location by patch).
commit 519e1f7c53a6d0add495fa08c5eccedbc24a1d3e
Author: Joel Brobecker <brobecker@gnat.com>
Date: Wed Sep 22 20:06:58 2010 +0000
preserve columnar alignment.
gdb/testsuite/ChangeLog:
* gdb.dwarf2/dw2-const.S: Minor (space) reformatting.
commit c408df2d80e5def5fc57fff7bc2dcf9e79f6d15a
Author: Jan Kratochvil <jan.kratochvil@redhat.com>
Date: Wed Sep 22 20:00:52 2010 +0000
gdb/
Code cleanup.
* objfiles.c (allocate_objfile) <objfile->name != NULL>: Remove.
(free_objfile) <objfile->name != NULL>: Remove the conditional around
xfree.
* objfiles.h (struct objfile) <name>: New comment it is never NULL.
* python/py-auto-load.c (auto_load_new_objfile) <!objfile->name>:
Remove.
* python/py-objfile.c (objfpy_get_filename) <obj->objfile->name>
Remove the conditional.
* python/py-progspace.c (pspy_get_filename) <objfile->name>: Likewise.
commit 3c608a850b8c35416d1dfef6875af62adf62f076
Author: Jan Kratochvil <jan.kratochvil@redhat.com>
Date: Wed Sep 22 19:59:11 2010 +0000
gdb/
* main.c: Include objfiles.h.
(captured_main): New variable objfile. Call
load_auto_scripts_for_objfile for ALL_OBJFILES.
commit 0d21ec3bc7edce96ad959d5e9fd2fd8bc0b8e307
Author: Jan Kratochvil <jan.kratochvil@redhat.com>
Date: Wed Sep 22 19:22:43 2010 +0000
gdb/
* dwarf2read.c (die_needs_namespace) <DW_TAG_variable>: Add also
DW_TAG_constant.
gdb/testsuite/
* gdb.fortran/module.exp (fully qualified name of DW_TAG_constant):
New test.
* gdb.fortran/module.f90 (mod1) <var_const>: New constant.
commit 5354be2515b24e1f451606218fed990039ed3591
Author: Joel Brobecker <brobecker@gnat.com>
Date: Wed Sep 22 19:13:40 2010 +0000
[testsuite] dw2-const.S: fix type reference size on 64bit platforms.
The testcase was failing on various 64bit platforms, because the
debugging info said that the target type for a const type is a
4-byte reference. In the asm file, I used a .long directive, but
the size of .long is of course dependent on the platform. This
replaces this .long by a .4byte directive.
gdb/testsuite/ChangeLog:
* gdb.dwarf2/dw2-const.S: Use .4byte to reference the target
type of our const type.
commit a94d3393376ef0fd2b60292ad33100ca830c2df0
Author: Joel Brobecker <brobecker@gnat.com>
Date: Wed Sep 22 16:15:33 2010 +0000
DWARF: Add support for DW_TAG_constant DIEs
gdb/ChangeLog:
* dwarf2read.c (scan_partial_symbols): Add handling of
DW_TAG_constant DIEs.
(add_partial_symbol, load_partial_dies, new_symbol): Likewise.
gdb/testsuite/ChangeLog:
* gdb.dwarf2/dw2-const.S, gdb.dwarf2/dw2-const.exp: New files.
commit 8ce2c9ced8485dc64edd4c274007d9252061521d
Author: Joel Brobecker <brobecker@gnat.com>
Date: Wed Sep 22 16:14:53 2010 +0000
Allow disabling of gdbserver build (--enable-gdbserver=yes/no/auto).
This patch adds a new --enable-gdbserver=yes/no/auto command-line switch
in gdb/configure. The primary purpose is to allow a user to disable the
build & install of gdbserver when not desired. It also allows the user
to request gdbserver in which case the configure script will abort if
automatic building of gdbserver is not supported for that configuration.
The default keeps things as is: We automatically build gdbserver if
building for a native configuration and if gdbserver is supported for
that configuration.
gdb/ChangeLog:
* configure.ac: Add support for --enable-gdbserver.
* configure: Regenerate.
At AdaCore, this is mostly intended for ia64-linux, where we currently
do not want to distribute gdbserver. This will be useful in the context
of I417-033, where we are now using "make install" to determine what
needs to be packaged inside the GNAT Pro package.
commit 6a4a712ca215ea1fea95fe64e73d92ec7bb8305b
Author: Tom Tromey <tromey@redhat.com>
Date: Wed Sep 22 15:51:43 2010 +0000
* gdb.texinfo (Values From Inferior): Mention Value.__init__.
commit efe1b362417c1cd51b6a0ca00bcf21a3fb797cd5
Author: swagiaal <swagiaal>
Date: Wed Sep 22 15:48:55 2010 +0000
Fix PR 12028: "GDB crashes on a double free during overload resolution "
2010-09-22 Sami Wagiaalla <swagiaal@redhat.com>
PR C++/12028
* valops.c (find_oload_champ_namespace_loop): removed incorrect
'old_cleanups' reassignment.
2010-09-22 Sami Wagiaalla <swagiaal@redhat.com>
* gdb.cp/pr12028.cc: New.
* gdb.cp/pr12028.exp: New.
commit 01a3616d4397e5cc80e024d1583e966706b66854
Author: Kai Tietz <kai.tietz@onevision.com>
Date: Wed Sep 22 14:19:34 2010 +0000
2010-09-22 Kai Tietz <kai.tietz@onevision.com>
* coffcode.h (sec_to_styp_flags): Adjust debug
sections to be conform to pe-coff specification
and avoid marking them as excluded.
(styp_to_sec_flags): Doing reverse mapping.
commit 59c9593474be8bba278d9361a689ebad4013e314
Author: Eli Zaretskii <eliz@gnu.org>
Date: Wed Sep 22 09:13:30 2010 +0000
gdb.texinfo (Values From Inferior): Clarify that
value.dynamic_type works only in C++ programs with RTTI.
commit 132173fd8d416c8f2f2f71410a51a5db5d322f50
Author: Kai Tietz <kai.tietz@onevision.com>
Date: Wed Sep 22 08:01:54 2010 +0000
2010-09-22 Kai Tietz <kai.tietz@onevision.com>
* peXXigen.c (_bfd_XXi_final_link_postscript):
Add handling for setting IAT directory entry.
commit f6333da5a82280bea786876098c03afcc2b0cce7
Author: gdbadmin <gdbadmin@sourceware.org>
Date: Wed Sep 22 00:00:33 2010 +0000
*** empty log message ***
commit 71fe0f1709007d0d57fb8d72cba05522eaa74ff1
Author: Alan Modra <amodra@bigpond.net.au>
Date: Wed Sep 22 00:00:06 2010 +0000
daily update
commit 3e6d829c6e8ff5fa42e0fddee02b35289b923192
Author: Mike Frysinger <vapier@gentoo.org>
Date: Tue Sep 21 06:04:21 2010 +0000
opcodes: blackfin: strip trailing whitespace
commit 542a3569b097c18cf0022684ff7a86fe29d55901
Author: gdbadmin <gdbadmin@sourceware.org>
Date: Tue Sep 21 00:00:33 2010 +0000
*** empty log message ***
commit 573c1119b57082cf461812195dda577cea7b0bb8
Author: Alan Modra <amodra@bigpond.net.au>
Date: Tue Sep 21 00:00:05 2010 +0000
daily update
commit f521e4e01ae86e32bf3372c62c2f1a0d4c18be96
Author: Richard Henderson <rth@redhat.com>
Date: Mon Sep 20 16:08:59 2010 +0000
Use bfd_elf_generic_reloc for alpha-elf.
-----------------------------------------------------------------------
Summary of changes:
bfd/ChangeLog | 44 ++++
bfd/bfd-in2.h | 1 +
bfd/coffcode.h | 45 +++--
bfd/cpu-d10v.c | 20 +-
bfd/elf.c | 2 +-
bfd/elf32-arm.c | 4 +-
bfd/elf32-cris.c | 2 +-
bfd/elf32-hppa.c | 4 +-
bfd/elf32-i370.c | 2 +-
bfd/elf32-m32r.c | 2 +-
bfd/elf32-m68k.c | 4 +-
bfd/elf32-microblaze.c | 4 +-
bfd/elf32-ppc.c | 10 +-
bfd/elf32-score.c | 6 +-
bfd/elf32-score7.c | 6 +-
bfd/elf32-sh.c | 2 +-
bfd/elf32-tic6x.c | 26 +++
bfd/elf32-vax.c | 2 +-
bfd/elf32-xtensa.c | 2 +-
bfd/elf64-alpha.c | 74 ++++----
bfd/elf64-hppa.c | 2 +-
bfd/elf64-mips.c | 2 +-
bfd/elf64-ppc.c | 14 +-
bfd/elf64-sparc.c | 2 +-
bfd/elfcode.h | 2 +-
bfd/elflink.c | 14 +-
bfd/elfxx-ia64.c | 4 +-
bfd/elfxx-mips.c | 8 +-
bfd/peXXigen.c | 43 ++++
bfd/version.h | 2 +-
gdb/ChangeLog | 83 ++++++++
gdb/ada-tasks.c | 15 +-
gdb/amd64-linux-nat.c | 20 +-
gdb/configure | 26 ++-
gdb/configure.ac | 20 ++-
gdb/doc/ChangeLog | 9 +
gdb/doc/gdb.texinfo | 53 ++++-
gdb/dwarf2read.c | 48 +++--
gdb/gdbserver/ChangeLog | 9 +
gdb/gdbserver/linux-x86-low.c | 20 +-
gdb/infrun.c | 58 +++++-
gdb/main.c | 6 +-
gdb/objfiles.c | 9 +-
gdb/objfiles.h | 45 ++++-
gdb/python/py-auto-load.c | 2 -
gdb/python/py-objfile.c | 2 +-
gdb/python/py-progspace.c | 2 +-
gdb/testsuite/ChangeLog | 30 +++
gdb/testsuite/gdb.base/siginfo-infcall.c | 79 +++++++
gdb/testsuite/gdb.base/siginfo-infcall.exp | 47 ++++
gdb/testsuite/gdb.cp/pr12028.cc | 21 ++
gdb/testsuite/gdb.cp/pr12028.exp | 29 +++
gdb/testsuite/gdb.dwarf2/dw2-const.S | 224 ++++++++++++++++++++
gdb/testsuite/gdb.dwarf2/dw2-const.exp | 46 ++++
gdb/testsuite/gdb.fortran/module.exp | 2 +
gdb/testsuite/gdb.fortran/module.f90 | 2 +
gdb/valops.c | 4 +-
gdb/version.in | 2 +-
include/ChangeLog | 13 ++
include/opcode/ChangeLog | 31 +++
include/opcode/arm.h | 31 +++-
include/opcode/bfin.h | 170 +++++++++------
opcodes/ChangeLog | 103 +++++++++
opcodes/arm-dis.c | 177 ++++++++++++++--
opcodes/bfin-dis.c | 317 ++++++++++++++++++++--------
sim/rx/ChangeLog | 14 ++
sim/rx/cpu.h | 1 +
sim/rx/fpu.c | 1 +
sim/rx/gdb-if.c | 1 +
sim/rx/load.c | 3 +
sim/rx/misc.c | 1 +
sim/rx/rx.c | 14 ++-
sim/rx/syscalls.c | 1 +
73 files changed, 1781 insertions(+), 365 deletions(-)
create mode 100644 gdb/testsuite/gdb.base/siginfo-infcall.c
create mode 100644 gdb/testsuite/gdb.base/siginfo-infcall.exp
create mode 100644 gdb/testsuite/gdb.cp/pr12028.cc
create mode 100644 gdb/testsuite/gdb.cp/pr12028.exp
create mode 100644 gdb/testsuite/gdb.dwarf2/dw2-const.S
create mode 100644 gdb/testsuite/gdb.dwarf2/dw2-const.exp
First 500 lines of diff:
diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 545c603..b281a04 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,47 @@
+2010-09-24 Thomas Schwinge <thomas@codesourcery.com>
+
+ * elf32-arm.c, elf32-cris.c, elf32-hppa.c, elf32-i370.c, elf32-m32r.c,
+ elf32-m68k.c, elf32-microblaze.c, elf32-ppc.c, elf32-score.c,
+ elf32-score7.c, elf32-sh.c, elf32-vax.c, elf32-xtensa.c, elf64-alpha.c,
+ elf64-hppa.c, elf64-mips.c, elf64-ppc.c, elf64-sparc.c, elfcode.h,
+ elflink.c, elfxx-ia64.c, elfxx-mips.c: Use STN_UNDEF when referring to
+ the zero symbol index.
+
+ * elflink.c (bfd_elf_reloc_symbol_deleted_p): Compare the symbol index
+ to STN_UNDEF, not SHN_UNDEF.
+
+2010-09-23 Bernd Schmidt <bernds@codesourcery.com>
+
+ * elf32-tic6x.c (elf32_tic6x_fake_sections): New function.
+ (elf_backend_fake_sections): Define.
+
+2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
+ * bfd-in2.h (BFD_RELOC_ARM_HVC): New enum value.
+
+2010-09-23 Alan Modra <amodra@gmail.com>
+
+ * cpu-d10v.c: Make bits_per_address 18 for all arch_info entries.
+
+2010-09-23 Alan Modra <amodra@gmail.com>
+
+ * elf.c (_bfd_elf_init_private_section_data): Allow for SEC_RELOC
+ difference between input and output section.
+
+2010-09-22 Kai Tietz <kai.tietz@onevision.com>
+
+ * coffcode.h (sec_to_styp_flags): Adjust debug
+ sections to be conform to pe-coff specification
+ and avoid marking them as excluded.
+ (styp_to_sec_flags): Doing reverse mapping.
+
+ * peXXigen.c (_bfd_XXi_final_link_postscript): Add handling for
+ setting IAT directory entry.
+
+2010-09-20 Richard Henderson <rth@redhat.com>
+
+ * elf64-alpha.c (elf64_alpha_howto_table): Use bfd_elf_generic_reloc.
+
2010-09-19 Richard Sandiford <rdsandiford@googlemail.com>
* elfxx-mips.c (mips_elf_link_hash_entry): Add got_only_for_calls.
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 0e7b337..4bd47ca 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -3166,6 +3166,7 @@ pc-relative or some form of GOT-indirect relocation. */
BFD_RELOC_ARM_T32_ADD_PC12,
BFD_RELOC_ARM_SHIFT_IMM,
BFD_RELOC_ARM_SMC,
+ BFD_RELOC_ARM_HVC,
BFD_RELOC_ARM_SWI,
BFD_RELOC_ARM_MULTI,
BFD_RELOC_ARM_CP_OFF_IMM,
diff --git a/bfd/coffcode.h b/bfd/coffcode.h
index 790908a..ff69704 100644
--- a/bfd/coffcode.h
+++ b/bfd/coffcode.h
@@ -636,6 +636,14 @@ static long
sec_to_styp_flags (const char *sec_name, flagword sec_flags)
{
long styp_flags = 0;
+ bfd_boolean is_dbg = FALSE;
+
+ if (CONST_STRNEQ (sec_name, DOT_DEBUG)
+#ifdef COFF_LONG_SECTION_NAMES
+ || CONST_STRNEQ (sec_name, GNU_LINKONCE_WI)
+#endif
+ || CONST_STRNEQ (sec_name, ".stab"))
+ is_dbg = TRUE;
/* caution: there are at least three groups of symbols that have
very similar bits and meanings: IMAGE_SCN*, SEC_*, and STYP_*.
@@ -646,16 +654,15 @@ sec_to_styp_flags (const char *sec_name, flagword sec_flags)
but there are more IMAGE_SCN_* flags. */
/* FIXME: There is no gas syntax to specify the debug section flag. */
- if (CONST_STRNEQ (sec_name, DOT_DEBUG)
- || CONST_STRNEQ (sec_name, GNU_LINKONCE_WI))
- sec_flags = SEC_DEBUGGING | SEC_READONLY;
+ if (is_dbg)
+ sec_flags = SEC_DEBUGGING | SEC_READONLY;
/* skip LOAD */
/* READONLY later */
/* skip RELOC */
if ((sec_flags & SEC_CODE) != 0)
styp_flags |= IMAGE_SCN_CNT_CODE;
- if ((sec_flags & SEC_DATA) != 0)
+ if ((sec_flags & (SEC_DATA | SEC_DEBUGGING)) != 0)
styp_flags |= IMAGE_SCN_CNT_INITIALIZED_DATA;
if ((sec_flags & SEC_ALLOC) != 0 && (sec_flags & SEC_LOAD) == 0)
styp_flags |= IMAGE_SCN_CNT_UNINITIALIZED_DATA; /* ==STYP_BSS */
@@ -666,9 +673,9 @@ sec_to_styp_flags (const char *sec_name, flagword sec_flags)
styp_flags |= IMAGE_SCN_LNK_COMDAT;
if ((sec_flags & SEC_DEBUGGING) != 0)
styp_flags |= IMAGE_SCN_MEM_DISCARDABLE;
- if ((sec_flags & SEC_EXCLUDE) != 0)
+ if ((sec_flags & SEC_EXCLUDE) != 0 && !is_dbg)
styp_flags |= IMAGE_SCN_LNK_REMOVE;
- if ((sec_flags & SEC_NEVER_LOAD) != 0)
+ if ((sec_flags & SEC_NEVER_LOAD) != 0 && !is_dbg)
styp_flags |= IMAGE_SCN_LNK_REMOVE;
/* skip IN_MEMORY */
/* skip SORT */
@@ -1120,7 +1127,14 @@ styp_to_sec_flags (bfd *abfd,
long styp_flags = internal_s->s_flags;
flagword sec_flags;
bfd_boolean result = TRUE;
+ bfd_boolean is_dbg = FALSE;
+ if (CONST_STRNEQ (name, DOT_DEBUG)
+#ifdef COFF_LONG_SECTION_NAMES
+ || CONST_STRNEQ (name, GNU_LINKONCE_WI)
+#endif
+ || CONST_STRNEQ (name, ".stab"))
+ is_dbg = TRUE;
/* Assume read only unless IMAGE_SCN_MEM_WRITE is specified. */
sec_flags = SEC_READONLY;
@@ -1190,27 +1204,30 @@ styp_to_sec_flags (bfd *abfd,
mean that a given section contains debug information. Thus
we only set the SEC_DEBUGGING flag on sections that we
recognise as containing debug information. */
- if (CONST_STRNEQ (name, DOT_DEBUG)
+ if (is_dbg
#ifdef _COMMENT
|| strcmp (name, _COMMENT) == 0
#endif
-#ifdef COFF_LONG_SECTION_NAMES
- || CONST_STRNEQ (name, GNU_LINKONCE_WI)
-#endif
- || CONST_STRNEQ (name, ".stab"))
- sec_flags |= SEC_DEBUGGING;
+ )
+ {
+ sec_flags |= SEC_DEBUGGING | SEC_READONLY;
+ }
break;
case IMAGE_SCN_MEM_SHARED:
sec_flags |= SEC_COFF_SHARED;
break;
case IMAGE_SCN_LNK_REMOVE:
- sec_flags |= SEC_EXCLUDE;
+ if (!is_dbg)
+ sec_flags |= SEC_EXCLUDE;
break;
case IMAGE_SCN_CNT_CODE:
sec_flags |= SEC_CODE | SEC_ALLOC | SEC_LOAD;
break;
case IMAGE_SCN_CNT_INITIALIZED_DATA:
- sec_flags |= SEC_DATA | SEC_ALLOC | SEC_LOAD;
+ if (is_dbg)
+ sec_flags |= SEC_DEBUGGING;
+ else
+ sec_flags |= SEC_DATA | SEC_ALLOC | SEC_LOAD;
break;
case IMAGE_SCN_CNT_UNINITIALIZED_DATA:
sec_flags |= SEC_ALLOC;
diff --git a/bfd/cpu-d10v.c b/bfd/cpu-d10v.c
index b69e840..b161115 100644
--- a/bfd/cpu-d10v.c
+++ b/bfd/cpu-d10v.c
@@ -1,5 +1,5 @@
/* BFD support for the D10V processor
- Copyright 1996, 1999, 2000, 2002, 2005, 2007
+ Copyright 1996, 1999, 2000, 2002, 2005, 2007, 2010
Free Software Foundation, Inc.
Contributed by Martin Hunt (hunt@cygnus.com).
@@ -27,7 +27,7 @@
static const bfd_arch_info_type d10v_ts3_info =
{
16, /* 16 bits in a word. */
- 16, /* 16 bits in an address. */
+ 18, /* really 16 bits in an address, but code has 18 bit range. */
8, /* 8 bits in a byte. */
bfd_arch_d10v,
bfd_mach_d10v_ts3,
@@ -42,14 +42,14 @@ static const bfd_arch_info_type d10v_ts3_info =
static const bfd_arch_info_type d10v_ts2_info =
{
- 16, /* 16 bits in a word. */
- 16, /* 16 bits in an address. */
- 8, /* 8 bits in a byte. */
+ 16,
+ 18,
+ 8,
bfd_arch_d10v,
bfd_mach_d10v_ts2,
"d10v",
"d10v:ts2",
- 4, /* Section alignment power. */
+ 4,
FALSE,
bfd_default_compatible,
bfd_default_scan,
@@ -58,14 +58,14 @@ static const bfd_arch_info_type d10v_ts2_info =
const bfd_arch_info_type bfd_d10v_arch =
{
- 16, /* 16 bits in a word. */
- 16, /* 16 bits in an address. */
- 8, /* 8 bits in a byte. */
+ 16,
+ 18,
+ 8,
bfd_arch_d10v,
bfd_mach_d10v,
"d10v",
"d10v",
- 4, /* Section alignment power. */
+ 4,
TRUE,
bfd_default_compatible,
bfd_default_scan,
diff --git a/bfd/elf.c b/bfd/elf.c
index 5ec92e9..fe5f19f 100644
--- a/bfd/elf.c
+++ b/bfd/elf.c
@@ -6110,7 +6110,7 @@ _bfd_elf_init_private_section_data (bfd *ibfd,
&& (osec->flags == isec->flags
|| (final_link
&& ((osec->flags ^ isec->flags)
- & ~ (SEC_LINK_ONCE | SEC_LINK_DUPLICATES)) == 0)))
+ & ~(SEC_LINK_ONCE | SEC_LINK_DUPLICATES | SEC_RELOC)) == 0)))
elf_section_type (osec) = elf_section_type (isec);
/* FIXME: Is this correct for all OS/PROC specific flags? */
diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
index 74fb855..2125582 100644
--- a/bfd/elf32-arm.c
+++ b/bfd/elf32-arm.c
@@ -9063,7 +9063,7 @@ elf32_arm_relocate_section (bfd * output_bfd,
name = bfd_section_name (input_bfd, sec);
}
- if (r_symndx != 0
+ if (r_symndx != STN_UNDEF
&& r_type != R_ARM_NONE
&& (h == NULL
|| h->root.type == bfd_link_hash_defined
@@ -10902,7 +10902,7 @@ elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
/* PR 9934: It is possible to have relocations that do not
refer to symbols, thus it is also possible to have an
object file containing relocations but no symbol table. */
- && (r_symndx > 0 || nsyms > 0))
+ && (r_symndx > STN_UNDEF || nsyms > 0))
{
(*_bfd_error_handler) (_("%B: bad symbol index: %d"), abfd,
r_symndx);
diff --git a/bfd/elf32-cris.c b/bfd/elf32-cris.c
index 71634c9..f3ed80d 100644
--- a/bfd/elf32-cris.c
+++ b/bfd/elf32-cris.c
@@ -1493,7 +1493,7 @@ cris_elf_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
case R_CRIS_16:
case R_CRIS_32:
if (info->shared
- && r_symndx != 0
+ && r_symndx != STN_UNDEF
&& (input_section->flags & SEC_ALLOC) != 0
&& ((r_type != R_CRIS_8_PCREL
&& r_type != R_CRIS_16_PCREL
diff --git a/bfd/elf32-hppa.c b/bfd/elf32-hppa.c
index 1a6fef8..3a3a355 100644
--- a/bfd/elf32-hppa.c
+++ b/bfd/elf32-hppa.c
@@ -4472,7 +4472,7 @@ static enum elf_reloc_type_class
elf32_hppa_reloc_type_class (const Elf_Internal_Rela *rela)
{
/* Handle TLS relocs first; we don't want them to be marked
- relative by the "if (ELF32_R_SYM (rela->r_info) == 0)"
+ relative by the "if (ELF32_R_SYM (rela->r_info) == STN_UNDEF)"
check below. */
switch ((int) ELF32_R_TYPE (rela->r_info))
{
@@ -4482,7 +4482,7 @@ elf32_hppa_reloc_type_class (const Elf_Internal_Rela *rela)
return reloc_class_normal;
}
- if (ELF32_R_SYM (rela->r_info) == 0)
+ if (ELF32_R_SYM (rela->r_info) == STN_UNDEF)
return reloc_class_relative;
switch ((int) ELF32_R_TYPE (rela->r_info))
diff --git a/bfd/elf32-i370.c b/bfd/elf32-i370.c
index 67e6598..01f9fb8 100644
--- a/bfd/elf32-i370.c
+++ b/bfd/elf32-i370.c
@@ -1183,7 +1183,7 @@ i370_elf_relocate_section (bfd *output_bfd,
case (int) R_I370_ADDR31:
case (int) R_I370_ADDR16:
if (info->shared
- && r_symndx != 0)
+ && r_symndx != STN_UNDEF)
{
Elf_Internal_Rela outrel;
bfd_byte *loc;
diff --git a/bfd/elf32-m32r.c b/bfd/elf32-m32r.c
index 28eff76..3df6add 100644
--- a/bfd/elf32-m32r.c
+++ b/bfd/elf32-m32r.c
@@ -2897,7 +2897,7 @@ m32r_elf_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
case R_M32R_HI16_ULO_RELA:
case R_M32R_LO16_RELA:
if (info->shared
- && r_symndx != 0
+ && r_symndx != STN_UNDEF
&& (input_section->flags & SEC_ALLOC) != 0
&& (( r_type != R_M32R_10_PCREL_RELA
&& r_type != R_M32R_18_PCREL_RELA
diff --git a/bfd/elf32-m68k.c b/bfd/elf32-m68k.c
index 7323612..8d1ee7f 100644
--- a/bfd/elf32-m68k.c
+++ b/bfd/elf32-m68k.c
@@ -4034,7 +4034,7 @@ elf_m68k_relocate_section (output_bfd, info, input_bfd, input_section,
case R_68K_PC16:
case R_68K_PC32:
if (info->shared
- && r_symndx != 0
+ && r_symndx != STN_UNDEF
&& (input_section->flags & SEC_ALLOC) != 0
&& (h == NULL
|| ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
@@ -4169,7 +4169,7 @@ elf_m68k_relocate_section (output_bfd, info, input_bfd, input_section,
return FALSE;
}
- if (r_symndx != 0
+ if (r_symndx != STN_UNDEF
&& r_type != R_68K_NONE
&& (h == NULL
|| h->root.type == bfd_link_hash_defined
diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
index a64926a..e260c55 100644
--- a/bfd/elf32-microblaze.c
+++ b/bfd/elf32-microblaze.c
@@ -1067,10 +1067,10 @@ microblaze_elf_relocate_section (bfd *output_bfd,
case (int) R_MICROBLAZE_64:
case (int) R_MICROBLAZE_32:
{
- /* r_symndx will be zero only for relocs against symbols
+ /* r_symndx will be STN_UNDEF (zero) only for relocs against symbols
from removed linkonce sections, or sections discarded by
a linker script. */
- if (r_symndx == 0 || (input_section->flags & SEC_ALLOC) == 0)
+ if (r_symndx == STN_UNDEF || (input_section->flags & SEC_ALLOC) == 0)
{
relocation += addend;
if (r_type == R_MICROBLAZE_32)
diff --git a/bfd/elf32-ppc.c b/bfd/elf32-ppc.c
index ef0e159..2b457d6 100644
--- a/bfd/elf32-ppc.c
+++ b/bfd/elf32-ppc.c
@@ -6985,9 +6985,9 @@ ppc_elf_relocate_section (bfd *output_bfd,
if (local_sections[r_symndx] == sec)
break;
if (r_symndx >= symtab_hdr->sh_info)
- r_symndx = 0;
+ r_symndx = STN_UNDEF;
rel->r_addend = htab->elf.tls_sec->vma + DTP_OFFSET;
- if (r_symndx != 0)
+ if (r_symndx != STN_UNDEF)
rel->r_addend -= (local_syms[r_symndx].st_value
+ sec->output_offset
+ sec->output_section->vma);
@@ -7053,9 +7053,9 @@ ppc_elf_relocate_section (bfd *output_bfd,
if (local_sections[r_symndx] == sec)
break;
if (r_symndx >= symtab_hdr->sh_info)
- r_symndx = 0;
+ r_symndx = STN_UNDEF;
rel->r_addend = htab->elf.tls_sec->vma + DTP_OFFSET;
- if (r_symndx != 0)
+ if (r_symndx != STN_UNDEF)
rel->r_addend -= (local_syms[r_symndx].st_value
+ sec->output_offset
+ sec->output_section->vma);
@@ -7658,7 +7658,7 @@ ppc_elf_relocate_section (bfd *output_bfd,
sym_name);
ret = FALSE;
}
- else if (r_symndx == 0 || bfd_is_abs_section (sec))
+ else if (r_symndx == STN_UNDEF || bfd_is_abs_section (sec))
;
else if (sec == NULL || sec->owner == NULL)
{
diff --git a/bfd/elf32-score.c b/bfd/elf32-score.c
index f1f1aae..fec177a 100644
--- a/bfd/elf32-score.c
+++ b/bfd/elf32-score.c
@@ -2126,7 +2126,7 @@ score_elf_final_link_relocate (reloc_howto_type *howto,
&& h != NULL
&& h->root.def_dynamic
&& !h->root.def_regular))
- && r_symndx != 0
+ && r_symndx != STN_UNDEF
&& (input_section->flags & SEC_ALLOC) != 0)
{
/* If we're creating a shared library, or this relocation is against a symbol
@@ -2139,8 +2139,8 @@ score_elf_final_link_relocate (reloc_howto_type *howto,
input_section))
return bfd_reloc_undefined;
}
- else if (r_symndx == 0)
- /* r_symndx will be zero only for relocs against symbols
+ else if (r_symndx == STN_UNDEF)
+ /* r_symndx will be STN_UNDEF (zero) only for relocs against symbols
from removed linkonce sections, or sections discarded by
a linker script. */
value = 0;
diff --git a/bfd/elf32-score7.c b/bfd/elf32-score7.c
index 85ce236..f780e56 100644
--- a/bfd/elf32-score7.c
+++ b/bfd/elf32-score7.c
@@ -2025,7 +2025,7 @@ score_elf_final_link_relocate (reloc_howto_type *howto,
&& h != NULL
&& h->root.def_dynamic
&& !h->root.def_regular))
- && r_symndx != 0
+ && r_symndx != STN_UNDEF
&& (input_section->flags & SEC_ALLOC) != 0)
{
/* If we're creating a shared library, or this relocation is against a symbol
@@ -2038,8 +2038,8 @@ score_elf_final_link_relocate (reloc_howto_type *howto,
input_section))
return bfd_reloc_undefined;
}
- else if (r_symndx == 0)
- /* r_symndx will be zero only for relocs against symbols
+ else if (r_symndx == STN_UNDEF)
+ /* r_symndx will be STN_UNDEF (zero) only for relocs against symbols
from removed linkonce sections, or sections discarded by
a linker script. */
value = 0;
diff --git a/bfd/elf32-sh.c b/bfd/elf32-sh.c
index 023ed7e..4937643 100644
--- a/bfd/elf32-sh.c
+++ b/bfd/elf32-sh.c
@@ -4405,7 +4405,7 @@ sh_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
&& (h == NULL
|| ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
|| h->root.type != bfd_link_hash_undefweak)
- && r_symndx != 0
+ && r_symndx != STN_UNDEF
&& (input_section->flags & SEC_ALLOC) != 0
&& !is_vxworks_tls
&& (r_type == R_SH_DIR32
diff --git a/bfd/elf32-tic6x.c b/bfd/elf32-tic6x.c
index 3815ff1..ed3d3d9 100644
--- a/bfd/elf32-tic6x.c
+++ b/bfd/elf32-tic6x.c
@@ -1348,6 +1348,31 @@ elf32_tic6x_set_use_rela_p (bfd *abfd, bfd_boolean use_rela_p)
}
static bfd_boolean
+elf32_tic6x_fake_sections (bfd *abfd,
+ Elf_Internal_Shdr *hdr ATTRIBUTE_UNUSED,
+ asection *sec)
+{
+ /* The generic elf_fake_sections will set up REL_HDR using the
+ default kind of relocations. But, we may actually need both
+ kinds of relocations, so we set up the second header here. */
+ if ((sec->flags & SEC_RELOC) != 0)
+ {
+ struct bfd_elf_section_data *esd;
+ bfd_size_type amt = sizeof (Elf_Internal_Shdr);
+
+ esd = elf_section_data (sec);
+ BFD_ASSERT (esd->rel_hdr2 == NULL);
+ esd->rel_hdr2 = bfd_zalloc (abfd, amt);
+ if (!esd->rel_hdr2)
+ return FALSE;
+ _bfd_elf_init_reloc_shdr (abfd, esd->rel_hdr2, sec,
+ !sec->use_rela_p);
+ }
+
+ return TRUE;
+}
+
+static bfd_boolean
elf32_tic6x_mkobject (bfd *abfd)
{
bfd_boolean ret;
@@ -1765,6 +1790,7 @@ elf32_tic6x_merge_private_bfd_data (bfd *ibfd, bfd *obfd)
#define elf_backend_default_use_rela_p 1
#define elf_backend_may_use_rel_p 1
#define elf_backend_may_use_rela_p 1
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