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From: jkratoch@sourceware.org
To: archer-commits@sourceware.org
Subject: [SCM] master: Merge remote-tracking branch 'gdb/master'
Date: Wed, 16 Mar 2011 07:11:00 -0000 [thread overview]
Message-ID: <20110316071059.13268.qmail@sourceware.org> (raw)
The branch, master has been updated
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- Log -----------------------------------------------------------------
commit c695bf2d9e45077584c648925b2f213f40c87669
Merge: 4f8d91f fb4c421
Author: Jan Kratochvil <jan.kratochvil@redhat.com>
Date: Wed Mar 16 08:10:51 2011 +0100
Merge remote-tracking branch 'gdb/master'
commit fb4c421cf68863046781cd9f70499b2c02c47fc0
Author: gdbadmin <gdbadmin@sourceware.org>
Date: Wed Mar 16 00:00:32 2011 +0000
*** empty log message ***
commit 3f7dcbfdae07840c89cd55e1a49348d1c6a187ea
Author: Alan Modra <amodra@bigpond.net.au>
Date: Tue Mar 15 23:00:05 2011 +0000
daily update
commit fe463b4c6e9c0a288ab586f84526b7a12f60806c
Author: andreast <andreast>
Date: Tue Mar 15 21:03:42 2011 +0000
2011-03-15 Andreas Tobler <andreast@fgznet.ch>
* gdb.base/jit-main.c: Define ElfW for non glibc elf targets.
commit 2ee1ea9c534369870d4043bb3e8d4f81a594452d
Author: Mike Frysinger <vapier@gentoo.org>
Date: Tue Mar 15 21:01:44 2011 +0000
sim: bfin: add GPIO device simulation
This takes care of the MMR interface and pushing up interrupts.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
commit 1c568374181fd7b1172561ce8d1a882d9fe0921c
Author: andreast <andreast>
Date: Tue Mar 15 21:01:37 2011 +0000
2011-03-15 Andreas Tobler <andreast@fgznet.ch>
* MAINTAINERS: Add myself for write after approval privileges.
commit 52c4c65117f334eaffd728d7652a66fc9c8ee763
Author: Mike Frysinger <vapier@gentoo.org>
Date: Tue Mar 15 20:55:11 2011 +0000
sim: bfin: fix brace style
commit 7196c5630d1f71b9428ed1245dbb1fb4f7c4cbc1
Author: Mike Frysinger <vapier@gentoo.org>
Date: Tue Mar 15 20:44:09 2011 +0000
sim: bfin: fix brace style
commit 894e4cb17dcec5279d6a634d4396194839aaa372
Author: Mike Frysinger <vapier@gentoo.org>
Date: Tue Mar 15 20:55:11 2011 +0000
sim: bfin: fix brace style
commit 164fe3906c67abc7cd79f0f6840ba936be25c5c8
Author: Mike Frysinger <vapier@gentoo.org>
Date: Tue Mar 15 20:44:09 2011 +0000
sim: bfin: fix brace style
commit 460390c42916c9e4615c308a28571377408b0de6
Author: Mike Frysinger <vapier@gentoo.org>
Date: Tue Mar 15 20:10:40 2011 +0000
sim: bfin: handle AZ updates with 16bit adds/subs
We weren't updating AZ when doing a 16bit add or sub insn. Implement it.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
commit 42ca845af2fa8a1f179d962f8d6b6f1eb1f785de
Author: Mike Frysinger <vapier@gentoo.org>
Date: Tue Mar 15 20:10:12 2011 +0000
sim: bfin: skip acc/ASTAT updates for moves
No point in moving unchanged acc values to the acc regs, and avoid
updating the acc ASTAT bits when only reading. This fixes incorrect
changing of the ASTAT bits when they're only being read.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
commit 47f7bb8721a67744f6c986221fdcdb5daab55465
Author: Mike Frysinger <vapier@gentoo.org>
Date: Tue Mar 15 20:09:39 2011 +0000
sim: bfin: handle AN (negative overflows) in dsp mult insns
The current dsp mult handler does not take care of overflows which turn
values negative (and thus set AN in ASTAT). So implement it.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
commit 7913e35d72358f84d0d8e77bac6d2c21e3eb4621
Author: Mike Frysinger <vapier@gentoo.org>
Date: Tue Mar 15 20:09:09 2011 +0000
sim: bfin: handle V overflows in dsp mult insns
The current dsp mult handler does not take care of overflows and updating
the V ASTAT bit. So implement it.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
commit 83e6f766ec3a2aa165aaf173b6487d1e0107ca2c
Author: Mike Frysinger <vapier@gentoo.org>
Date: Tue Mar 15 20:08:27 2011 +0000
sim: bfin: decode ASTAT on failure
When testing ASTAT regs, specific bit differences carry a lot more meaning
than when checking the value of a data register. So automatically decode
the bits of the two values and print things out so that people don't have
to manually do it themselves every time.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
commit 80c402fb208e60fcffd08e109f7af198b50aaa0f
Author: Mike Frysinger <vapier@gentoo.org>
Date: Tue Mar 15 20:04:04 2011 +0000
sim: bfin: handle saturation with fract multiplications
The saturation behavior with fract modes differs from non-fract modes.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
commit c61443c395556911f937205e2c84ded4bb88322c
Author: Mike Frysinger <vapier@gentoo.org>
Date: Tue Mar 15 20:10:40 2011 +0000
sim: bfin: handle AZ updates with 16bit adds/subs
We weren't updating AZ when doing a 16bit add or sub insn. Implement it.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
commit 226a5ce35f72865c694f56064842a6d57ac41012
Author: Mike Frysinger <vapier@gentoo.org>
Date: Tue Mar 15 20:10:12 2011 +0000
sim: bfin: skip acc/ASTAT updates for moves
No point in moving unchanged acc values to the acc regs, and avoid
updating the acc ASTAT bits when only reading. This fixes incorrect
changing of the ASTAT bits when they're only being read.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
commit feaab51570a27b7db02de928a3fe9031259e8c6e
Author: Mike Frysinger <vapier@gentoo.org>
Date: Tue Mar 15 20:09:39 2011 +0000
sim: bfin: handle AN (negative overflows) in dsp mult insns
The current dsp mult handler does not take care of overflows which turn
values negative (and thus set AN in ASTAT). So implement it.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
commit 29b21c5eceb36bf1ae27f5f577f778e3363605cc
Author: Mike Frysinger <vapier@gentoo.org>
Date: Tue Mar 15 20:09:09 2011 +0000
sim: bfin: handle V overflows in dsp mult insns
The current dsp mult handler does not take care of overflows and updating
the V ASTAT bit. So implement it.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
commit ca69ef3f8024128be3533d8e3cf8239492073f5a
Author: Mike Frysinger <vapier@gentoo.org>
Date: Tue Mar 15 20:08:27 2011 +0000
sim: bfin: decode ASTAT on failure
When testing ASTAT regs, specific bit differences carry a lot more meaning
than when checking the value of a data register. So automatically decode
the bits of the two values and print things out so that people don't have
to manually do it themselves every time.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
commit 455c3aca4b6b03f634056d3a16c187fc6e8c09e8
Author: Mike Frysinger <vapier@gentoo.org>
Date: Tue Mar 15 20:04:04 2011 +0000
sim: bfin: handle saturation with fract multiplications
The saturation behavior with fract modes differs from non-fract modes.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
-----------------------------------------------------------------------
Summary of changes:
bfd/version.h | 2 +-
gdb/ChangeLog | 4 +
gdb/MAINTAINERS | 1 +
gdb/testsuite/ChangeLog | 4 +
gdb/testsuite/gdb.base/jit-main.c | 13 ++
gdb/version.in | 2 +-
sim/bfin/ChangeLog | 68 +++++++++
sim/bfin/Makefile.in | 4 +-
sim/bfin/bfin-sim.c | 177 ++++++++++++++++-------
sim/bfin/bfroms/bf50x-0.0.h | 3 +-
sim/bfin/bfroms/bf51x-0.0.h | 3 +-
sim/bfin/bfroms/bf51x-0.1.h | 3 +-
sim/bfin/bfroms/bf51x-0.2.h | 3 +-
sim/bfin/bfroms/bf526-0.0.h | 3 +-
sim/bfin/bfroms/bf526-0.1.h | 3 +-
sim/bfin/bfroms/bf527-0.0.h | 3 +-
sim/bfin/bfroms/bf527-0.1.h | 3 +-
sim/bfin/bfroms/bf527-0.2.h | 3 +-
sim/bfin/bfroms/bf533-0.1.h | 3 +-
sim/bfin/bfroms/bf533-0.2.h | 3 +-
sim/bfin/bfroms/bf533-0.3.h | 3 +-
sim/bfin/bfroms/bf537-0.0.h | 3 +-
sim/bfin/bfroms/bf537-0.1.h | 3 +-
sim/bfin/bfroms/bf537-0.3.h | 3 +-
sim/bfin/bfroms/bf538-0.0.h | 3 +-
sim/bfin/bfroms/bf54x-0.0.h | 3 +-
sim/bfin/bfroms/bf54x-0.1.h | 3 +-
sim/bfin/bfroms/bf54x-0.2.h | 3 +-
sim/bfin/bfroms/bf54x_l1-0.0.h | 3 +-
sim/bfin/bfroms/bf54x_l1-0.1.h | 3 +-
sim/bfin/bfroms/bf54x_l1-0.2.h | 3 +-
sim/bfin/bfroms/bf561-0.5.h | 3 +-
sim/bfin/bfroms/bf59x-0.0.h | 3 +-
sim/bfin/bfroms/bf59x_l1-0.1.h | 3 +-
sim/bfin/configure | 1 +
sim/bfin/configure.ac | 1 +
sim/bfin/dv-bfin_cec.c | 12 +-
sim/bfin/dv-bfin_ctimer.c | 9 +-
sim/bfin/dv-bfin_dma.c | 9 +-
sim/bfin/dv-bfin_dmac.c | 75 +++++++----
sim/bfin/dv-bfin_ebiu_amc.c | 12 +-
sim/bfin/dv-bfin_ebiu_ddrc.c | 6 +-
sim/bfin/dv-bfin_ebiu_sdc.c | 6 +-
sim/bfin/dv-bfin_emac.c | 9 +-
sim/bfin/dv-bfin_eppi.c | 9 +-
sim/bfin/dv-bfin_evt.c | 6 +-
sim/bfin/dv-bfin_gpio.c | 287 +++++++++++++++++++++++++++++++++++++
sim/bfin/dv-bfin_gpio.h | 27 ++++
sim/bfin/dv-bfin_gptimer.c | 9 +-
sim/bfin/dv-bfin_jtag.c | 6 +-
sim/bfin/dv-bfin_mmu.c | 6 +-
sim/bfin/dv-bfin_nfc.c | 9 +-
sim/bfin/dv-bfin_otp.c | 6 +-
sim/bfin/dv-bfin_pll.c | 9 +-
sim/bfin/dv-bfin_ppi.c | 9 +-
sim/bfin/dv-bfin_rtc.c | 9 +-
sim/bfin/dv-bfin_sic.c | 42 ++++--
sim/bfin/dv-bfin_spi.c | 9 +-
sim/bfin/dv-bfin_trace.c | 6 +-
sim/bfin/dv-bfin_twi.c | 9 +-
sim/bfin/dv-bfin_uart.c | 9 +-
sim/bfin/dv-bfin_uart2.c | 9 +-
sim/bfin/dv-bfin_wdog.c | 9 +-
sim/bfin/dv-bfin_wp.c | 6 +-
sim/bfin/dv-eth_phy.c | 6 +-
sim/bfin/gui.c | 18 ++-
sim/bfin/linux-fixed-code.h | 3 +-
sim/bfin/linux-targ-map.h | 12 +-
sim/bfin/machs.c | 197 ++++++++++++++++---------
69 files changed, 944 insertions(+), 273 deletions(-)
create mode 100644 sim/bfin/dv-bfin_gpio.c
create mode 100644 sim/bfin/dv-bfin_gpio.h
First 500 lines of diff:
diff --git a/bfd/version.h b/bfd/version.h
index 05c4cc6..8f2a14e 100644
--- a/bfd/version.h
+++ b/bfd/version.h
@@ -1,4 +1,4 @@
-#define BFD_VERSION_DATE 20110315
+#define BFD_VERSION_DATE 20110316
#define BFD_VERSION @bfd_version@
#define BFD_VERSION_STRING @bfd_version_package@ @bfd_version_string@
#define REPORT_BUGS_TO @report_bugs_to@
diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index dc48a2a..3f4998e 100644
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,3 +1,7 @@
+2011-03-15 Andreas Tobler <andreast@fgznet.ch>
+
+ * MAINTAINERS: Add myself for write after approval privileges.
+
2011-03-15 Michael Snyder <msnyder@vmware.com>
* frame.c (find_frame_sal): Assert sym is not null.
diff --git a/gdb/MAINTAINERS b/gdb/MAINTAINERS
index 3f5c696..cb8ed65 100644
--- a/gdb/MAINTAINERS
+++ b/gdb/MAINTAINERS
@@ -611,6 +611,7 @@ Gary Thomas gthomas@redhat.com
Jason Thorpe thorpej@netbsd.org
Caroline Tice ctice@apple.com
Kai Tietz kai.tietz@onevision.com
+Andreas Tobler andreast@fgznet.ch
Tom Tromey tromey@redhat.com
David Ung davidu@mips.com
D Venkatasubramanian dvenkat@noida.hcltech.com
diff --git a/gdb/testsuite/ChangeLog b/gdb/testsuite/ChangeLog
index 5f0cb6c..df52132 100644
--- a/gdb/testsuite/ChangeLog
+++ b/gdb/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2011-03-15 Andreas Tobler <andreast@fgznet.ch>
+
+ * gdb.base/jit-main.c: Define ElfW for non glibc elf targets.
+
2011-03-15 Phil Muldoon <pmuldoon@redhat.com>
* lib/gdb.exp (gdb_unload): Add another termination case.
diff --git a/gdb/testsuite/gdb.base/jit-main.c b/gdb/testsuite/gdb.base/jit-main.c
index 07ff198..b20c516 100644
--- a/gdb/testsuite/gdb.base/jit-main.c
+++ b/gdb/testsuite/gdb.base/jit-main.c
@@ -29,6 +29,19 @@
#include <sys/mman.h>
#include <sys/stat.h>
+/* ElfW is coming from linux. On other platforms it does not exist.
+ Let us define it here. */
+#ifndef ElfW
+# if (defined (_LP64) || defined (__LP64__))
+# define WORDSIZE 64
+# else
+# define WORDSIZE 32
+# endif /* _LP64 || __LP64__ */
+#define ElfW(type) _ElfW (Elf, WORDSIZE, type)
+#define _ElfW(e,w,t) _ElfW_1 (e, w, _##t)
+#define _ElfW_1(e,w,t) e##w##t
+#endif /* !ElfW */
+
typedef enum
{
JIT_NOACTION = 0,
diff --git a/gdb/version.in b/gdb/version.in
index 2905266..6c5c062 100644
--- a/gdb/version.in
+++ b/gdb/version.in
@@ -1 +1 @@
-7.2.50.20110315-cvs
+7.2.50.20110316-cvs
diff --git a/sim/bfin/ChangeLog b/sim/bfin/ChangeLog
index 8065fad..1dea111 100644
--- a/sim/bfin/ChangeLog
+++ b/sim/bfin/ChangeLog
@@ -1,3 +1,71 @@
+2011-03-15 Mike Frysinger <vapier@gentoo.org>
+
+ * Makefile.in (dv-bfin_gpio.o): New target.
+ * configure.ac (SIM_AC_OPTION_HARDWARE): Add bfin_gpio.
+ * configure: Regenerate.
+ * dv-bfin_gpio.c, dv-bfin_gpio.h: New files.
+ * machs.c: Include dv-bfin_gpio.h.
+ (bf50x_mem, bf51x_mem, bf52x_mem, bf531_mem, bf532_mem, bf533_mem,
+ bf534_mem, bf536_mem, bf537_mem, bf538_mem, bf561_mem, bf592_mem):
+ Delete GPIO memory stubs.
+ (bf50x_dev, bf512_dev, bf516_dev, bf522_dev, bf526_dev, bf533_dev,
+ bf534_dev, bf537_dev, bf538_dev, bf561_dev, bf592_dev): Add GPIO
+ peripheral devices.
+ (bfin_model_hw_tree_init): Hook up GPIO interrupts to SIC.
+
+2011-03-15 Mike Frysinger <vapier@gentoo.org>
+
+ * bfroms/bf50x-0.0.h, bfroms/bf51x-0.0.h, bfroms/bf51x-0.1.h,
+ bfroms/bf51x-0.2.h, bfroms/bf526-0.0.h, bfroms/bf526-0.1.h,
+ bfroms/bf527-0.0.h, bfroms/bf527-0.1.h, bfroms/bf527-0.2.h,
+ bfroms/bf533-0.1.h, bfroms/bf533-0.2.h, bfroms/bf533-0.3.h,
+ bfroms/bf537-0.0.h, bfroms/bf537-0.1.h, bfroms/bf537-0.3.h,
+ bfroms/bf538-0.0.h, bfroms/bf54x-0.0.h, bfroms/bf54x-0.1.h,
+ bfroms/bf54x-0.2.h, bfroms/bf54x_l1-0.0.h, bfroms/bf54x_l1-0.1.h,
+ bfroms/bf54x_l1-0.2.h, bfroms/bf561-0.5.h, bfroms/bf59x-0.0.h,
+ bfroms/bf59x_l1-0.1.h, dv-bfin_cec.c, dv-bfin_ctimer.c,
+ dv-bfin_dma.c, dv-bfin_dmac.c, dv-bfin_ebiu_amc.c,
+ dv-bfin_ebiu_ddrc.c, dv-bfin_ebiu_sdc.c, dv-bfin_emac.c,
+ dv-bfin_eppi.c, dv-bfin_evt.c, dv-bfin_gptimer.c, dv-bfin_jtag.c,
+ dv-bfin_mmu.c, dv-bfin_nfc.c, dv-bfin_otp.c, dv-bfin_pll.c,
+ dv-bfin_ppi.c, dv-bfin_rtc.c, dv-bfin_sic.c, dv-bfin_spi.c,
+ dv-bfin_trace.c, dv-bfin_twi.c, dv-bfin_uart.c, dv-bfin_uart2.c,
+ dv-bfin_wdog.c, dv-bfin_wp.c, dv-eth_phy.c, gui.c,
+ linux-fixed-code.h, linux-targ-map.h, machs.c, Makefile.in: Fix style.
+
+2011-03-15 Robin Getz <robin.getz@analog.com>
+
+ * bfin-sim.c (decode_dsp32alu_0): Set AZ based on val for 16bit adds
+ and subs.
+
+2011-03-15 Robin Getz <robin.getz@analog.com>
+
+ * bfin-sim.c (decode_macfunc): Move acc STOREs behind op != 3 check.
+
+2011-03-15 Robin Getz <robin.getz@analog.com>
+
+ * bfin-sim.c (decode_macfunc): New neg parameter. Set when the
+ high bit is set after extract_mult.
+ (decode_dsp32mac_0): Declare n_1 and n_0. Pass to the decode_macfunc
+ functions. Use these to update the AN bit.
+
+2011-03-15 Robin Getz <robin.getz@analog.com>
+
+ * bfin-sim.c (decode_dsp32mult_0): Declare v_i0 and v_i1. Pass to
+ the extract_mult functions. Include these when updating the V, VS,
+ and V_COPY bits.
+
+2011-03-15 Robin Getz <robin.getz@analog.com>
+
+ * bfin-sim.c (astat_names): New global bit array.
+ (decode_CC2stat_0): Delete local astat_name and astat_names.
+ (decode_psedodbg_assert_0): Move hardcoded offset into a variable.
+ Print out ASTAT bit values when checking an ASTAT register.
+
+2010-03-15 Robin Getz <robin.getz@analog.com>
+
+ * bfin-sim.c (extract_mult): Handle M_IU.
+
2011-03-05 Mike Frysinger <vapier@gentoo.org>
* Makefile.in, TODO, aclocal.m4, bfin-sim.c, bfin-sim.h,
diff --git a/sim/bfin/Makefile.in b/sim/bfin/Makefile.in
index 64f26d3..2276c52 100644
--- a/sim/bfin/Makefile.in
+++ b/sim/bfin/Makefile.in
@@ -53,7 +53,8 @@ $(srcdir)/linux-fixed-code.h: $(srcdir)/linux-fixed-code.s Makefile.in
$(AS_FOR_TARGET) $< -o linux-fixed-code.o
( set -e; \
echo "/* DO NOT EDIT: Autogenerated from linux-fixed-code.s. */"; \
- echo "static const unsigned char bfin_linux_fixed_code[] = {"; \
+ echo "static const unsigned char bfin_linux_fixed_code[] ="; \
+ echo "{"; \
$(OBJDUMP_FOR_TARGET) -d -z linux-fixed-code.o > $@.dis; \
sed -n $@.dis \
-e 's:^[^ ]* :0x:' \
@@ -78,6 +79,7 @@ dv-bfin_ebiu_sdc.o: dv-bfin_ebiu_sdc.c devices.h $(INCLUDE)
dv-bfin_emac.o: dv-bfin_emac.c devices.h $(INCLUDE)
dv-bfin_eppi.o: dv-bfin_eppi.c devices.h $(INCLUDE)
dv-bfin_evt.o: dv-bfin_evt.c devices.h $(INCLUDE)
+dv-bfin_gpio.o: dv-bfin_gpio.c devices.h $(INCLUDE)
dv-bfin_gptimer.o: dv-bfin_gptimer.c devices.h $(INCLUDE)
dv-bfin_jtag.o: dv-bfin_jtag.c devices.h $(INCLUDE)
dv-bfin_mmu.o: dv-bfin_mmu.c devices.h $(INCLUDE)
diff --git a/sim/bfin/bfin-sim.c b/sim/bfin/bfin-sim.c
index 6d9361e..6415388 100644
--- a/sim/bfin/bfin-sim.c
+++ b/sim/bfin/bfin-sim.c
@@ -75,6 +75,42 @@ unhandled_instruction (SIM_CPU *cpu, const char *insn)
illegal_instruction (cpu);
}
+static const char * const astat_names[] =
+{
+ [ 0] = "AZ",
+ [ 1] = "AN",
+ [ 2] = "AC0_COPY",
+ [ 3] = "V_COPY",
+ [ 4] = "ASTAT_4",
+ [ 5] = "CC",
+ [ 6] = "AQ",
+ [ 7] = "ASTAT_7",
+ [ 8] = "RND_MOD",
+ [ 9] = "ASTAT_9",
+ [10] = "ASTAT_10",
+ [11] = "ASTAT_11",
+ [12] = "AC0",
+ [13] = "AC1",
+ [14] = "ASTAT_14",
+ [15] = "ASTAT_15",
+ [16] = "AV0",
+ [17] = "AV0S",
+ [18] = "AV1",
+ [19] = "AV1S",
+ [20] = "ASTAT_20",
+ [21] = "ASTAT_21",
+ [22] = "ASTAT_22",
+ [23] = "ASTAT_23",
+ [24] = "V",
+ [25] = "VS",
+ [26] = "ASTAT_26",
+ [27] = "ASTAT_27",
+ [28] = "ASTAT_28",
+ [29] = "ASTAT_29",
+ [30] = "ASTAT_30",
+ [31] = "ASTAT_31",
+};
+
typedef enum
{
c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4,
@@ -1479,6 +1515,8 @@ extract_mult (SIM_CPU *cpu, bu64 res, int mmod, int MM,
case 0:
case M_IS:
return saturate_s32 (res, overflow);
+ case M_IU:
+ return saturate_u32 (res, overflow);
case M_FU:
if (MM)
return saturate_s32 (res, overflow);
@@ -1524,10 +1562,11 @@ extract_mult (SIM_CPU *cpu, bu64 res, int mmod, int MM,
static bu32
decode_macfunc (SIM_CPU *cpu, int which, int op, int h0, int h1, int src0,
- int src1, int mmod, int MM, int fullword, bu32 *overflow)
+ int src1, int mmod, int MM, int fullword, bu32 *overflow,
+ bu32 *neg)
{
bu64 acc;
- bu32 sat = 0, tsat;
+ bu32 sat = 0, tsat, ret;
/* Sign extend accumulator if necessary, otherwise unsigned. */
if (mmod == 0 || mmod == M_T || mmod == M_IS || mmod == M_ISS2
@@ -1620,15 +1659,31 @@ decode_macfunc (SIM_CPU *cpu, int which, int op, int h0, int h1, int src0,
default:
illegal_instruction (cpu);
}
+
+ if (acc & 0x8000000000ull)
+ *neg = 1;
+
+ STORE (AXREG (which), (acc >> 32) & 0xff);
+ STORE (AWREG (which), acc & 0xffffffff);
+ STORE (ASTATREG (av[which]), sat);
+ if (sat)
+ STORE (ASTATREG (avs[which]), sat);
}
- STORE (AXREG (which), (acc >> 32) & 0xff);
- STORE (AWREG (which), acc & 0xffffffff);
- STORE (ASTATREG (av[which]), sat);
- if (sat)
- STORE (ASTATREG (avs[which]), sat);
+ ret = extract_mult (cpu, acc, mmod, MM, fullword, overflow);
+
+ if (!fullword)
+ {
+ if (ret & 0x8000)
+ *neg = 1;
+ }
+ else
+ {
+ if (ret & 0x80000000)
+ *neg = 1;
+ }
- return extract_mult (cpu, acc, mmod, MM, fullword, overflow);
+ return ret;
}
bu32
@@ -2278,37 +2333,12 @@ decode_CC2stat_0 (SIM_CPU *cpu, bu16 iw0)
bu32 pval;
const char * const op_names[] = { "", "|", "&", "^" } ;
- const char *astat_name;
- const char * const astat_names[32] = {
- [ 0] = "AZ",
- [ 1] = "AN",
- [ 2] = "AC0_COPY",
- [ 3] = "V_COPY",
- [ 5] = "CC",
- [ 6] = "AQ",
- [ 8] = "RND_MOD",
- [12] = "AC0",
- [13] = "AC1",
- [16] = "AV0",
- [17] = "AV0S",
- [18] = "AV1",
- [19] = "AV1S",
- [24] = "V",
- [25] = "VS",
- };
- astat_name = astat_names[cbit];
- if (!astat_name)
- {
- static char astat_bit[12];
- sprintf (astat_bit, "ASTAT[%i]", cbit);
- astat_name = astat_bit;
- }
PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_CC2stat);
TRACE_EXTRACT (cpu, "%s: D:%i op:%i cbit:%i", __func__, D, op, cbit);
- TRACE_INSN (cpu, "%s %s= %s;", D ? astat_name : "CC",
- op_names[op], D ? "CC" : astat_name);
+ TRACE_INSN (cpu, "%s %s= %s;", D ? astat_names[cbit] : "CC",
+ op_names[op], D ? "CC" : astat_names[cbit]);
/* CC = CC; is invalid. */
if (cbit == 5)
@@ -2335,10 +2365,7 @@ decode_CC2stat_0 (SIM_CPU *cpu, bu16 iw0)
case 2: pval &= CCREG; break;
case 3: pval ^= CCREG; break;
}
- if (astat_names[cbit])
- TRACE_REGISTER (cpu, "wrote ASTAT[%s] = %i", astat_name, pval);
- else
- TRACE_REGISTER (cpu, "wrote %s = %i", astat_name, pval);
+ TRACE_REGISTER (cpu, "wrote ASTAT[%s] = %i", astat_names[cbit], pval);
SET_ASTAT ((ASTAT & ~(1 << cbit)) | (pval << cbit));
}
}
@@ -3692,7 +3719,7 @@ decode_dsp32mac_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
bu32 res = DREG (dst);
- bu32 v_i = 0, zero = 0;
+ bu32 v_i = 0, zero = 0, n_1 = 0, n_0 = 0;
static const char * const ops[] = { "=", "+=", "-=" };
char _buf[128], *buf = _buf;
@@ -3717,7 +3744,7 @@ decode_dsp32mac_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
if (w1 == 1 || op1 != 3)
{
bu32 res1 = decode_macfunc (cpu, 1, op1, h01, h11, src0,
- src1, mmod, MM, P, &v_i);
+ src1, mmod, MM, P, &v_i, &n_1);
if (w1)
buf += sprintf (buf, P ? "R%i" : "R%i.H", dst + P);
@@ -3763,7 +3790,7 @@ decode_dsp32mac_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
if (w0 == 1 || op0 != 3)
{
bu32 res0 = decode_macfunc (cpu, 0, op0, h00, h10, src0,
- src1, mmod, 0, P, &v_i);
+ src1, mmod, 0, P, &v_i, &n_0);
if (w0)
buf += sprintf (buf, P ? "R%i" : "R%i.L", dst);
@@ -3812,8 +3839,16 @@ decode_dsp32mac_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
if (v_i)
SET_ASTATREG (vs, v_i);
}
- if (op0 == 3 || op1 == 3)
- SET_ASTATREG (az, zero);
+
+ if ((w0 == 1 && op0 == 3) || (w1 == 1 && op1 == 3))
+ {
+ SET_ASTATREG (az, zero);
+ if (!(w0 == 1 && op0 == 3))
+ n_0 = 0;
+ if (!(w1 == 1 && op1 == 3))
+ n_1 = 0;
+ SET_ASTATREG (an, n_1 | n_0);
+ }
}
static void
@@ -3841,7 +3876,7 @@ decode_dsp32mult_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
int h01 = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
bu32 res = DREG (dst);
- bu32 sat0 = 0, sat1 = 0;
+ bu32 sat0 = 0, sat1 = 0, v_i0 = 0, v_i1 = 0;
char _buf[128], *buf = _buf;
int _MM = MM;
@@ -3864,7 +3899,7 @@ decode_dsp32mult_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
if (w1)
{
bu64 r = decode_multfunc (cpu, h01, h11, src0, src1, mmod, MM, &sat1);
- bu32 res1 = extract_mult (cpu, r, mmod, MM, P, NULL);
+ bu32 res1 = extract_mult (cpu, r, mmod, MM, P, &v_i1);
buf += sprintf (buf, P ? "R%i" : "R%i.H", dst + P);
buf += sprintf (buf, " = R%i.%c * R%i.%c",
@@ -3892,7 +3927,7 @@ decode_dsp32mult_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
if (w0)
{
bu64 r = decode_multfunc (cpu, h00, h10, src0, src1, mmod, 0, &sat0);
- bu32 res0 = extract_mult (cpu, r, mmod, 0, P, NULL);
+ bu32 res0 = extract_mult (cpu, r, mmod, 0, P, &v_i0);
buf += sprintf (buf, P ? "R%i" : "R%i.L", dst);
buf += sprintf (buf, " = R%i.%c * R%i.%c",
@@ -3916,10 +3951,12 @@ decode_dsp32mult_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
if (w0 || w1)
{
- STORE (ASTATREG (v), sat0 | sat1);
- STORE (ASTATREG (v_copy), sat0 | sat1);
- if (sat0 | sat1)
- STORE (ASTATREG (vs), 1);
+ bu32 v = sat0 | sat1 | v_i0 | v_i1;
+
+ STORE (ASTATREG (v), v);
+ STORE (ASTATREG (v_copy), v);
+ if (v)
+ STORE (ASTATREG (vs), v);
}
}
@@ -4091,7 +4128,7 @@ decode_dsp32alu_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
SET_DREG_L (dst0, val);
SET_ASTATREG (an, val & 0x8000);
-
+ SET_ASTATREG (az, val == 0);
}
else if ((aop == 0 || aop == 2) && aopcde == 9 && s == 1)
{
@@ -5897,6 +5934,7 @@ decode_psedodbg_assert_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1, bu32 pc)
int dbgop = ((iw0 >> (PseudoDbg_Assert_dbgop_bits - 16)) & PseudoDbg_Assert_dbgop_mask);
int grp = ((iw0 >> (PseudoDbg_Assert_grp_bits - 16)) & PseudoDbg_Assert_grp_mask);
int regtest = ((iw0 >> (PseudoDbg_Assert_regtest_bits - 16)) & PseudoDbg_Assert_regtest_mask);
+ int offset;
bu16 actual;
bu32 val = reg_read (cpu, grp, regtest);
const char *reg_name = get_allreg_name (grp, regtest);
@@ -5910,22 +5948,51 @@ decode_psedodbg_assert_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1, bu32 pc)
{
dbg_name = dbgop == 0 ? "DBGA" : "DBGAL";
dbg_appd = dbgop == 0 ? ".L" : "";
- actual = val;
+ offset = 0;
}
else if (dbgop == 1 || dbgop == 3)
{
dbg_name = dbgop == 1 ? "DBGA" : "DBGAH";
dbg_appd = dbgop == 1 ? ".H" : "";
- actual = val >> 16;
+ offset = 16;
}
else
illegal_instruction (cpu);
+ actual = val >> offset;
+
TRACE_INSN (cpu, "%s (%s%s, 0x%x);", dbg_name, reg_name, dbg_appd, expected);
if (actual != expected)
{
- sim_io_printf (sd, "FAIL at %#x: %s (%s%s, 0x%04x), actual value %#x\n",
+ sim_io_printf (sd, "FAIL at %#x: %s (%s%s, 0x%04x); actual value %#x\n",
pc, dbg_name, reg_name, dbg_appd, expected, actual);
+
+ /* Decode the actual ASTAT bits that are different. */
+ if (grp == 4 && regtest == 6)
+ {
+ int i;
+
+ sim_io_printf (sd, "Expected ASTAT:\n");
+ for (i = 0; i < 16; ++i)
+ sim_io_printf (sd, " %8s%c%i%s",
+ astat_names[i + offset],
+ (((expected >> i) & 1) != ((actual >> i) & 1))
+ ? '!' : ' ',
+ (expected >> i) & 1,
+ i == 7 ? "\n" : "");
+ sim_io_printf (sd, "\n");
+
+ sim_io_printf (sd, "Actual ASTAT:\n");
+ for (i = 0; i < 16; ++i)
+ sim_io_printf (sd, " %8s%c%i%s",
+ astat_names[i + offset],
+ (((expected >> i) & 1) != ((actual >> i) & 1))
+ ? '!' : ' ',
+ (actual >> i) & 1,
+ i == 7 ? "\n" : "");
+ sim_io_printf (sd, "\n");
+ }
+
cec_exception (cpu, VEC_SIM_DBGA);
SET_DREG (0, 1);
}
diff --git a/sim/bfin/bfroms/bf50x-0.0.h b/sim/bfin/bfroms/bf50x-0.0.h
index 00dcc10..c5dfcda 100644
--- a/sim/bfin/bfroms/bf50x-0.0.h
hooks/post-receive
--
Repository for Project Archer.
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