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From: pmuldoon@sourceware.org
To: archer-commits@sourceware.org
Subject: [SCM] archer-pmuldoon-python-backtrace: Merge remote-tracking branch 'gdb/master' into archer-pmuldoon-python-backtrace
Date: Tue, 27 Mar 2012 16:42:00 -0000 [thread overview]
Message-ID: <20120327164230.10392.qmail@sourceware.org> (raw)
The branch, archer-pmuldoon-python-backtrace has been updated
via 20f87ab1f910cdebb5d23eb5e5db0d3647959cb0 (commit)
via 095df86ce5d49a046a33909f71a81c17b102da6b (commit)
via 4fffe3b0d1073f79e8ce64643f48a00160a49efb (commit)
via 19cf5a11f2e11dcd899d609095b00d4d6fe2f019 (commit)
via 704c705f1069d47eea11c2ac60dce9242e8df2d0 (commit)
via e10e2ede4e6478085578c776c369ce540389f087 (commit)
via 79be8325606facdce0467e5e1b54b30513f8f727 (commit)
via b0e5cb87d66e1c74613ba923664bef9547b96172 (commit)
via a5cb0e3d12758e08a1ccc7f6f73529bc102a6d31 (commit)
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- Log -----------------------------------------------------------------
commit 20f87ab1f910cdebb5d23eb5e5db0d3647959cb0
Merge: 6a48d61 095df86
Author: Phil Muldoon <pmuldoon@redhat.com>
Date: Tue Mar 27 17:42:15 2012 +0100
Merge remote-tracking branch 'gdb/master' into archer-pmuldoon-python-backtrace
commit 095df86ce5d49a046a33909f71a81c17b102da6b
Author: ozapawandeep <ozapawandeep>
Date: Tue Mar 27 15:46:27 2012 +0000
* arm-linux-tdep.c (arm_linux_init_abi): Call
set_gdbarch_process_record.
Initialize `arm_swi_record' field.
* arm-tdep.c (arm_process_record): New function.
(deallocate_reg_mem): New function.
(decode_insn): New function.
(thumb_record_branch): New function.
(thumb_record_ldm_stm_swi(): New function.
(thumb_record_misc): New function.
(thumb_record_ld_st_stack): New function.
(thumb_record_ld_st_imm_offset): New function.
(thumb_record_ld_st_reg_offset(): New function.
(thumb_record_add_sub_cmp_mov): New function.
(thumb_record_shift_add_sub): New function.
(arm_record_coproc_data_proc): New function.
(arm_record_coproc): New function.
(arm_record_b_bl): New function.
(arm_record_ld_st_multiple): New function.
(arm_record_ld_st_reg_offset): New function.
(arm_record_ld_st_imm_offset): New function.
(arm_record_data_proc_imm): New function.
(arm_record_data_proc_misc_ld_str): New function.
(arm_record_extension_space): New function.
(arm_record_strx): New function.
(sbo_sbz): New function.
(struct insn_decode_record): New structure for arm insn record.
(REG_ALLOC): New macro for reg allocations.
(MEM_ALLOC): New macro for memory allocations.
* arm-tdep.h (struct gdbarch_tdep): New field 'arm_swi_record'
commit 4fffe3b0d1073f79e8ce64643f48a00160a49efb
Author: Andreas Schwab <schwab@suse.de>
Date: Tue Mar 27 08:15:16 2012 +0000
* m68klinux-nat.c (fetch_register): Fix strict-aliasing violation.
(store_register): Likewise.
commit 19cf5a11f2e11dcd899d609095b00d4d6fe2f019
Author: Mike Frysinger <vapier@gentoo.org>
Date: Tue Mar 27 04:18:05 2012 +0000
sim: add bugzilla marking
commit 704c705f1069d47eea11c2ac60dce9242e8df2d0
Author: gdbadmin <gdbadmin@sourceware.org>
Date: Tue Mar 27 00:00:32 2012 +0000
*** empty log message ***
commit e10e2ede4e6478085578c776c369ce540389f087
Author: Alan Modra <amodra@bigpond.net.au>
Date: Mon Mar 26 23:00:04 2012 +0000
daily update
-----------------------------------------------------------------------
Summary of changes:
bfd/version.h | 2 +-
gdb/ChangeLog | 48 +
gdb/MAINTAINERS | 2 +-
gdb/NEWS | 9 +-
gdb/arm-linux-tdep.c | 5 +
gdb/arm-tdep.c | 2061 +++++++++++++++++++++
gdb/arm-tdep.h | 5 +
gdb/gdbserver/ChangeLog | 21 +
gdb/gdbserver/linux-low.c | 36 +-
gdb/gdbserver/server.c | 4 -
gdb/m68klinux-nat.c | 10 +-
gdb/testsuite/ChangeLog | 4 +
gdb/testsuite/lib/gdb.exp | 5 +-
gdb/version.in | 2 +-
opcodes/ChangeLog | 4 +
opcodes/mips-dis.c | 8 +
sim/arm/ChangeLog | 4 +
sim/arm/aclocal.m4 | 11 +-
sim/arm/config.in | 32 +
sim/arm/configure | 304 ++--
sim/avr/ChangeLog | 4 +
sim/avr/aclocal.m4 | 11 +-
sim/avr/config.in | 32 +
sim/avr/configure | 304 ++--
sim/bfin/ChangeLog | 4 +
sim/bfin/aclocal.m4 | 11 +-
sim/bfin/config.in | 32 +
sim/bfin/configure | 370 +++--
sim/common/ChangeLog | 15 +
sim/common/acinclude.m4 | 1 +
sim/common/aclocal.m4 | 11 +-
sim/common/config.in | 32 +
sim/common/configure | 298 ++--
sim/common/nrun.c | 16 +
sim/common/sim-core.h | 8 +
sim/cr16/ChangeLog | 4 +
sim/cr16/aclocal.m4 | 11 +-
sim/cr16/config.in | 32 +
sim/cr16/configure | 376 +++--
sim/cris/ChangeLog | 4 +
sim/cris/aclocal.m4 | 11 +-
sim/cris/config.in | 35 +
sim/cris/configure | 376 +++--
sim/d10v/ChangeLog | 4 +
sim/d10v/aclocal.m4 | 11 +-
sim/d10v/config.in | 32 +
sim/d10v/configure | 376 +++--
sim/erc32/ChangeLog | 5 +
sim/erc32/aclocal.m4 | 11 +-
sim/erc32/config.in | 32 +
sim/erc32/configure | 298 ++--
sim/frv/ChangeLog | 4 +
sim/frv/aclocal.m4 | 11 +-
sim/frv/config.in | 32 +
sim/frv/configure | 304 ++--
sim/h8300/ChangeLog | 4 +
sim/h8300/aclocal.m4 | 11 +-
sim/h8300/config.in | 32 +
sim/h8300/configure | 304 ++--
sim/igen/ChangeLog | 4 +
sim/igen/configure | 116 +-
sim/iq2000/ChangeLog | 4 +
sim/iq2000/aclocal.m4 | 11 +-
sim/iq2000/config.in | 32 +
sim/iq2000/configure | 304 ++--
sim/lm32/ChangeLog | 4 +
sim/lm32/aclocal.m4 | 11 +-
sim/lm32/config.in | 35 +
sim/lm32/configure | 304 ++--
sim/m32c/ChangeLog | 4 +
sim/m32c/aclocal.m4 | 11 +-
sim/m32c/config.in | 34 +-
sim/m32c/configure | 304 ++--
sim/m32r/ChangeLog | 8 +
sim/m32r/aclocal.m4 | 11 +-
sim/m32r/config.in | 32 +
sim/m32r/configure | 304 ++--
sim/m32r/traps-linux.c | 1 -
sim/m68hc11/ChangeLog | 4 +
sim/m68hc11/aclocal.m4 | 11 +-
sim/m68hc11/config.in | 35 +
sim/m68hc11/configure | 376 +++--
sim/mcore/ChangeLog | 4 +
sim/mcore/aclocal.m4 | 11 +-
sim/mcore/config.in | 32 +
sim/mcore/configure | 304 ++--
sim/microblaze/ChangeLog | 4 +
sim/microblaze/aclocal.m4 | 11 +-
sim/microblaze/config.in | 32 +
sim/microblaze/configure | 304 ++--
sim/mips/ChangeLog | 4 +
sim/mips/aclocal.m4 | 11 +-
sim/mips/config.in | 32 +
sim/mips/configure | 378 +++--
sim/mn10300/ChangeLog | 4 +
sim/mn10300/aclocal.m4 | 11 +-
sim/mn10300/config.in | 35 +
sim/mn10300/configure | 376 +++--
sim/moxie/ChangeLog | 4 +
sim/moxie/aclocal.m4 | 11 +-
sim/moxie/config.in | 47 +
sim/moxie/configure | 304 ++--
sim/rl78/ChangeLog | 4 +
sim/rl78/aclocal.m4 | 11 +-
sim/rl78/config.in | 38 +-
sim/rl78/configure | 304 ++--
sim/rx/ChangeLog | 4 +
sim/rx/aclocal.m4 | 11 +-
sim/rx/config.in | 44 +-
sim/rx/configure | 310 ++--
sim/sh/ChangeLog | 4 +
sim/sh/aclocal.m4 | 11 +-
sim/sh/config.in | 32 +
sim/sh/configure | 304 ++--
sim/sh64/ChangeLog | 4 +
sim/sh64/aclocal.m4 | 11 +-
sim/sh64/config.in | 32 +
sim/sh64/configure | 304 ++--
sim/testsuite/ChangeLog | 4 +
sim/testsuite/sim/bfin/ChangeLog | 16 +
sim/testsuite/sim/bfin/allinsn.exp | 28 +
sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0.s | 2 +-
sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0_iutsh.s | 2 +-
sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0_m.s | 2 +-
sim/testsuite/sim/bfin/c_dsp32shift_vmaxvmax.s | 2 +-
sim/testsuite/sim/bfin/c_dsp32shiftim_af_s.s | 2 +-
sim/testsuite/sim/bfin/fact.s | 6 +-
sim/testsuite/sim/cris/ChangeLog | 9 +
sim/testsuite/sim/cris/c/clone5.c | 2 +-
sim/testsuite/sim/cris/c/fcntl1.c | 2 +-
sim/testsuite/sim/cris/c/kill2.c | 2 +-
sim/testsuite/sim/cris/c/kill3.c | 2 +-
sim/testsuite/sim/cris/c/mprotect1.c | 2 +-
sim/testsuite/sim/cris/c/pipe5.c | 2 +-
sim/testsuite/sim/cris/c/readlink5.c | 2 +-
sim/testsuite/sim/cris/c/rtsigprocmask1.c | 2 +-
sim/testsuite/sim/cris/c/rtsigsuspend1.c | 2 +-
sim/testsuite/sim/cris/c/sig10.c | 2 +-
sim/testsuite/sim/cris/c/sig11.c | 2 +-
sim/testsuite/sim/cris/c/sig3.c | 2 +-
sim/testsuite/sim/cris/c/sig4.c | 2 +-
sim/testsuite/sim/cris/c/sig5.c | 2 +-
sim/testsuite/sim/cris/c/sig6.c | 2 +-
sim/testsuite/sim/cris/c/sig7.c | 2 +-
sim/testsuite/sim/cris/c/sig8.c | 2 +-
sim/testsuite/sim/cris/c/sigreturn1.c | 2 +-
sim/testsuite/sim/cris/c/sigreturn2.c | 2 +-
sim/testsuite/sim/cris/c/syscall1.c | 2 +-
sim/testsuite/sim/cris/c/syscall2.c | 2 +-
sim/testsuite/sim/cris/c/syscall3.c | 2 +-
sim/testsuite/sim/cris/c/syscall4.c | 2 +-
sim/testsuite/sim/cris/c/sysctl2.c | 2 +-
sim/v850/ChangeLog | 4 +
sim/v850/aclocal.m4 | 11 +-
sim/v850/config.in | 32 +
sim/v850/configure | 376 +++--
156 files changed, 8445 insertions(+), 3452 deletions(-)
First 500 lines of diff:
diff --git a/bfd/version.h b/bfd/version.h
index afd724b..6bd584b 100644
--- a/bfd/version.h
+++ b/bfd/version.h
@@ -1,4 +1,4 @@
-#define BFD_VERSION_DATE 20120323
+#define BFD_VERSION_DATE 20120327
#define BFD_VERSION @bfd_version@
#define BFD_VERSION_STRING @bfd_version_package@ @bfd_version_string@
#define REPORT_BUGS_TO @report_bugs_to@
diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index 82fa1b4..4f74aa6 100644
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,3 +1,51 @@
+2012-03-27 Oza Pawandeep <oza.pawandeep@gmail.com>
+
+ * arm-linux-tdep.c (arm_linux_init_abi): Call
+ set_gdbarch_process_record.
+ Initialize `arm_swi_record' field.
+
+ * arm-tdep.c (arm_process_record): New function.
+ (deallocate_reg_mem): New function.
+ (decode_insn): New function.
+ (thumb_record_branch): New function.
+ (thumb_record_ldm_stm_swi(): New function.
+ (thumb_record_misc): New function.
+ (thumb_record_ld_st_stack): New function.
+ (thumb_record_ld_st_imm_offset): New function.
+ (thumb_record_ld_st_reg_offset(): New function.
+ (thumb_record_add_sub_cmp_mov): New function.
+ (thumb_record_shift_add_sub): New function.
+ (arm_record_coproc_data_proc): New function.
+ (arm_record_coproc): New function.
+ (arm_record_b_bl): New function.
+ (arm_record_ld_st_multiple): New function.
+ (arm_record_ld_st_reg_offset): New function.
+ (arm_record_ld_st_imm_offset): New function.
+ (arm_record_data_proc_imm): New function.
+ (arm_record_data_proc_misc_ld_str): New function.
+ (arm_record_extension_space): New function.
+ (arm_record_strx): New function.
+ (sbo_sbz): New function.
+ (struct insn_decode_record): New structure for arm insn record.
+ (REG_ALLOC): New macro for reg allocations.
+ (MEM_ALLOC): New macro for memory allocations.
+
+ * arm-tdep.h (struct gdbarch_tdep): New field 'arm_swi_record'
+
+2012-03-27 Andreas Schwab <schwab@linux-m68k.org>
+
+ * m68klinux-nat.c (fetch_register): Fix strict-aliasing violation.
+ (store_register): Likewise.
+
+2012-03-26 Oza Pawandeep <oza.pawandeep@gmail.com>
+
+ * MAINTAINERS (Write After Approval): Add myself to the list.
+
+2012-03-25 Jan Kratochvil <jan.kratochvil@redhat.com>
+
+ * NEWS (set breakpoint condition-evaluation): Change "gdb" to "host".
+ Describe also the option "auto".
+
2012-03-22 Richard Henderson <rth@redhat.com>
* sparc-linux-nat.c (_initialize_sparc_linux_nat): Fix prototype.
diff --git a/gdb/MAINTAINERS b/gdb/MAINTAINERS
index a6dceae..6dc5d67 100644
--- a/gdb/MAINTAINERS
+++ b/gdb/MAINTAINERS
@@ -649,7 +649,7 @@ Jie Zhang jzhang918@gmail.com
Wu Zhou woodzltc@cn.ibm.com
Yoshinori Sato ysato@users.sourceforge.jp
Hui Zhu teawater@gmail.com
-
+Oza Pawandeep oza.pawandeep@gmail.com
Past Maintainers
diff --git a/gdb/NEWS b/gdb/NEWS
index 696de32..8ff7876 100644
--- a/gdb/NEWS
+++ b/gdb/NEWS
@@ -3,6 +3,10 @@
*** Changes since GDB 7.4
+* GDB now supports reversible debugging on ARM, it allows you to
+ debug basic ARM and THUMB instructions, and provides
+ record/replay support.
+
* The option "symbol-reloading" has been deleted as it is no longer used.
* Python scripting
@@ -102,8 +106,9 @@ HP OpenVMS ia64 ia64-hp-openvms*
set breakpoint condition-evaluation
show breakpoint condition-evaluation
- Controls whether breakpoint conditions are evaluated by GDB ("gdb") or by
- GDBserver ("target").
+ Controls whether breakpoint conditions are evaluated by GDB ("host") or by
+ GDBserver ("target"). Default option "auto" chooses the most efficient
+ available mode.
This option can improve debugger efficiency depending on the speed of the
target.
diff --git a/gdb/arm-linux-tdep.c b/gdb/arm-linux-tdep.c
index e41205b..486e6ed 100644
--- a/gdb/arm-linux-tdep.c
+++ b/gdb/arm-linux-tdep.c
@@ -1155,8 +1155,13 @@ arm_linux_init_abi (struct gdbarch_info info,
simple_displaced_step_free_closure);
set_gdbarch_displaced_step_location (gdbarch, displaced_step_at_entry_point);
+ /* Reversible debugging, process record. */
+ set_gdbarch_process_record (gdbarch, arm_process_record);
tdep->syscall_next_pc = arm_linux_syscall_next_pc;
+
+ /* Syscall record. */
+ tdep->arm_swi_record = NULL;
}
/* Provide a prototype to silence -Wmissing-prototypes. */
diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index a3cdc7c..08c5ed4 100644
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -55,6 +55,8 @@
#include "gdb_assert.h"
#include "vec.h"
+#include "record.h"
+
#include "features/arm-with-m.c"
#include "features/arm-with-m-fpa-layout.c"
#include "features/arm-with-iwmmxt.c"
@@ -10444,3 +10446,2062 @@ vfp - VFP co-processor."),
NULL, /* FIXME: i18n: "ARM debugging is %s. */
&setdebuglist, &showdebuglist);
}
+
+/* ARM-reversible process record data structures. */
+
+#define ARM_INSN_SIZE_BYTES 4
+#define THUMB_INSN_SIZE_BYTES 2
+#define THUMB2_INSN_SIZE_BYTES 4
+
+
+#define INSN_S_L_BIT_NUM 20
+
+#define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
+ do \
+ { \
+ unsigned int reg_len = LENGTH; \
+ if (reg_len) \
+ { \
+ REGS = XNEWVEC (uint32_t, reg_len); \
+ memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
+ } \
+ } \
+ while (0)
+
+#define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
+ do \
+ { \
+ unsigned int mem_len = LENGTH; \
+ if (mem_len) \
+ { \
+ MEMS = XNEWVEC (struct arm_mem_r, mem_len); \
+ memcpy(&MEMS->len, &RECORD_BUF[0], \
+ sizeof(struct arm_mem_r) * LENGTH); \
+ } \
+ } \
+ while (0)
+
+/* Checks whether insn is already recorded or yet to be decoded. (boolean expression). */
+#define INSN_RECORDED(ARM_RECORD) \
+ (0 != (ARM_RECORD)->reg_rec_count || 0 != (ARM_RECORD)->mem_rec_count)
+
+/* ARM memory record structure. */
+struct arm_mem_r
+{
+ uint32_t len; /* Record length. */
+ CORE_ADDR addr; /* Memory address. */
+};
+
+/* ARM instruction record contains opcode of current insn
+ and execution state (before entry to decode_insn()),
+ contains list of to-be-modified registers and
+ memory blocks (on return from decode_insn()). */
+
+typedef struct insn_decode_record_t
+{
+ struct gdbarch *gdbarch;
+ struct regcache *regcache;
+ CORE_ADDR this_addr; /* Address of the insn being decoded. */
+ uint32_t arm_insn; /* Should accommodate thumb. */
+ uint32_t cond; /* Condition code. */
+ uint32_t opcode; /* Insn opcode. */
+ uint32_t decode; /* Insn decode bits. */
+ uint32_t mem_rec_count; /* No of mem records. */
+ uint32_t reg_rec_count; /* No of reg records. */
+ uint32_t *arm_regs; /* Registers to be saved for this record. */
+ struct arm_mem_r *arm_mems; /* Memory to be saved for this record. */
+} insn_decode_record;
+
+
+/* Checks ARM SBZ and SBO mandatory fields. */
+
+static int
+sbo_sbz (uint32_t insn, uint32_t bit_num, uint32_t len, uint32_t sbo)
+{
+ uint32_t ones = bits (insn, bit_num - 1, (bit_num -1) + (len - 1));
+
+ if (!len)
+ return 1;
+
+ if (!sbo)
+ ones = ~ones;
+
+ while (ones)
+ {
+ if (!(ones & sbo))
+ {
+ return 0;
+ }
+ ones = ones >> 1;
+ }
+ return 1;
+}
+
+typedef enum
+{
+ ARM_RECORD_STRH=1,
+ ARM_RECORD_STRD
+} arm_record_strx_t;
+
+typedef enum
+{
+ ARM_RECORD=1,
+ THUMB_RECORD,
+ THUMB2_RECORD
+} record_type_t;
+
+
+static int
+arm_record_strx (insn_decode_record *arm_insn_r, uint32_t *record_buf,
+ uint32_t *record_buf_mem, arm_record_strx_t str_type)
+{
+
+ struct regcache *reg_cache = arm_insn_r->regcache;
+ ULONGEST u_regval[2]= {0};
+
+ uint32_t reg_src1 = 0, reg_src2 = 0;
+ uint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0;
+ uint32_t opcode1 = 0;
+
+ arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
+ arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
+ opcode1 = bits (arm_insn_r->arm_insn, 20, 24);
+
+
+ if (14 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
+ {
+ /* 1) Handle misc store, immediate offset. */
+ immed_low = bits (arm_insn_r->arm_insn, 0, 3);
+ immed_high = bits (arm_insn_r->arm_insn, 8, 11);
+ reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
+ regcache_raw_read_unsigned (reg_cache, reg_src1,
+ &u_regval[0]);
+ if (ARM_PC_REGNUM == reg_src1)
+ {
+ /* If R15 was used as Rn, hence current PC+8. */
+ u_regval[0] = u_regval[0] + 8;
+ }
+ offset_8 = (immed_high << 4) | immed_low;
+ /* Calculate target store address. */
+ if (14 == arm_insn_r->opcode)
+ {
+ tgt_mem_addr = u_regval[0] + offset_8;
+ }
+ else
+ {
+ tgt_mem_addr = u_regval[0] - offset_8;
+ }
+ if (ARM_RECORD_STRH == str_type)
+ {
+ record_buf_mem[0] = 2;
+ record_buf_mem[1] = tgt_mem_addr;
+ arm_insn_r->mem_rec_count = 1;
+ }
+ else if (ARM_RECORD_STRD == str_type)
+ {
+ record_buf_mem[0] = 4;
+ record_buf_mem[1] = tgt_mem_addr;
+ record_buf_mem[2] = 4;
+ record_buf_mem[3] = tgt_mem_addr + 4;
+ arm_insn_r->mem_rec_count = 2;
+ }
+ }
+ else if (12 == arm_insn_r->opcode || 8 == arm_insn_r->opcode)
+ {
+ /* 2) Store, register offset. */
+ /* Get Rm. */
+ reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
+ /* Get Rn. */
+ reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
+ regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
+ regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
+ if (15 == reg_src2)
+ {
+ /* If R15 was used as Rn, hence current PC+8. */
+ u_regval[0] = u_regval[0] + 8;
+ }
+ /* Calculate target store address, Rn +/- Rm, register offset. */
+ if (12 == arm_insn_r->opcode)
+ {
+ tgt_mem_addr = u_regval[0] + u_regval[1];
+ }
+ else
+ {
+ tgt_mem_addr = u_regval[1] - u_regval[0];
+ }
+ if (ARM_RECORD_STRH == str_type)
+ {
+ record_buf_mem[0] = 2;
+ record_buf_mem[1] = tgt_mem_addr;
+ arm_insn_r->mem_rec_count = 1;
+ }
+ else if (ARM_RECORD_STRD == str_type)
+ {
+ record_buf_mem[0] = 4;
+ record_buf_mem[1] = tgt_mem_addr;
+ record_buf_mem[2] = 4;
+ record_buf_mem[3] = tgt_mem_addr + 4;
+ arm_insn_r->mem_rec_count = 2;
+ }
+ }
+ else if (11 == arm_insn_r->opcode || 15 == arm_insn_r->opcode
+ || 2 == arm_insn_r->opcode || 6 == arm_insn_r->opcode)
+ {
+ /* 3) Store, immediate pre-indexed. */
+ /* 5) Store, immediate post-indexed. */
+ immed_low = bits (arm_insn_r->arm_insn, 0, 3);
+ immed_high = bits (arm_insn_r->arm_insn, 8, 11);
+ offset_8 = (immed_high << 4) | immed_low;
+ reg_src1 = bits (arm_insn_r->arm_insn, 16, 19);
+ regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
+ /* Calculate target store address, Rn +/- Rm, register offset. */
+ if (15 == arm_insn_r->opcode || 6 == arm_insn_r->opcode)
+ {
+ tgt_mem_addr = u_regval[0] + offset_8;
+ }
+ else
+ {
+ tgt_mem_addr = u_regval[0] - offset_8;
+ }
+ if (ARM_RECORD_STRH == str_type)
+ {
+ record_buf_mem[0] = 2;
+ record_buf_mem[1] = tgt_mem_addr;
+ arm_insn_r->mem_rec_count = 1;
+ }
+ else if (ARM_RECORD_STRD == str_type)
+ {
+ record_buf_mem[0] = 4;
+ record_buf_mem[1] = tgt_mem_addr;
+ record_buf_mem[2] = 4;
+ record_buf_mem[3] = tgt_mem_addr + 4;
+ arm_insn_r->mem_rec_count = 2;
+ }
+ /* Record Rn also as it changes. */
+ *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19);
+ arm_insn_r->reg_rec_count = 1;
+ }
+ else if (9 == arm_insn_r->opcode || 13 == arm_insn_r->opcode
+ || 0 == arm_insn_r->opcode || 4 == arm_insn_r->opcode)
+ {
+ /* 4) Store, register pre-indexed. */
+ /* 6) Store, register post -indexed. */
+ reg_src1 = bits (arm_insn_r->arm_insn, 0, 3);
+ reg_src2 = bits (arm_insn_r->arm_insn, 16, 19);
+ regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
+ regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
+ /* Calculate target store address, Rn +/- Rm, register offset. */
+ if (13 == arm_insn_r->opcode || 4 == arm_insn_r->opcode)
+ {
+ tgt_mem_addr = u_regval[0] + u_regval[1];
+ }
+ else
+ {
+ tgt_mem_addr = u_regval[1] - u_regval[0];
+ }
+ if (ARM_RECORD_STRH == str_type)
+ {
+ record_buf_mem[0] = 2;
+ record_buf_mem[1] = tgt_mem_addr;
+ arm_insn_r->mem_rec_count = 1;
+ }
+ else if (ARM_RECORD_STRD == str_type)
+ {
+ record_buf_mem[0] = 4;
+ record_buf_mem[1] = tgt_mem_addr;
+ record_buf_mem[2] = 4;
+ record_buf_mem[3] = tgt_mem_addr + 4;
+ arm_insn_r->mem_rec_count = 2;
+ }
+ /* Record Rn also as it changes. */
+ *(record_buf) = bits (arm_insn_r->arm_insn, 16, 19);
+ arm_insn_r->reg_rec_count = 1;
+ }
+ return 0;
+}
+
+/* Handling ARM extension space insns. */
+
+static int
+arm_record_extension_space (insn_decode_record *arm_insn_r)
+{
+ uint32_t ret = 0; /* Return value: -1:record failure ; 0:success */
+ uint32_t opcode1 = 0, opcode2 = 0, insn_op1 = 0;
+ uint32_t record_buf[8], record_buf_mem[8];
+ uint32_t reg_src1 = 0;
+ uint32_t immed_high = 0, immed_low = 0,offset_8 = 0, tgt_mem_addr = 0;
+ struct regcache *reg_cache = arm_insn_r->regcache;
+ ULONGEST u_regval = 0;
+
+ gdb_assert (!INSN_RECORDED(arm_insn_r));
+ /* Handle unconditional insn extension space. */
+
+ opcode1 = bits (arm_insn_r->arm_insn, 20, 27);
+ opcode2 = bits (arm_insn_r->arm_insn, 4, 7);
+ if (arm_insn_r->cond)
+ {
+ /* PLD has no affect on architectural state, it just affects
+ the caches. */
+ if (5 == ((opcode1 & 0xE0) >> 5))
+ {
+ /* BLX(1) */
+ record_buf[0] = ARM_PS_REGNUM;
+ record_buf[1] = ARM_LR_REGNUM;
+ arm_insn_r->reg_rec_count = 2;
+ }
+ /* STC2, LDC2, MCR2, MRC2, CDP2: <TBD>, co-processor insn. */
+ }
+
+
+ opcode1 = bits (arm_insn_r->arm_insn, 25, 27);
+ if (3 == opcode1 && bit (arm_insn_r->arm_insn, 4))
+ {
+ ret = -1;
+ /* Undefined instruction on ARM V5; need to handle if later
+ versions define it. */
+ }
+
+ opcode1 = bits (arm_insn_r->arm_insn, 24, 27);
+ opcode2 = bits (arm_insn_r->arm_insn, 4, 7);
+ insn_op1 = bits (arm_insn_r->arm_insn, 20, 23);
+
+ /* Handle arithmetic insn extension space. */
+ if (!opcode1 && 9 == opcode2 && 1 != arm_insn_r->cond
+ && !INSN_RECORDED(arm_insn_r))
+ {
+ /* Handle MLA(S) and MUL(S). */
+ if (0 <= insn_op1 && 3 >= insn_op1)
+ {
+ record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
+ record_buf[1] = ARM_PS_REGNUM;
+ arm_insn_r->reg_rec_count = 2;
+ }
+ else if (4 <= insn_op1 && 15 >= insn_op1)
+ {
+ /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
+ record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
+ record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15);
+ record_buf[2] = ARM_PS_REGNUM;
+ arm_insn_r->reg_rec_count = 3;
+ }
+ }
+
+ opcode1 = bits (arm_insn_r->arm_insn, 26, 27);
+ opcode2 = bits (arm_insn_r->arm_insn, 23, 24);
+ insn_op1 = bits (arm_insn_r->arm_insn, 21, 22);
+
+ /* Handle control insn extension space. */
+
+ if (!opcode1 && 2 == opcode2 && !bit (arm_insn_r->arm_insn, 20)
+ && 1 != arm_insn_r->cond && !INSN_RECORDED(arm_insn_r))
+ {
+ if (!bit (arm_insn_r->arm_insn,25))
+ {
+ if (!bits (arm_insn_r->arm_insn, 4, 7))
+ {
+ if ((0 == insn_op1) || (2 == insn_op1))
+ {
+ /* MRS. */
+ record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
+ arm_insn_r->reg_rec_count = 1;
+ }
hooks/post-receive
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Repository for Project Archer.
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