From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 78849 invoked by alias); 2 Nov 2016 20:46:27 -0000 Mailing-List: contact archer-commits-help@sourceware.org; run by ezmlm Sender: Precedence: bulk List-Post: List-Help: List-Subscribe: Received: (qmail 78815 invoked by uid 9674); 2 Nov 2016 20:46:26 -0000 Date: Wed, 02 Nov 2016 20:46:00 -0000 Message-ID: <20161102204626.78774.qmail@sourceware.org> From: jkratoch@sourceware.org To: archer-commits@sourceware.org Subject: [SCM] users/jkratoch/dwarf5gcc-gdb: . X-Git-Refname: refs/heads/users/jkratoch/dwarf5gcc-gdb X-Git-Reftype: branch X-Git-Oldrev: 8ac14c4c6fc26c02b6333792728cbc0c0eece05a X-Git-Newrev: f3127892db71eac1c92d554b74e5023cc1ea8bbb X-SW-Source: 2016-q4/txt/msg00003.txt.bz2 List-Id: The branch, users/jkratoch/dwarf5gcc-gdb has been updated via f3127892db71eac1c92d554b74e5023cc1ea8bbb (commit) via 527ebef0eeae9a062efe77f4eeb2f1a006bc18d9 (commit) via 2e6305d981cdd51a7349fb82f83b00a9c52c81d1 (commit) via e23eba971dd409b999dd83d8df0f842680c1c642 (commit) via 4e56efac8b4d5e251e8edc13febec93992bd6eb4 (commit) via c50730217d606814cda69a2bb6975730c0f1ee63 (commit) via 7e3d947dd6ae45d71aa175b96fbd42a51e93b3f8 (commit) via de4bfa865e5ea54f2ab5b7af53e4abe825da699e (commit) via fb47deda560b754008c35b5ec13fe02ef0593019 (commit) via c646b02fdcae5f37bd88f33a0c4683ef13ad5c82 (commit) via 1964088538cbf9483a1c9f411ad9d9054ea7be90 (commit) from 8ac14c4c6fc26c02b6333792728cbc0c0eece05a (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email. - Log ----------------------------------------------------------------- commit f3127892db71eac1c92d554b74e5023cc1ea8bbb Author: Jan Kratochvil Date: Wed Nov 2 21:46:09 2016 +0100 . commit 527ebef0eeae9a062efe77f4eeb2f1a006bc18d9 Merge: 8ac14c4 2e6305d Author: Jan Kratochvil Date: Tue Nov 1 18:46:28 2016 +0100 Merge branch 'dwarf5gcc' into dwarf5gcc-gdb commit 2e6305d981cdd51a7349fb82f83b00a9c52c81d1 Merge: e64174f e23eba9 Author: Jan Kratochvil Date: Tue Nov 1 18:46:28 2016 +0100 Merge remote-tracking branch 'gdb/master' into dwarf5gcc commit e23eba971dd409b999dd83d8df0f842680c1c642 Author: Nick Clifton Date: Tue Nov 1 16:45:57 2016 +0000 Add support for RISC-V architecture. bfd * Makefile.am: Add entries for riscv32-elf and riscv64-elf. * config.bdf: Likewise. * configure.ac: Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * archures.c: Add bfd_riscv_arch. * reloc.c: Add riscv relocs. * targets.c: Add riscv_elf32_vec and riscv_elf64_vec. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elf-bfd.h: Add RISCV_ELF_DATA to enum elf_target_id. * elfnn-riscv.c: New file. * elfxx-riscv.c: New file. * elfxx-riscv.h: New file. binutils* readelf.c (guess_is_rela): Add EM_RISCV. (get_machine_name): Likewise. (dump_relocations): Add support for riscv relocations. (get_machine_flags): Add support for riscv flags. (is_32bit_abs_reloc): Add R_RISCV_32. (is_64bit_abs_reloc): Add R_RISCV_64. (is_none_reloc): Add R_RISCV_NONE. * testsuite/binutils-all/objdump.exp (cpus_expected): Add riscv. Expect the debug_ranges test to fail. gas * Makefile.am: Add riscv files. * Makefile.in: Regenerate. * NEWS: Mention the support for this architecture. * configure.in: Define a default architecture. * configure: Regenerate. * configure.tgt: Add entries for riscv. * doc/as.texinfo: Likewise. * testsuite/gas/all/gas.exp: Expect the redef tests to fail. * testsuite/gas/elf/elf.exp: Expect the groupauto tests to fail. * config/tc-riscv.c: New file. * config/tc-riscv.h: New file. * doc/c-riscv.texi: New file. * testsuite/gas/riscv: New directory. * testsuite/gas/riscv/riscv.exp: New file. * testsuite/gas/riscv/t_insns.d: New file. * testsuite/gas/riscv/t_insns.s: New file. ld * Makefile.am: Add riscv files. * Makefile.in: Regenerate. * NEWS: Mention the support for this target. * configure.tgt: Add riscv entries. * emulparams/elf32lriscv-defs.sh: New file. * emulparams/elf32lriscv.sh: New file. * emulparams/elf64lriscv-defs.sh: New file. * emulparams/elf64lriscv.sh: New file. * emultempl/riscvelf.em: New file. opcodes * configure.ac: Add entry for bfd_riscv_arch. * configure: Regenerate. * disassemble.c (disassembler): Add support for riscv. (disassembler_usage): Likewise. * riscv-dis.c: New file. * riscv-opc.c: New file. include * dis-asm.h: Add prototypes for print_insn_riscv and print_riscv_disassembler_options. * elf/riscv.h: New file. * opcode/riscv-opc.h: New file. * opcode/riscv.h: New file. commit 4e56efac8b4d5e251e8edc13febec93992bd6eb4 Author: GDB Administrator Date: Tue Nov 1 00:00:19 2016 +0000 Automatic date update in version.in commit c50730217d606814cda69a2bb6975730c0f1ee63 Author: Maciej W. Rozycki Date: Mon Oct 31 16:24:04 2016 +0000 Remove IRIX 5 _KMEMUSER workaround Complement commit 3831839c089c ("Delete IRIX support") and remove the IRIX 5 _KMEMUSER workaround from the `configure' script, as IRIX is no longer a supported host configuration. gdb/ * configure.ac : Remove _KMEMUSER workaround. * configure: Regenerate. * config.in: Regenerate. commit 7e3d947dd6ae45d71aa175b96fbd42a51e93b3f8 Author: Maciej W. Rozycki Date: Mon Oct 31 02:08:06 2016 +0000 MIPS: Remove remains of legacy remote target support Complement commit f7c382926d78 ("Remove support for "target m32rsdi" and "target mips/pmon/ddb/rockhopper/lsi"") and remove dead MIPS target code which used to support these legacy remote targets. gdb/ * mips-tdep.c (mips_r3041_reg_names): Remove. (mips_breakpoint_from_pc): Remove IDT and PMON breakpoint encodings. commit de4bfa865e5ea54f2ab5b7af53e4abe825da699e Author: Maciej W. Rozycki Date: Mon Oct 31 02:07:26 2016 +0000 MIPS: Remove remains of IRIX OS ABI support Complement commit 3831839c089c ("Delete IRIX support") and remove dead MIPS target IRIX OS ABI support code. gdb/ * defs.h (gdb_osabi): Remove GDB_OSABI_IRIX enum value. * osabi.c (gdb_osabi_names): Remove "Irix" entry. * mips-tdep.c (mips_irix_reg_names): Remove. (mips_register_type): Remove GDB_OSABI_IRIX code. (mips_pseudo_register_type): Likewise. (mips_breakpoint_from_pc): Likewise. (mips_gdbarch_init): Likewise. commit fb47deda560b754008c35b5ec13fe02ef0593019 Author: Thomas Preud'homme Date: Mon Oct 31 09:44:18 2016 +0000 Initialize input statement created in add_archive_member 2016-10-31 Thomas Preud'homme ld/ * ldmain.c (add_archive_element): Initialize input->header.type. * plugin.c (plugin_maybe_claim): Assert the statement is an input statement. commit c646b02fdcae5f37bd88f33a0c4683ef13ad5c82 Author: Alan Modra Date: Mon Oct 31 12:46:38 2016 +1030 Revert part "Set dynamic tag VMA and size from dynamic section when possible" PR 20748 * elf32-microblaze.c (microblaze_elf_finish_dynamic_sections): Revert 2016-05-13 change. commit 1964088538cbf9483a1c9f411ad9d9054ea7be90 Author: GDB Administrator Date: Mon Oct 31 00:00:22 2016 +0000 Automatic date update in version.in ----------------------------------------------------------------------- Summary of changes: bfd/ChangeLog | 25 + bfd/Makefile.am | 28 +- bfd/Makefile.in | 32 +- bfd/archures.c | 7 +- bfd/bfd-in2.h | 43 + bfd/config.bfd | 15 + bfd/configure | 2 + bfd/configure.ac | 2 + bfd/cpu-riscv.c | 79 + bfd/elf-bfd.h | 1 + bfd/elf32-microblaze.c | 4 +- bfd/elfnn-riscv.c | 3160 +++++++++++++++++++++++++++ bfd/elfxx-riscv.c | 815 +++++++ bfd/elfxx-riscv.h | 33 + bfd/libbfd.h | 38 + bfd/reloc.c | 80 + bfd/targets.c | 6 + bfd/version.h | 2 +- binutils/ChangeLog | 14 + binutils/dwarf.c | 442 ++++- binutils/dwarf.h | 4 + binutils/readelf.c | 20 +- binutils/testsuite/binutils-all/objdump.exp | 4 +- gas/ChangeLog | 21 + gas/Makefile.am | 2 + gas/Makefile.in | 17 + gas/NEWS | 2 + gas/config/tc-riscv.c | 2408 ++++++++++++++++++++ gas/config/tc-riscv.h | 101 + gas/configure | 2 +- gas/configure.ac | 2 +- gas/configure.tgt | 6 +- gas/doc/as.texinfo | 19 + gas/doc/c-riscv.texi | 48 + gas/testsuite/gas/all/gas.exp | 8 +- gas/testsuite/gas/elf/elf.exp | 3 + gas/testsuite/gas/riscv/riscv.exp | 23 + gas/testsuite/gas/riscv/t_insns.d | 10 + gas/testsuite/gas/riscv/t_insns.s | 2 + gdb/ChangeLog | 23 + gdb/config.in | 4 - gdb/configure | 6 - gdb/configure.ac | 6 - gdb/defs.h | 1 - gdb/dwarf2read.c | 12 +- gdb/mips-tdep.c | 77 +- gdb/osabi.c | 1 - gdb/symfile.h | 1 + include/ChangeLog | 10 + include/dis-asm.h | 2 + include/elf/riscv.h | 92 + include/opcode/riscv-opc.h | 1160 ++++++++++ include/opcode/riscv.h | 342 +++ ld/ChangeLog | 20 + ld/Makefile.am | 13 + ld/Makefile.in | 15 + ld/NEWS | 2 +- ld/configure.tgt | 6 + ld/emulparams/elf32lriscv-defs.sh | 42 + ld/emulparams/elf32lriscv.sh | 2 + ld/emulparams/elf64lriscv-defs.sh | 13 + ld/emulparams/elf64lriscv.sh | 2 + ld/emultempl/riscvelf.em | 68 + ld/ldmain.c | 1 + ld/plugin.c | 1 + opcodes/ChangeLog | 11 + opcodes/configure | 1 + opcodes/configure.ac | 1 + opcodes/disassemble.c | 8 + opcodes/riscv-dis.c | 502 +++++ opcodes/riscv-opc.c | 624 ++++++ 71 files changed, 10470 insertions(+), 129 deletions(-) create mode 100644 bfd/cpu-riscv.c create mode 100644 bfd/elfnn-riscv.c create mode 100644 bfd/elfxx-riscv.c create mode 100644 bfd/elfxx-riscv.h create mode 100644 gas/config/tc-riscv.c create mode 100644 gas/config/tc-riscv.h create mode 100644 gas/doc/c-riscv.texi create mode 100644 gas/testsuite/gas/riscv/riscv.exp create mode 100644 gas/testsuite/gas/riscv/t_insns.d create mode 100644 gas/testsuite/gas/riscv/t_insns.s create mode 100644 include/elf/riscv.h create mode 100644 include/opcode/riscv-opc.h create mode 100644 include/opcode/riscv.h create mode 100644 ld/emulparams/elf32lriscv-defs.sh create mode 100644 ld/emulparams/elf32lriscv.sh create mode 100644 ld/emulparams/elf64lriscv-defs.sh create mode 100644 ld/emulparams/elf64lriscv.sh create mode 100644 ld/emultempl/riscvelf.em create mode 100644 opcodes/riscv-dis.c create mode 100644 opcodes/riscv-opc.c First 500 lines of diff: diff --git a/bfd/ChangeLog b/bfd/ChangeLog index 3fbac7e..75ffab5 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,3 +1,28 @@ +2016-11-01 Palmer Dabbelt + Andrew Waterman + + Add support for RISC-V architecture. + * Makefile.am: Add entries for riscv32-elf and riscv64-elf. + * config.bdf: Likewise. + * configure.ac: Likewise. + * Makefile.in: Regenerate. + * configure: Regenerate. + * archures.c: Add bfd_riscv_arch. + * reloc.c: Add riscv relocs. + * targets.c: Add riscv_elf32_vec and riscv_elf64_vec. + * bfd-in2.h: Regenerate. + * libbfd.h: Regenerate. + * elf-bfd.h: Add RISCV_ELF_DATA to enum elf_target_id. + * elfnn-riscv.c: New file. + * elfxx-riscv.c: New file. + * elfxx-riscv.h: New file. + +2016-10-31 Alan Modra + + PR 20748 + * elf32-microblaze.c (microblaze_elf_finish_dynamic_sections): Revert + 2016-05-13 change. + 2016-10-27 Andrew Burgess * cpu-arc.c (arc_get_mach): Delete. diff --git a/bfd/Makefile.am b/bfd/Makefile.am index e04be5a..0d5dd4a 100644 --- a/bfd/Makefile.am +++ b/bfd/Makefile.am @@ -148,6 +148,7 @@ ALL_MACHINES = \ cpu-plugin.lo \ cpu-powerpc.lo \ cpu-rs6000.lo \ + cpu-riscv.lo \ cpu-rl78.lo \ cpu-rx.lo \ cpu-s390.lo \ @@ -235,6 +236,7 @@ ALL_MACHINES_CFILES = \ cpu-plugin.c \ cpu-powerpc.c \ cpu-rs6000.c \ + cpu-riscv.c \ cpu-rl78.c \ cpu-rx.c \ cpu-s390.c \ @@ -671,18 +673,21 @@ BFD64_BACKENDS = \ elf64-hppa.lo \ elf64-ia64.lo \ elf64-ia64-vms.lo \ + elfxx-ia64.lo \ + elfn32-mips.lo \ elf64-mips.lo \ + elfxx-mips.lo \ elf64-mmix.lo \ elf64-ppc.lo \ + elf32-riscv.lo \ + elf64-riscv.lo \ + elfxx-riscv.lo \ elf64-s390.lo \ elf64-sh64.lo \ elf64-sparc.lo \ elf64-tilegx.lo \ elf64-x86-64.lo \ elf64.lo \ - elfn32-mips.lo \ - elfxx-ia64.lo \ - elfxx-mips.lo \ mach-o-aarch64.lo \ mach-o-x86-64.lo \ mmo.lo \ @@ -722,6 +727,7 @@ BFD64_BACKENDS_CFILES = \ elfxx-aarch64.c \ elfxx-ia64.c \ elfxx-mips.c \ + elfxx-riscv.c \ mach-o-aarch64.c \ mach-o-x86-64.c \ mmo.c \ @@ -785,7 +791,9 @@ SOURCE_CFILES = \ BUILD_CFILES = \ elf32-aarch64.c elf64-aarch64.c \ - elf32-ia64.c elf64-ia64.c peigen.c pepigen.c pex64igen.c + elf32-ia64.c elf64-ia64.c \ + elf32-riscv.c elf64-riscv.c \ + peigen.c pepigen.c pex64igen.c CFILES = $(SOURCE_CFILES) $(BUILD_CFILES) @@ -955,6 +963,18 @@ elf64-ia64.c : elfnn-ia64.c $(SED) -e s/NN/64/g < $(srcdir)/elfnn-ia64.c > elf64-ia64.new mv -f elf64-ia64.new elf64-ia64.c +elf32-riscv.c : elfnn-riscv.c + rm -f elf32-riscv.c + echo "#line 1 \"$(srcdir)/elfnn-riscv.c\"" > elf32-riscv.new + sed -e s/NN/32/g < $(srcdir)/elfnn-riscv.c >> elf32-riscv.new + mv -f elf32-riscv.new elf32-riscv.c + +elf64-riscv.c : elfnn-riscv.c + rm -f elf64-riscv.c + echo "#line 1 \"$(srcdir)/elfnn-riscv.c\"" > elf64-riscv.new + sed -e s/NN/64/g < $(srcdir)/elfnn-riscv.c >> elf64-riscv.new + mv -f elf64-riscv.new elf64-riscv.c + peigen.c : peXXigen.c rm -f peigen.c $(SED) -e s/XX/pe/g < $(srcdir)/peXXigen.c > peigen.new diff --git a/bfd/Makefile.in b/bfd/Makefile.in index 64658c5..661155c 100644 --- a/bfd/Makefile.in +++ b/bfd/Makefile.in @@ -481,6 +481,7 @@ ALL_MACHINES = \ cpu-plugin.lo \ cpu-powerpc.lo \ cpu-rs6000.lo \ + cpu-riscv.lo \ cpu-rl78.lo \ cpu-rx.lo \ cpu-s390.lo \ @@ -568,6 +569,7 @@ ALL_MACHINES_CFILES = \ cpu-plugin.c \ cpu-powerpc.c \ cpu-rs6000.c \ + cpu-riscv.c \ cpu-rl78.c \ cpu-rx.c \ cpu-s390.c \ @@ -1006,18 +1008,21 @@ BFD64_BACKENDS = \ elf64-hppa.lo \ elf64-ia64.lo \ elf64-ia64-vms.lo \ + elfxx-ia64.lo \ + elfn32-mips.lo \ elf64-mips.lo \ + elfxx-mips.lo \ elf64-mmix.lo \ elf64-ppc.lo \ + elf32-riscv.lo \ + elf64-riscv.lo \ + elfxx-riscv.lo \ elf64-s390.lo \ elf64-sh64.lo \ elf64-sparc.lo \ elf64-tilegx.lo \ elf64-x86-64.lo \ elf64.lo \ - elfn32-mips.lo \ - elfxx-ia64.lo \ - elfxx-mips.lo \ mach-o-aarch64.lo \ mach-o-x86-64.lo \ mmo.lo \ @@ -1057,6 +1062,7 @@ BFD64_BACKENDS_CFILES = \ elfxx-aarch64.c \ elfxx-ia64.c \ elfxx-mips.c \ + elfxx-riscv.c \ mach-o-aarch64.c \ mach-o-x86-64.c \ mmo.c \ @@ -1122,7 +1128,9 @@ SOURCE_CFILES = \ BUILD_CFILES = \ elf32-aarch64.c elf64-aarch64.c \ - elf32-ia64.c elf64-ia64.c peigen.c pepigen.c pex64igen.c + elf32-ia64.c elf64-ia64.c \ + elf32-riscv.c elf64-riscv.c \ + peigen.c pepigen.c pex64igen.c CFILES = $(SOURCE_CFILES) $(BUILD_CFILES) SOURCE_HFILES = \ @@ -1412,6 +1420,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-pj.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-plugin.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-powerpc.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-riscv.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-rl78.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-rs6000.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-rx.Plo@am__quote@ @@ -1501,6 +1510,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-or1k.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-pj.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-ppc.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-riscv.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-rl78.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-rx.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-s390.Plo@am__quote@ @@ -1532,6 +1542,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-mips.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-mmix.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-ppc.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-riscv.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-s390.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-sh64.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-sparc.Plo@am__quote@ @@ -1543,6 +1554,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elfxx-aarch64.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elfxx-ia64.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elfxx-mips.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elfxx-riscv.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elfxx-sparc.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elfxx-tilegx.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/epoc-pe-arm.Plo@am__quote@ @@ -2080,6 +2092,18 @@ elf64-ia64.c : elfnn-ia64.c $(SED) -e s/NN/64/g < $(srcdir)/elfnn-ia64.c > elf64-ia64.new mv -f elf64-ia64.new elf64-ia64.c +elf32-riscv.c : elfnn-riscv.c + rm -f elf32-riscv.c + echo "#line 1 \"$(srcdir)/elfnn-riscv.c\"" > elf32-riscv.new + sed -e s/NN/32/g < $(srcdir)/elfnn-riscv.c >> elf32-riscv.new + mv -f elf32-riscv.new elf32-riscv.c + +elf64-riscv.c : elfnn-riscv.c + rm -f elf64-riscv.c + echo "#line 1 \"$(srcdir)/elfnn-riscv.c\"" > elf64-riscv.new + sed -e s/NN/64/g < $(srcdir)/elfnn-riscv.c >> elf64-riscv.new + mv -f elf64-riscv.new elf64-riscv.c + peigen.c : peXXigen.c rm -f peigen.c $(SED) -e s/XX/pe/g < $(srcdir)/peXXigen.c > peigen.new diff --git a/bfd/archures.c b/bfd/archures.c index af70b18..e503492 100644 --- a/bfd/archures.c +++ b/bfd/archures.c @@ -457,6 +457,9 @@ DESCRIPTION .#define bfd_mach_cris_v0_v10 255 .#define bfd_mach_cris_v32 32 .#define bfd_mach_cris_v10_v32 1032 +. bfd_arch_riscv, +.#define bfd_mach_riscv32 132 +.#define bfd_mach_riscv64 164 . bfd_arch_rl78, .#define bfd_mach_rl78 0x75 . bfd_arch_rx, {* Renesas RX. *} @@ -628,6 +631,7 @@ extern const bfd_arch_info_type bfd_pj_arch; extern const bfd_arch_info_type bfd_plugin_arch; extern const bfd_arch_info_type bfd_powerpc_archs[]; #define bfd_powerpc_arch bfd_powerpc_archs[0] +extern const bfd_arch_info_type bfd_riscv_arch; extern const bfd_arch_info_type bfd_rs6000_arch; extern const bfd_arch_info_type bfd_rl78_arch; extern const bfd_arch_info_type bfd_rx_arch; @@ -717,8 +721,9 @@ static const bfd_arch_info_type * const bfd_archures_list[] = &bfd_or1k_arch, &bfd_pdp11_arch, &bfd_powerpc_arch, - &bfd_rs6000_arch, + &bfd_riscv_arch, &bfd_rl78_arch, + &bfd_rs6000_arch, &bfd_rx_arch, &bfd_s390_arch, &bfd_score_arch, diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index 3c0ff9d..fdb7878 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -2295,6 +2295,9 @@ enum bfd_architecture #define bfd_mach_cris_v0_v10 255 #define bfd_mach_cris_v32 32 #define bfd_mach_cris_v10_v32 1032 + bfd_arch_riscv, +#define bfd_mach_riscv32 132 +#define bfd_mach_riscv64 164 bfd_arch_rl78, #define bfd_mach_rl78 0x75 bfd_arch_rx, /* Renesas RX. */ @@ -4691,6 +4694,46 @@ number for the IN and OUT instructions */ number for the SBIC, SBIS, SBI and CBI instructions */ BFD_RELOC_AVR_PORT5, +/* RISC-V relocations. */ + BFD_RELOC_RISCV_HI20, + BFD_RELOC_RISCV_PCREL_HI20, + BFD_RELOC_RISCV_PCREL_LO12_I, + BFD_RELOC_RISCV_PCREL_LO12_S, + BFD_RELOC_RISCV_LO12_I, + BFD_RELOC_RISCV_LO12_S, + BFD_RELOC_RISCV_GPREL12_I, + BFD_RELOC_RISCV_GPREL12_S, + BFD_RELOC_RISCV_TPREL_HI20, + BFD_RELOC_RISCV_TPREL_LO12_I, + BFD_RELOC_RISCV_TPREL_LO12_S, + BFD_RELOC_RISCV_TPREL_ADD, + BFD_RELOC_RISCV_CALL, + BFD_RELOC_RISCV_CALL_PLT, + BFD_RELOC_RISCV_ADD8, + BFD_RELOC_RISCV_ADD16, + BFD_RELOC_RISCV_ADD32, + BFD_RELOC_RISCV_ADD64, + BFD_RELOC_RISCV_SUB8, + BFD_RELOC_RISCV_SUB16, + BFD_RELOC_RISCV_SUB32, + BFD_RELOC_RISCV_SUB64, + BFD_RELOC_RISCV_GOT_HI20, + BFD_RELOC_RISCV_TLS_GOT_HI20, + BFD_RELOC_RISCV_TLS_GD_HI20, + BFD_RELOC_RISCV_JMP, + BFD_RELOC_RISCV_TLS_DTPMOD32, + BFD_RELOC_RISCV_TLS_DTPREL32, + BFD_RELOC_RISCV_TLS_DTPMOD64, + BFD_RELOC_RISCV_TLS_DTPREL64, + BFD_RELOC_RISCV_TLS_TPREL32, + BFD_RELOC_RISCV_TLS_TPREL64, + BFD_RELOC_RISCV_ALIGN, + BFD_RELOC_RISCV_RVC_BRANCH, + BFD_RELOC_RISCV_RVC_JUMP, + BFD_RELOC_RISCV_RVC_LUI, + BFD_RELOC_RISCV_GPREL_I, + BFD_RELOC_RISCV_GPREL_S, + /* Renesas RL78 Relocations. */ BFD_RELOC_RL78_NEG8, BFD_RELOC_RL78_NEG16, diff --git a/bfd/config.bfd b/bfd/config.bfd index 6400722..98663fd 100644 --- a/bfd/config.bfd +++ b/bfd/config.bfd @@ -122,6 +122,7 @@ or1k*|or1knd*) targ_archs=bfd_or1k_arch ;; pdp11*) targ_archs=bfd_pdp11_arch ;; pj*) targ_archs="bfd_pj_arch bfd_i386_arch";; powerpc*) targ_archs="bfd_rs6000_arch bfd_powerpc_arch" ;; +riscv*) targ_archs=bfd_riscv_arch ;; rs6000) targ_archs="bfd_rs6000_arch bfd_powerpc_arch" ;; s390*) targ_archs=bfd_s390_arch ;; sh*) targ_archs=bfd_sh_arch ;; @@ -1359,6 +1360,20 @@ case "${targ}" in targ_selvecs="powerpc_pei_le_vec powerpc_pei_vec powerpc_pe_le_vec powerpc_pe_vec" ;; +#ifdef BFD64 + riscv32-*-*) + targ_defvec=riscv_elf32_vec + targ_selvecs="riscv_elf32_vec" + want64=true + ;; + + riscv64-*-*) + targ_defvec=riscv_elf64_vec + targ_selvecs="riscv_elf32_vec riscv_elf64_vec" + want64=true + ;; +#endif + rl78-*-elf) targ_defvec=rl78_elf32_vec ;; diff --git a/bfd/configure b/bfd/configure index 8284069..68db12f 100755 --- a/bfd/configure +++ b/bfd/configure @@ -14475,6 +14475,8 @@ do powerpc_pei_vec) tb="$tb pei-ppc.lo peigen.lo $coff" ;; powerpc_pei_le_vec) tb="$tb pei-ppc.lo peigen.lo $coff" ;; powerpc_xcoff_vec) tb="$tb coff-rs6000.lo $xcoff" ;; + riscv_elf32_vec) tb="$tb elf32-riscv.lo elfxx-riscv.lo elf32.lo $elf" ;; + riscv_elf64_vec) tb="$tb elf64-riscv.lo elf64.lo elfxx-riscv.lo elf32.lo $elf"; target_size=64 ;; rl78_elf32_vec) tb="$tb elf32-rl78.lo elf32.lo $elf" ;; rs6000_xcoff64_vec) tb="$tb coff64-rs6000.lo aix5ppc-core.lo $xcoff"; target_size=64 ;; rs6000_xcoff64_aix_vec) tb="$tb coff64-rs6000.lo aix5ppc-core.lo $xcoff"; target_size=64 ;; diff --git a/bfd/configure.ac b/bfd/configure.ac index 669cff7..6f11d29 100644 --- a/bfd/configure.ac +++ b/bfd/configure.ac @@ -606,6 +606,8 @@ do powerpc_pei_vec) tb="$tb pei-ppc.lo peigen.lo $coff" ;; powerpc_pei_le_vec) tb="$tb pei-ppc.lo peigen.lo $coff" ;; powerpc_xcoff_vec) tb="$tb coff-rs6000.lo $xcoff" ;; + riscv_elf32_vec) tb="$tb elf32-riscv.lo elfxx-riscv.lo elf32.lo $elf" ;; + riscv_elf64_vec) tb="$tb elf64-riscv.lo elf64.lo elfxx-riscv.lo elf32.lo $elf"; target_size=64 ;; rl78_elf32_vec) tb="$tb elf32-rl78.lo elf32.lo $elf" ;; rs6000_xcoff64_vec) tb="$tb coff64-rs6000.lo aix5ppc-core.lo $xcoff"; target_size=64 ;; rs6000_xcoff64_aix_vec) tb="$tb coff64-rs6000.lo aix5ppc-core.lo $xcoff"; target_size=64 ;; diff --git a/bfd/cpu-riscv.c b/bfd/cpu-riscv.c new file mode 100644 index 0000000..a938199 --- /dev/null +++ b/bfd/cpu-riscv.c @@ -0,0 +1,79 @@ +/* BFD backend for RISC-V + Copyright 2011-2016 Free Software Foundation, Inc. + + Contributed by Andrew Waterman (andrew@sifive.com). + Based on MIPS target. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING3. If not, + see . */ + +#include "sysdep.h" +#include "bfd.h" +#include "libbfd.h" + +/* This routine is provided two arch_infos and returns an arch_info + that is compatible with both, or NULL if none exists. */ + +static const bfd_arch_info_type * +riscv_compatible (const bfd_arch_info_type *a, const bfd_arch_info_type *b) +{ + if (a->arch != b->arch) + return NULL; + + /* Machine compatibility is checked in + _bfd_riscv_elf_merge_private_bfd_data. */ + + return a; +} + +#define N(BITS_WORD, BITS_ADDR, NUMBER, PRINT, DEFAULT, NEXT) \ + { \ + BITS_WORD, /* bits in a word */ \ + BITS_ADDR, /* bits in an address */ \ + 8, /* 8 bits in a byte */ \ + bfd_arch_riscv, \ + NUMBER, \ + "riscv", \ + PRINT, \ + 3, \ + DEFAULT, \ + riscv_compatible, \ + bfd_default_scan, \ + bfd_arch_default_fill, \ + NEXT, \ + } + +/* This enum must be kept in the same order as arch_info_struct. */ +enum +{ + I_riscv64, + I_riscv32 +}; + +#define NN(index) (&arch_info_struct[(index) + 1]) + +/* This array must be kept in the same order as the anonymous enum above, + and each entry except the last should end with NN (my enum value). */ +static const bfd_arch_info_type arch_info_struct[] = +{ + N (64, 64, bfd_mach_riscv64, "riscv:rv64", FALSE, NN (I_riscv64)), + N (32, 32, bfd_mach_riscv32, "riscv:rv32", FALSE, 0) +}; + +/* The default architecture is riscv:rv64. */ + +const bfd_arch_info_type bfd_riscv_arch = + N (64, 64, 0, "riscv", TRUE, &arch_info_struct[0]); diff --git a/bfd/elf-bfd.h b/bfd/elf-bfd.h index af2af2c..50151cb 100644 --- a/bfd/elf-bfd.h +++ b/bfd/elf-bfd.h @@ -477,6 +477,7 @@ enum elf_target_id XGATE_ELF_DATA, TILEGX_ELF_DATA, TILEPRO_ELF_DATA, + RISCV_ELF_DATA, GENERIC_ELF_DATA }; diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c index 477e7b3..5c66808 100644 --- a/bfd/elf32-microblaze.c +++ b/bfd/elf32-microblaze.c @@ -3396,13 +3396,13 @@ microblaze_elf_finish_dynamic_sections (bfd *output_bfd, { asection *s; - s = bfd_get_linker_section (dynobj, name); + s = bfd_get_section_by_name (output_bfd, name); if (s == NULL) dyn.d_un.d_val = 0; else { if (! size) - dyn.d_un.d_ptr = s->output_section->vma + s->output_offset; + dyn.d_un.d_ptr = s->vma; else dyn.d_un.d_val = s->size; hooks/post-receive -- Repository for Project Archer.