From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jason Molenda <jsm@cygnus.com>
To: bfd@cygnus.com
Subject: [toddpw@wrs.com: Patch to opcodes/ppc-opc.c to avoid overnested parens in MSVC.]
Date: Tue, 28 Jul 1998 11:47:00 -0000
Message-id: <19980728114708.E20870@cygnus.com>
X-SW-Source: 1998/msg00062.html

This was sent to the gdb mailing list.  I haven't looked into copyright
assignments, etc, I'm just passing it along.

----- Forwarded message from Todd Whitesel <toddpw@wrs.com> -----

From: toddpw@wrs.com (Todd Whitesel)
Subject: Patch to opcodes/ppc-opc.c to avoid overnested parens in MSVC.
To: gdb@cygnus.com
Date: Mon, 27 Jul 1998 18:46:34 -0700 (PDT)
X-Mailer: ELM [version 2.4 PL24]

The C compiler in Microsoft Developer Studio 5 has a limit on nested
parentheses. Here is the patch I am using to avoid it, applied to 4.17.
The only file affected is 'opcodes/ppc-opc.c'.

Todd Whitesel
toddpw @ wrs.com
--- cut here ---
#!/bin/sh

patch -b -c -p 0 <<':END:PATCH:HUNKS:'
Index: opcodes/ppc-opc.c
diff -c opcodes/ppc-opc.c.orig opcodes/ppc-opc.c
*** opcodes/ppc-opc.c.orig	Mon Jul 27 18:39:42 1998
--- opcodes/ppc-opc.c	Mon Jul 27 18:39:51 1998
***************
*** 79,176 ****
  
     The fields are bits, shift, insert, extract, flags.  */
  
  const struct powerpc_operand powerpc_operands[] =
  {
    /* The zero index is used to indicate the end of the list of
       operands.  */
! #define UNUSED 0
    { 0, 0, 0, 0, 0 },
  
    /* The BA field in an XL form instruction.  */
! #define BA (UNUSED + 1)
  #define BA_MASK (0x1f << 16)
    { 5, 16, 0, 0, PPC_OPERAND_CR },
  
    /* The BA field in an XL form instruction when it must be the same
       as the BT field in the same instruction.  */
! #define BAT (BA + 1)
    { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
  
    /* The BB field in an XL form instruction.  */
! #define BB (BAT + 1)
  #define BB_MASK (0x1f << 11)
    { 5, 11, 0, 0, PPC_OPERAND_CR },
  
    /* The BB field in an XL form instruction when it must be the same
       as the BA field in the same instruction.  */
! #define BBA (BB + 1)
    { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
  
    /* The BD field in a B form instruction.  The lower two bits are
       forced to zero.  */
! #define BD (BBA + 1)
    { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
  
    /* The BD field in a B form instruction when absolute addressing is
       used.  */
! #define BDA (BD + 1)
    { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
  
    /* The BD field in a B form instruction when the - modifier is used.
       This sets the y bit of the BO field appropriately.  */
! #define BDM (BDA + 1)
    { 16, 0, insert_bdm, extract_bdm,
        PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
  
    /* The BD field in a B form instruction when the - modifier is used
       and absolute address is used.  */
! #define BDMA (BDM + 1)
    { 16, 0, insert_bdm, extract_bdm,
        PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
  
    /* The BD field in a B form instruction when the + modifier is used.
       This sets the y bit of the BO field appropriately.  */
! #define BDP (BDMA + 1)
    { 16, 0, insert_bdp, extract_bdp,
        PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
  
    /* The BD field in a B form instruction when the + modifier is used
       and absolute addressing is used.  */
! #define BDPA (BDP + 1)
    { 16, 0, insert_bdp, extract_bdp,
        PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
  
    /* The BF field in an X or XL form instruction.  */
! #define BF (BDPA + 1)
    { 3, 23, 0, 0, PPC_OPERAND_CR },
  
    /* An optional BF field.  This is used for comparison instructions,
       in which an omitted BF field is taken as zero.  */
! #define OBF (BF + 1)
    { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
  
    /* The BFA field in an X or XL form instruction.  */
! #define BFA (OBF + 1)
    { 3, 18, 0, 0, PPC_OPERAND_CR },
  
    /* The BI field in a B form or XL form instruction.  */
! #define BI (BFA + 1)
  #define BI_MASK (0x1f << 16)
    { 5, 16, 0, 0, PPC_OPERAND_CR },
  
    /* The BO field in a B form instruction.  Certain values are
       illegal.  */
! #define BO (BI + 1)
  #define BO_MASK (0x1f << 21)
    { 5, 21, insert_bo, extract_bo, 0 },
  
    /* The BO field in a B form instruction when the + or - modifier is
       used.  This is like the BO field, but it must be even.  */
! #define BOE (BO + 1)
    { 5, 21, insert_boe, extract_boe, 0 },
  
    /* The BT field in an X or XL form instruction.  */
! #define BT (BOE + 1)
    { 5, 21, 0, 0, PPC_OPERAND_CR },
  
    /* The condition register number portion of the BI field in a B form
--- 79,198 ----
  
     The fields are bits, shift, insert, extract, flags.  */
  
+ /*[TPW] Apparently 58 levels of nested parentheses is more than the poor MSVC
+ 	compiler can handle. So I introduce MACRO_np versions of each macro to
+ 	combine the +1+1+1... together and slap on safety paren's at the end. */
+ 
  const struct powerpc_operand powerpc_operands[] =
  {
    /* The zero index is used to indicate the end of the list of
       operands.  */
! #define UNUSED_np 0
! #define UNUSED (0)
    { 0, 0, 0, 0, 0 },
  
    /* The BA field in an XL form instruction.  */
! #define BA_np UNUSED_np + 1
! #define BA (UNUSED_np + 1)
  #define BA_MASK (0x1f << 16)
    { 5, 16, 0, 0, PPC_OPERAND_CR },
  
    /* The BA field in an XL form instruction when it must be the same
       as the BT field in the same instruction.  */
! #define BAT_np BA_np + 1
! #define BAT (BA_np + 1)
    { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
  
    /* The BB field in an XL form instruction.  */
! #define BB_np BAT_np + 1
! #define BB (BAT_np + 1)
  #define BB_MASK (0x1f << 11)
    { 5, 11, 0, 0, PPC_OPERAND_CR },
  
    /* The BB field in an XL form instruction when it must be the same
       as the BA field in the same instruction.  */
! #define BBA_np BB_np + 1
! #define BBA (BB_np + 1)
    { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
  
    /* The BD field in a B form instruction.  The lower two bits are
       forced to zero.  */
! #define BD_np BBA_np + 1
! #define BD (BBA_np + 1)
    { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
  
    /* The BD field in a B form instruction when absolute addressing is
       used.  */
! #define BDA_np BD_np + 1
! #define BDA (BD_np + 1)
    { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
  
    /* The BD field in a B form instruction when the - modifier is used.
       This sets the y bit of the BO field appropriately.  */
! #define BDM_np BDA_np + 1
! #define BDM (BDA_np + 1)
    { 16, 0, insert_bdm, extract_bdm,
        PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
  
    /* The BD field in a B form instruction when the - modifier is used
       and absolute address is used.  */
! #define BDMA_np BDM_np + 1
! #define BDMA (BDM_np + 1)
    { 16, 0, insert_bdm, extract_bdm,
        PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
  
    /* The BD field in a B form instruction when the + modifier is used.
       This sets the y bit of the BO field appropriately.  */
! #define BDP_np BDMA_np + 1
! #define BDP (BDMA_np + 1)
    { 16, 0, insert_bdp, extract_bdp,
        PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
  
    /* The BD field in a B form instruction when the + modifier is used
       and absolute addressing is used.  */
! #define BDPA_np BDP_np + 1
! #define BDPA (BDP_np + 1)
    { 16, 0, insert_bdp, extract_bdp,
        PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
  
    /* The BF field in an X or XL form instruction.  */
! #define BF_np BDPA_np + 1
! #define BF (BDPA_np + 1)
    { 3, 23, 0, 0, PPC_OPERAND_CR },
  
    /* An optional BF field.  This is used for comparison instructions,
       in which an omitted BF field is taken as zero.  */
! #define OBF_np BF_np + 1
! #define OBF (BF_np + 1)
    { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
  
    /* The BFA field in an X or XL form instruction.  */
! #define BFA_np OBF_np + 1
! #define BFA (OBF_np + 1)
    { 3, 18, 0, 0, PPC_OPERAND_CR },
  
    /* The BI field in a B form or XL form instruction.  */
! #define BI_np BFA_np + 1
! #define BI (BFA_np + 1)
  #define BI_MASK (0x1f << 16)
    { 5, 16, 0, 0, PPC_OPERAND_CR },
  
    /* The BO field in a B form instruction.  Certain values are
       illegal.  */
! #define BO_np BI_np + 1
! #define BO (BI_np + 1)
  #define BO_MASK (0x1f << 21)
    { 5, 21, insert_bo, extract_bo, 0 },
  
    /* The BO field in a B form instruction when the + or - modifier is
       used.  This is like the BO field, but it must be even.  */
! #define BOE_np BO_np + 1
! #define BOE (BO_np + 1)
    { 5, 21, insert_boe, extract_boe, 0 },
  
    /* The BT field in an X or XL form instruction.  */
! #define BT_np BOE_np + 1
! #define BT (BOE_np + 1)
    { 5, 21, 0, 0, PPC_OPERAND_CR },
  
    /* The condition register number portion of the BI field in a B form
***************
*** 177,263 ****
       or XL form instruction.  This is used for the extended
       conditional branch mnemonics, which set the lower two bits of the
       BI field.  This field is optional.  */
! #define CR (BT + 1)
    { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
  
    /* The D field in a D form instruction.  This is a displacement off
       a register, and implies that the next operand is a register in
       parentheses.  */
! #define D (CR + 1)
    { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
  
    /* The DS field in a DS form instruction.  This is like D, but the
       lower two bits are forced to zero.  */
! #define DS (D + 1)
    { 16, 0, insert_ds, extract_ds, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
  
    /* The E field in a wrteei instruction.  */
! #define E (DS + 1)
    { 1, 15, 0, 0, 0 },
  
    /* The FL1 field in a POWER SC form instruction.  */
! #define FL1 (E + 1)
    { 4, 12, 0, 0, 0 },
  
    /* The FL2 field in a POWER SC form instruction.  */
! #define FL2 (FL1 + 1)
    { 3, 2, 0, 0, 0 },
  
    /* The FLM field in an XFL form instruction.  */
! #define FLM (FL2 + 1)
    { 8, 17, 0, 0, 0 },
  
    /* The FRA field in an X or A form instruction.  */
! #define FRA (FLM + 1)
  #define FRA_MASK (0x1f << 16)
    { 5, 16, 0, 0, PPC_OPERAND_FPR },
  
    /* The FRB field in an X or A form instruction.  */
! #define FRB (FRA + 1)
  #define FRB_MASK (0x1f << 11)
    { 5, 11, 0, 0, PPC_OPERAND_FPR },
  
    /* The FRC field in an A form instruction.  */
! #define FRC (FRB + 1)
  #define FRC_MASK (0x1f << 6)
    { 5, 6, 0, 0, PPC_OPERAND_FPR },
  
    /* The FRS field in an X form instruction or the FRT field in a D, X
       or A form instruction.  */
! #define FRS (FRC + 1)
  #define FRT (FRS)
    { 5, 21, 0, 0, PPC_OPERAND_FPR },
  
    /* The FXM field in an XFX instruction.  */
! #define FXM (FRS + 1)
  #define FXM_MASK (0xff << 12)
    { 8, 12, 0, 0, 0 },
  
    /* The L field in a D or X form instruction.  */
! #define L (FXM + 1)
    { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
  
    /* The LEV field in a POWER SC form instruction.  */
! #define LEV (L + 1)
    { 7, 5, 0, 0, 0 },
  
    /* The LI field in an I form instruction.  The lower two bits are
       forced to zero.  */
! #define LI (LEV + 1)
    { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
  
    /* The LI field in an I form instruction when used as an absolute
       address.  */
! #define LIA (LI + 1)
    { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
  
    /* The MB field in an M form instruction.  */
! #define MB (LIA + 1)
  #define MB_MASK (0x1f << 6)
    { 5, 6, 0, 0, 0 },
  
    /* The ME field in an M form instruction.  */
! #define ME (MB + 1)
  #define ME_MASK (0x1f << 1)
    { 5, 1, 0, 0, 0 },
  
--- 199,303 ----
       or XL form instruction.  This is used for the extended
       conditional branch mnemonics, which set the lower two bits of the
       BI field.  This field is optional.  */
! #define CR_np BT_np + 1
! #define CR (BT_np + 1)
    { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
  
    /* The D field in a D form instruction.  This is a displacement off
       a register, and implies that the next operand is a register in
       parentheses.  */
! #define D_np CR_np + 1
! #define D (CR_np + 1)
    { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
  
    /* The DS field in a DS form instruction.  This is like D, but the
       lower two bits are forced to zero.  */
! #define DS_np D_np + 1
! #define DS (D_np + 1)
    { 16, 0, insert_ds, extract_ds, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
  
    /* The E field in a wrteei instruction.  */
! #define E_np DS_np + 1
! #define E (DS_np + 1)
    { 1, 15, 0, 0, 0 },
  
    /* The FL1 field in a POWER SC form instruction.  */
! #define FL1_np E_np + 1
! #define FL1 (E_np + 1)
    { 4, 12, 0, 0, 0 },
  
    /* The FL2 field in a POWER SC form instruction.  */
! #define FL2_np FL1_np + 1
! #define FL2 (FL1_np + 1)
    { 3, 2, 0, 0, 0 },
  
    /* The FLM field in an XFL form instruction.  */
! #define FLM_np FL2_np + 1
! #define FLM (FL2_np + 1)
    { 8, 17, 0, 0, 0 },
  
    /* The FRA field in an X or A form instruction.  */
! #define FRA_np FLM_np + 1
! #define FRA (FLM_np + 1)
  #define FRA_MASK (0x1f << 16)
    { 5, 16, 0, 0, PPC_OPERAND_FPR },
  
    /* The FRB field in an X or A form instruction.  */
! #define FRB_np FRA_np + 1
! #define FRB (FRA_np + 1)
  #define FRB_MASK (0x1f << 11)
    { 5, 11, 0, 0, PPC_OPERAND_FPR },
  
    /* The FRC field in an A form instruction.  */
! #define FRC_np FRB_np + 1
! #define FRC (FRB_np + 1)
  #define FRC_MASK (0x1f << 6)
    { 5, 6, 0, 0, PPC_OPERAND_FPR },
  
    /* The FRS field in an X form instruction or the FRT field in a D, X
       or A form instruction.  */
! #define FRS_np FRC_np + 1
! #define FRS (FRC_np + 1)
  #define FRT (FRS)
    { 5, 21, 0, 0, PPC_OPERAND_FPR },
  
    /* The FXM field in an XFX instruction.  */
! #define FXM_np FRS_np + 1
! #define FXM (FRS_np + 1)
  #define FXM_MASK (0xff << 12)
    { 8, 12, 0, 0, 0 },
  
    /* The L field in a D or X form instruction.  */
! #define L_np FXM_np + 1
! #define L (FXM_np + 1)
    { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
  
    /* The LEV field in a POWER SC form instruction.  */
! #define LEV_np L_np + 1
! #define LEV (L_np + 1)
    { 7, 5, 0, 0, 0 },
  
    /* The LI field in an I form instruction.  The lower two bits are
       forced to zero.  */
! #define LI_np LEV_np + 1
! #define LI (LEV_np + 1)
    { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
  
    /* The LI field in an I form instruction when used as an absolute
       address.  */
! #define LIA_np LI_np + 1
! #define LIA (LI_np + 1)
    { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
  
    /* The MB field in an M form instruction.  */
! #define MB_np LIA_np + 1
! #define MB (LIA_np + 1)
  #define MB_MASK (0x1f << 6)
    { 5, 6, 0, 0, 0 },
  
    /* The ME field in an M form instruction.  */
! #define ME_np MB_np + 1
! #define ME (MB_np + 1)
  #define ME_MASK (0x1f << 1)
    { 5, 1, 0, 0, 0 },
  
***************
*** 265,277 ****
       operand which is a bitmask indicating which bits to select.  This
       is a two operand form using PPC_OPERAND_NEXT.  See the
       description in opcode/ppc.h for what this means.  */
! #define MBE (ME + 1)
    { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
    { 32, 0, insert_mbe, extract_mbe, 0 },
  
    /* The MB or ME field in an MD or MDS form instruction.  The high
       bit is wrapped to the low end.  */
! #define MB6 (MBE + 2)
  #define ME6 (MB6)
  #define MB6_MASK (0x3f << 5)
    { 6, 5, insert_mb6, extract_mb6, 0 },
--- 305,319 ----
       operand which is a bitmask indicating which bits to select.  This
       is a two operand form using PPC_OPERAND_NEXT.  See the
       description in opcode/ppc.h for what this means.  */
! #define MBE_np ME_np + 1
! #define MBE (ME_np + 1)
    { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
    { 32, 0, insert_mbe, extract_mbe, 0 },
  
    /* The MB or ME field in an MD or MDS form instruction.  The high
       bit is wrapped to the low end.  */
! #define MB6_np MBE_np + 2
! #define MB6 (MBE_np + 2)
  #define ME6 (MB6)
  #define MB6_MASK (0x3f << 5)
    { 6, 5, insert_mb6, extract_mb6, 0 },
***************
*** 278,294 ****
  
    /* The NB field in an X form instruction.  The value 32 is stored as
       0.  */
! #define NB (MB6 + 1)
    { 6, 11, insert_nb, extract_nb, 0 },
  
    /* The NSI field in a D form instruction.  This is the same as the
       SI field, only negated.  */
! #define NSI (NB + 1)
    { 16, 0, insert_nsi, extract_nsi,
        PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
  
    /* The RA field in an D, DS, X, XO, M, or MDS form instruction.  */
! #define RA (NSI + 1)
  #define RA_MASK (0x1f << 16)
    { 5, 16, 0, 0, PPC_OPERAND_GPR },
  
--- 320,339 ----
  
    /* The NB field in an X form instruction.  The value 32 is stored as
       0.  */
! #define NB_np MB6_np + 1
! #define NB (MB6_np + 1)
    { 6, 11, insert_nb, extract_nb, 0 },
  
    /* The NSI field in a D form instruction.  This is the same as the
       SI field, only negated.  */
! #define NSI_np NB_np + 1
! #define NSI (NB_np + 1)
    { 16, 0, insert_nsi, extract_nsi,
        PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
  
    /* The RA field in an D, DS, X, XO, M, or MDS form instruction.  */
! #define RA_np NSI_np + 1
! #define RA (NSI_np + 1)
  #define RA_MASK (0x1f << 16)
    { 5, 16, 0, 0, PPC_OPERAND_GPR },
  
***************
*** 295,316 ****
    /* The RA field in a D or X form instruction which is an updating
       load, which means that the RA field may not be zero and may not
       equal the RT field.  */
! #define RAL (RA + 1)
    { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
  
    /* The RA field in an lmw instruction, which has special value
       restrictions.  */
! #define RAM (RAL + 1)
    { 5, 16, insert_ram, 0, PPC_OPERAND_GPR },
  
    /* The RA field in a D or X form instruction which is an updating
       store or an updating floating point load, which means that the RA
       field may not be zero.  */
! #define RAS (RAM + 1)
    { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
  
    /* The RB field in an X, XO, M, or MDS form instruction.  */
! #define RB (RAS + 1)
  #define RB_MASK (0x1f << 11)
    { 5, 11, 0, 0, PPC_OPERAND_GPR },
  
--- 340,365 ----
    /* The RA field in a D or X form instruction which is an updating
       load, which means that the RA field may not be zero and may not
       equal the RT field.  */
! #define RAL_np RA_np + 1
! #define RAL (RA_np + 1)
    { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
  
    /* The RA field in an lmw instruction, which has special value
       restrictions.  */
! #define RAM_np RAL_np + 1
! #define RAM (RAL_np + 1)
    { 5, 16, insert_ram, 0, PPC_OPERAND_GPR },
  
    /* The RA field in a D or X form instruction which is an updating
       store or an updating floating point load, which means that the RA
       field may not be zero.  */
! #define RAS_np RAM_np + 1
! #define RAS (RAM_np + 1)
    { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
  
    /* The RB field in an X, XO, M, or MDS form instruction.  */
! #define RB_np RAS_np + 1
! #define RB (RAS_np + 1)
  #define RB_MASK (0x1f << 11)
    { 5, 11, 0, 0, PPC_OPERAND_GPR },
  
***************
*** 317,392 ****
    /* The RB field in an X form instruction when it must be the same as
       the RS field in the instruction.  This is used for extended
       mnemonics like mr.  */
! #define RBS (RB + 1)
    { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
  
    /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
       instruction or the RT field in a D, DS, X, XFX or XO form
       instruction.  */
! #define RS (RBS + 1)
  #define RT (RS)
  #define RT_MASK (0x1f << 21)
    { 5, 21, 0, 0, PPC_OPERAND_GPR },
  
    /* The SH field in an X or M form instruction.  */
! #define SH (RS + 1)
  #define SH_MASK (0x1f << 11)
    { 5, 11, 0, 0, 0 },
  
    /* The SH field in an MD form instruction.  This is split.  */
! #define SH6 (SH + 1)
  #define SH6_MASK ((0x1f << 11) | (1 << 1))
    { 6, 1, insert_sh6, extract_sh6, 0 },
  
    /* The SI field in a D form instruction.  */
! #define SI (SH6 + 1)
    { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
  
    /* The SI field in a D form instruction when we accept a wide range
       of positive values.  */
! #define SISIGNOPT (SI + 1)
    { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
  
    /* The SPR field in an XFX form instruction.  This is flipped--the
       lower 5 bits are stored in the upper 5 and vice- versa.  */
! #define SPR (SISIGNOPT + 1)
  #define SPR_MASK (0x3ff << 11)
    { 10, 11, insert_spr, extract_spr, 0 },
  
    /* The BAT index number in an XFX form m[ft]ibat[lu] instruction.  */
! #define SPRBAT (SPR + 1)
  #define SPRBAT_MASK (0x3 << 17)
    { 2, 17, 0, 0, 0 },
  
    /* The SPRG register number in an XFX form m[ft]sprg instruction.  */
! #define SPRG (SPRBAT + 1)
  #define SPRG_MASK (0x3 << 16)
    { 2, 16, 0, 0, 0 },
  
    /* The SR field in an X form instruction.  */
! #define SR (SPRG + 1)
    { 4, 16, 0, 0, 0 },
  
    /* The SV field in a POWER SC form instruction.  */
! #define SV (SR + 1)
    { 14, 2, 0, 0, 0 },
  
    /* The TBR field in an XFX form instruction.  This is like the SPR
       field, but it is optional.  */
! #define TBR (SV + 1)
    { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
  
    /* The TO field in a D or X form instruction.  */
! #define TO (TBR + 1)
  #define TO_MASK (0x1f << 21)
    { 5, 21, 0, 0, 0 },
  
    /* The U field in an X form instruction.  */
! #define U (TO + 1)
    { 4, 12, 0, 0, 0 },
  
    /* The UI field in a D form instruction.  */
! #define UI (U + 1)
    { 16, 0, 0, 0, 0 },
  };
  
--- 366,456 ----
    /* The RB field in an X form instruction when it must be the same as
       the RS field in the instruction.  This is used for extended
       mnemonics like mr.  */
! #define RBS_np RB_np + 1
! #define RBS (RB_np + 1)
    { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
  
    /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
       instruction or the RT field in a D, DS, X, XFX or XO form
       instruction.  */
! #define RS_np RBS_np + 1
! #define RS (RBS_np + 1)
  #define RT (RS)
  #define RT_MASK (0x1f << 21)
    { 5, 21, 0, 0, PPC_OPERAND_GPR },
  
    /* The SH field in an X or M form instruction.  */
! #define SH_np RS_np + 1
! #define SH (RS_np + 1)
  #define SH_MASK (0x1f << 11)
    { 5, 11, 0, 0, 0 },
  
    /* The SH field in an MD form instruction.  This is split.  */
! #define SH6_np SH_np + 1
! #define SH6 (SH_np + 1)
  #define SH6_MASK ((0x1f << 11) | (1 << 1))
    { 6, 1, insert_sh6, extract_sh6, 0 },
  
    /* The SI field in a D form instruction.  */
! #define SI_np SH6_np + 1
! #define SI (SH6_np + 1)
    { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
  
    /* The SI field in a D form instruction when we accept a wide range
       of positive values.  */
! #define SISIGNOPT_np SI_np + 1
! #define SISIGNOPT (SI_np + 1)
    { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
  
    /* The SPR field in an XFX form instruction.  This is flipped--the
       lower 5 bits are stored in the upper 5 and vice- versa.  */
! #define SPR_np SISIGNOPT_np + 1
! #define SPR (SISIGNOPT_np + 1)
  #define SPR_MASK (0x3ff << 11)
    { 10, 11, insert_spr, extract_spr, 0 },
  
    /* The BAT index number in an XFX form m[ft]ibat[lu] instruction.  */
! #define SPRBAT_np SPR_np + 1
! #define SPRBAT (SPR_np + 1)
  #define SPRBAT_MASK (0x3 << 17)
    { 2, 17, 0, 0, 0 },
  
    /* The SPRG register number in an XFX form m[ft]sprg instruction.  */
! #define SPRG_np SPRBAT_np + 1
! #define SPRG (SPRBAT_np + 1)
  #define SPRG_MASK (0x3 << 16)
    { 2, 16, 0, 0, 0 },
  
    /* The SR field in an X form instruction.  */
! #define SR_np SPRG_np + 1
! #define SR (SPRG_np + 1)
    { 4, 16, 0, 0, 0 },
  
    /* The SV field in a POWER SC form instruction.  */
! #define SV_np SR_np + 1
! #define SV (SR_np + 1)
    { 14, 2, 0, 0, 0 },
  
    /* The TBR field in an XFX form instruction.  This is like the SPR
       field, but it is optional.  */
! #define TBR_np SV_np + 1
! #define TBR (SV_np + 1)
    { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
  
    /* The TO field in a D or X form instruction.  */
! #define TO_np TBR_np + 1
! #define TO (TBR_np + 1)
  #define TO_MASK (0x1f << 21)
    { 5, 21, 0, 0, 0 },
  
    /* The U field in an X form instruction.  */
! #define U_np TO_np + 1
! #define U (TO_np + 1)
    { 4, 12, 0, 0, 0 },
  
    /* The UI field in a D form instruction.  */
! #define UI_np U_np + 1
! #define UI (U_np + 1)
    { 16, 0, 0, 0, 0 },
  };
  
:END:PATCH:HUNKS:
# eof

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