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* [binutils-gdb] drop XC16x bits
@ 2022-06-27  9:12 Jan Beulich
  0 siblings, 0 replies; only message in thread
From: Jan Beulich @ 2022-06-27  9:12 UTC (permalink / raw)
  To: bfd-cvs

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=ddd7bf3e2881aa339dc3ad4a36efc8ee3c3f7192

commit ddd7bf3e2881aa339dc3ad4a36efc8ee3c3f7192
Author: Jan Beulich <jbeulich@suse.com>
Date:   Mon Jun 27 11:11:46 2022 +0200

    drop XC16x bits
    
    Commit 04f096fb9e25 ("Move the xc16x target to the obsolete list") moved
    the architecture from the "obsolete but still available" to the
    "obsolete / support removed" list in config.bfd, making the architecture
    impossible to enable (except maybe via "enable everything" options").
    
    Note that I didn't touch */po/*.po{,t} on the assumption that these
    would be updated by some (half)automatic means.

Diff:
---
 bfd/Makefile.am                       |    4 -
 bfd/Makefile.in                       |    6 -
 bfd/archures.c                        |    6 -
 bfd/bfd-in2.h                         |   10 -
 bfd/config.bfd                        |    4 -
 bfd/configure                         |    1 -
 bfd/configure.ac                      |    1 -
 bfd/cpu-xc16x.c                       |   53 -
 bfd/elf32-xc16x.c                     |  487 -----
 bfd/libbfd.h                          |    4 -
 bfd/po/SRC-POTFILES.in                |    2 -
 bfd/reloc.c                           |   11 -
 bfd/targets.c                         |    3 -
 binutils/readelf.c                    |   14 -
 cpu/xc16x.cpu                         | 3146 -----------------------------
 cpu/xc16x.opc                         |  290 ---
 gas/Makefile.am                       |    2 -
 gas/Makefile.in                       |    5 -
 gas/config/tc-xc16x.c                 |  350 ----
 gas/config/tc-xc16x.h                 |   59 -
 gas/configure                         |    4 -
 gas/configure.ac                      |    4 -
 gas/doc/all.texi                      |    1 -
 gas/doc/c-xc16x.texi                  |   80 -
 gas/po/POTFILES.in                    |    2 -
 gas/testsuite/gas/xc16x/add.s         |   17 -
 gas/testsuite/gas/xc16x/add_test.s    |   92 -
 gas/testsuite/gas/xc16x/addb.s        |   11 -
 gas/testsuite/gas/xc16x/addc.s        |   11 -
 gas/testsuite/gas/xc16x/addcb.s       |   17 -
 gas/testsuite/gas/xc16x/and.s         |   14 -
 gas/testsuite/gas/xc16x/andb.s        |   10 -
 gas/testsuite/gas/xc16x/bfldl.s       |    4 -
 gas/testsuite/gas/xc16x/bit.s         |   11 -
 gas/testsuite/gas/xc16x/calla.s       |   24 -
 gas/testsuite/gas/xc16x/calli.s       |   21 -
 gas/testsuite/gas/xc16x/cmp.s         |    9 -
 gas/testsuite/gas/xc16x/cmp_test.s    |   45 -
 gas/testsuite/gas/xc16x/cmpb.s        |    8 -
 gas/testsuite/gas/xc16x/cmpi.s        |   18 -
 gas/testsuite/gas/xc16x/cpl.s         |    7 -
 gas/testsuite/gas/xc16x/div.s         |    8 -
 gas/testsuite/gas/xc16x/jmpa.s        |   23 -
 gas/testsuite/gas/xc16x/jmpi.s        |   24 -
 gas/testsuite/gas/xc16x/jmpr.s        |   25 -
 gas/testsuite/gas/xc16x/mov.s         |   20 -
 gas/testsuite/gas/xc16x/mov_test.s    |   85 -
 gas/testsuite/gas/xc16x/movb.s        |   26 -
 gas/testsuite/gas/xc16x/movbs.s       |    8 -
 gas/testsuite/gas/xc16x/movbz.s       |    9 -
 gas/testsuite/gas/xc16x/mul.s         |    6 -
 gas/testsuite/gas/xc16x/neg.s         |    6 -
 gas/testsuite/gas/xc16x/nop.s         |    6 -
 gas/testsuite/gas/xc16x/or.s          |   11 -
 gas/testsuite/gas/xc16x/orb.s         |   10 -
 gas/testsuite/gas/xc16x/prior.s       |    5 -
 gas/testsuite/gas/xc16x/pushpop.s     |    5 -
 gas/testsuite/gas/xc16x/ret.s         |    9 -
 gas/testsuite/gas/xc16x/scxt.s        |    6 -
 gas/testsuite/gas/xc16x/shlrol.s      |   14 -
 gas/testsuite/gas/xc16x/sub.s         |   19 -
 gas/testsuite/gas/xc16x/sub_test.s    |   70 -
 gas/testsuite/gas/xc16x/subb.s        |   19 -
 gas/testsuite/gas/xc16x/subc.s        |   19 -
 gas/testsuite/gas/xc16x/subcb.s       |   20 -
 gas/testsuite/gas/xc16x/syscontrol1.s |   12 -
 gas/testsuite/gas/xc16x/syscontrol2.s |   26 -
 gas/testsuite/gas/xc16x/trap.s        |    6 -
 gas/testsuite/gas/xc16x/xc16x.exp     | 1333 -------------
 gas/testsuite/gas/xc16x/xor.s         |   10 -
 gas/testsuite/gas/xc16x/xorb.s        |   10 -
 include/elf/xc16x.h                   |   40 -
 ld/Makefile.am                        |    6 -
 ld/Makefile.in                        |    9 -
 ld/configure.tgt                      |    3 -
 ld/emulparams/elf32xc16x.sh           |    8 -
 ld/emulparams/elf32xc16xl.sh          |    8 -
 ld/emulparams/elf32xc16xs.sh          |    8 -
 ld/po/BLD-POTFILES.in                 |    3 -
 ld/scripttempl/elf32xc16x.sc          |   80 -
 ld/scripttempl/elf32xc16xl.sc         |   80 -
 ld/scripttempl/elf32xc16xs.sc         |   81 -
 ld/testsuite/ld-elf/elf.exp           |    1 -
 ld/testsuite/ld-elf/pr22450.d         |    4 +-
 ld/testsuite/ld-elf/pr23658-1a.d      |    2 +-
 ld/testsuite/ld-xc16x/absrel.d        |   28 -
 ld/testsuite/ld-xc16x/absrel.s        |   31 -
 ld/testsuite/ld-xc16x/offset.d        |   18 -
 ld/testsuite/ld-xc16x/offset.s        |   13 -
 ld/testsuite/ld-xc16x/pcreloc.d       |   34 -
 ld/testsuite/ld-xc16x/pcreloc.s       |   27 -
 ld/testsuite/ld-xc16x/pcrelocl.d      |   34 -
 ld/testsuite/ld-xc16x/xc16x.exp       |   68 -
 opcodes/Makefile.am                   |   21 +-
 opcodes/Makefile.in                   |   26 +-
 opcodes/configure                     |    1 -
 opcodes/configure.ac                  |    1 -
 opcodes/disassemble.c                 |    6 -
 opcodes/disassemble.h                 |    1 -
 opcodes/po/POTFILES.in                |    7 -
 opcodes/xc16x-asm.c                   |  786 --------
 opcodes/xc16x-desc.c                  | 3521 ---------------------------------
 opcodes/xc16x-desc.h                  |  456 -----
 opcodes/xc16x-dis.c                   |  849 --------
 opcodes/xc16x-ibld.c                  | 1830 -----------------
 opcodes/xc16x-opc.c                   | 3049 ----------------------------
 opcodes/xc16x-opc.h                   |  234 ---
 107 files changed, 7 insertions(+), 18085 deletions(-)

diff --git a/bfd/Makefile.am b/bfd/Makefile.am
index 92ff15b36ee..670e0598f55 100644
--- a/bfd/Makefile.am
+++ b/bfd/Makefile.am
@@ -171,7 +171,6 @@ ALL_MACHINES = \
 	cpu-vax.lo \
 	cpu-visium.lo \
 	cpu-wasm32.lo \
-	cpu-xc16x.lo \
 	cpu-xgate.lo \
 	cpu-xstormy16.lo \
 	cpu-xtensa.lo \
@@ -255,7 +254,6 @@ ALL_MACHINES_CFILES = \
 	cpu-vax.c \
 	cpu-visium.c \
 	cpu-wasm32.c \
-	cpu-xc16x.c \
 	cpu-xgate.c \
 	cpu-xstormy16.c \
 	cpu-xtensa.c \
@@ -352,7 +350,6 @@ BFD32_BACKENDS = \
 	elf32-vax.lo \
 	elf32-visium.lo \
 	elf32-wasm32.lo \
-	elf32-xc16x.lo \
 	elf32-xgate.lo \
 	elf32-xstormy16.lo \
 	elf32-xtensa.lo \
@@ -485,7 +482,6 @@ BFD32_BACKENDS_CFILES = \
 	elf32-vax.c \
 	elf32-visium.c \
 	elf32-wasm32.c \
-	elf32-xc16x.c \
 	elf32-xgate.c \
 	elf32-xstormy16.c \
 	elf32-xtensa.c \
diff --git a/bfd/Makefile.in b/bfd/Makefile.in
index 741e08d603c..d3ef4c2524b 100644
--- a/bfd/Makefile.in
+++ b/bfd/Makefile.in
@@ -633,7 +633,6 @@ ALL_MACHINES = \
 	cpu-vax.lo \
 	cpu-visium.lo \
 	cpu-wasm32.lo \
-	cpu-xc16x.lo \
 	cpu-xgate.lo \
 	cpu-xstormy16.lo \
 	cpu-xtensa.lo \
@@ -717,7 +716,6 @@ ALL_MACHINES_CFILES = \
 	cpu-vax.c \
 	cpu-visium.c \
 	cpu-wasm32.c \
-	cpu-xc16x.c \
 	cpu-xgate.c \
 	cpu-xstormy16.c \
 	cpu-xtensa.c \
@@ -815,7 +813,6 @@ BFD32_BACKENDS = \
 	elf32-vax.lo \
 	elf32-visium.lo \
 	elf32-wasm32.lo \
-	elf32-xc16x.lo \
 	elf32-xgate.lo \
 	elf32-xstormy16.lo \
 	elf32-xtensa.lo \
@@ -948,7 +945,6 @@ BFD32_BACKENDS_CFILES = \
 	elf32-vax.c \
 	elf32-visium.c \
 	elf32-wasm32.c \
-	elf32-xc16x.c \
 	elf32-xgate.c \
 	elf32-xstormy16.c \
 	elf32-xtensa.c \
@@ -1549,7 +1545,6 @@ distclean-compile:
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-vax.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-visium.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-wasm32.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-xc16x.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-xgate.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-xstormy16.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-xtensa.Plo@am__quote@
@@ -1632,7 +1627,6 @@ distclean-compile:
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-vax.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-visium.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-wasm32.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-xc16x.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-xgate.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-xstormy16.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-xtensa.Plo@am__quote@
diff --git a/bfd/archures.c b/bfd/archures.c
index bcd2b1cf48b..c67bacddfdc 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -487,10 +487,6 @@ DESCRIPTION
 .#define bfd_mach_msp46		46
 .#define bfd_mach_msp47		47
 .#define bfd_mach_msp54		54
-.  bfd_arch_xc16x,     {* Infineon's XC16X Series.  *}
-.#define bfd_mach_xc16x		1
-.#define bfd_mach_xc16xl	2
-.#define bfd_mach_xc16xs	3
 .  bfd_arch_xgate,     {* Freescale XGATE.  *}
 .#define bfd_mach_xgate		1
 .  bfd_arch_xtensa,    {* Tensilica's Xtensa cores.  *}
@@ -698,7 +694,6 @@ extern const bfd_arch_info_type bfd_visium_arch;
 extern const bfd_arch_info_type bfd_wasm32_arch;
 extern const bfd_arch_info_type bfd_xstormy16_arch;
 extern const bfd_arch_info_type bfd_xtensa_arch;
-extern const bfd_arch_info_type bfd_xc16x_arch;
 extern const bfd_arch_info_type bfd_xgate_arch;
 extern const bfd_arch_info_type bfd_z80_arch;
 extern const bfd_arch_info_type bfd_z8k_arch;
@@ -785,7 +780,6 @@ static const bfd_arch_info_type * const bfd_archures_list[] =
     &bfd_wasm32_arch,
     &bfd_xstormy16_arch,
     &bfd_xtensa_arch,
-    &bfd_xc16x_arch,
     &bfd_xgate_arch,
     &bfd_z80_arch,
     &bfd_z8k_arch,
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 14d37630c79..4e1182e93d4 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1824,10 +1824,6 @@ enum bfd_architecture
 #define bfd_mach_msp46         46
 #define bfd_mach_msp47         47
 #define bfd_mach_msp54         54
-  bfd_arch_xc16x,     /* Infineon's XC16X Series.  */
-#define bfd_mach_xc16x         1
-#define bfd_mach_xc16xl        2
-#define bfd_mach_xc16xs        3
   bfd_arch_xgate,     /* Freescale XGATE.  */
 #define bfd_mach_xgate         1
   bfd_arch_xtensa,    /* Tensilica's Xtensa cores.  */
@@ -5028,12 +5024,6 @@ then it may be truncated to 8 bits.  */
   BFD_RELOC_RELC,
 
 
-/* Infineon Relocations.  */
-  BFD_RELOC_XC16X_PAG,
-  BFD_RELOC_XC16X_POF,
-  BFD_RELOC_XC16X_SEG,
-  BFD_RELOC_XC16X_SOF,
-
 /* Relocations used by VAX ELF.  */
   BFD_RELOC_VAX_GLOB_DAT,
   BFD_RELOC_VAX_JMP_SLOT,
diff --git a/bfd/config.bfd b/bfd/config.bfd
index 2a6aec28036..8dcb4e0de3c 100644
--- a/bfd/config.bfd
+++ b/bfd/config.bfd
@@ -1431,10 +1431,6 @@ case "${targ}" in
     targ_selvecs="wasm_vec"
     ;;
 
-  xc16x-*-elf)
-    targ_defvec=xc16x_elf32_vec
-    ;;
-
   xgate-*-*)
     targ_defvec=xgate_elf32_vec
     targ_selvecs="xgate_elf32_vec"
diff --git a/bfd/configure b/bfd/configure
index 3d2656229e5..33ef7656017 100755
--- a/bfd/configure
+++ b/bfd/configure
@@ -13587,7 +13587,6 @@ do
     x86_64_pe_vec)		 tb="$tb pe-x86_64.lo pex64igen.lo $coff"; target_size=64 ;;
     x86_64_pe_big_vec)		 tb="$tb pe-x86_64.lo pex64igen.lo $coff"; target_size=64 ;;
     x86_64_pei_vec)		 tb="$tb pei-x86_64.lo pex64igen.lo $coff"; target_size=64 ;;
-    xc16x_elf32_vec)		 tb="$tb elf32-xc16x.lo elf32.lo $elf" ;;
     xgate_elf32_vec)		 tb="$tb elf32-xgate.lo elf32.lo $elf" ;;
     xstormy16_elf32_vec)	 tb="$tb elf32-xstormy16.lo elf32.lo $elf" ;;
     xtensa_elf32_be_vec)	 tb="$tb xtensa-isa.lo xtensa-modules.lo elf32-xtensa.lo elf32.lo $elf" ;;
diff --git a/bfd/configure.ac b/bfd/configure.ac
index 8ad0e05959d..aad4f3c83a5 100644
--- a/bfd/configure.ac
+++ b/bfd/configure.ac
@@ -665,7 +665,6 @@ do
     x86_64_pe_vec)		 tb="$tb pe-x86_64.lo pex64igen.lo $coff"; target_size=64 ;;
     x86_64_pe_big_vec)		 tb="$tb pe-x86_64.lo pex64igen.lo $coff"; target_size=64 ;;
     x86_64_pei_vec)		 tb="$tb pei-x86_64.lo pex64igen.lo $coff"; target_size=64 ;;
-    xc16x_elf32_vec)		 tb="$tb elf32-xc16x.lo elf32.lo $elf" ;;
     xgate_elf32_vec)		 tb="$tb elf32-xgate.lo elf32.lo $elf" ;;
     xstormy16_elf32_vec)	 tb="$tb elf32-xstormy16.lo elf32.lo $elf" ;;
     xtensa_elf32_be_vec)	 tb="$tb xtensa-isa.lo xtensa-modules.lo elf32-xtensa.lo elf32.lo $elf" ;;
diff --git a/bfd/cpu-xc16x.c b/bfd/cpu-xc16x.c
deleted file mode 100644
index bd10242a94b..00000000000
--- a/bfd/cpu-xc16x.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/* BFD support for the Infineon XC16X Microcontroller.
-   Copyright (C) 2006-2022 Free Software Foundation, Inc.
-   Contributed by KPIT Cummins Infosystems
-
-   This file is part of BFD, the Binary File Descriptor library.
-   Contributed by Anil Paranjpe(anilp1@kpitcummins.com)
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 3 of the License, or
-   (at your option) any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software
-   Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
-   02110-1301, USA.  */
-
-#include "sysdep.h"
-#include "bfd.h"
-#include "libbfd.h"
-
-#define N(BITS_ADDR, NUMBER, PRINT, DEFAULT, NEXT)	\
-  {							\
-    16,        /* Bits in a word.  */			\
-    BITS_ADDR, /* Bits in an address.  */		\
-    8,	       /* Bits in a byte.  */			\
-    bfd_arch_xc16x,					\
-    NUMBER,						\
-    "xc16x",						\
-    PRINT,						\
-    1,		/* Section alignment power.  */		\
-    DEFAULT,						\
-    bfd_default_compatible,				\
-    bfd_default_scan,					\
-    bfd_arch_default_fill,				\
-    NEXT,						\
-    0 /* Maximum offset of a reloc from the start of an insn.  */ \
-  }
-
-const bfd_arch_info_type xc16xs_info_struct =
-  N (16, bfd_mach_xc16xs, "xc16xs", false, NULL);
-
-const bfd_arch_info_type xc16xl_info_struct =
-  N (32, bfd_mach_xc16xl, "xc16xl", false, & xc16xs_info_struct);
-
-const bfd_arch_info_type bfd_xc16x_arch =
-  N (16, bfd_mach_xc16x, "xc16x", true, & xc16xl_info_struct);
-
diff --git a/bfd/elf32-xc16x.c b/bfd/elf32-xc16x.c
deleted file mode 100644
index 99cba147cde..00000000000
--- a/bfd/elf32-xc16x.c
+++ /dev/null
@@ -1,487 +0,0 @@
-/* Infineon XC16X-specific support for 16-bit ELF.
-   Copyright (C) 2006-2022 Free Software Foundation, Inc.
-   Contributed by KPIT Cummins Infosystems
-
-   This file is part of BFD, the Binary File Descriptor library.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 3 of the License, or
-   (at your option) any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software
-   Foundation, 51 Franklin Street - Fifth Floor, Boston,
-   MA 02110-1301, USA.  */
-
-#include "sysdep.h"
-#include "bfd.h"
-#include "libbfd.h"
-#include "elf-bfd.h"
-#include "elf/xc16x.h"
-#include "dwarf2.h"
-#include "libiberty.h"
-
-static reloc_howto_type xc16x_elf_howto_table [] =
-{
-  /* This reloc does nothing.  */
-  HOWTO (R_XC16X_NONE,		/* type */
-	 0,			/* rightshift */
-	 0,			/* size */
-	 0,			/* bitsize */
-	 false,			/* pc_relative */
-	 0,			/* bitpos */
-	 complain_overflow_dont, /* complain_on_overflow */
-	 bfd_elf_generic_reloc,	/* special_function */
-	 "R_XC16X_NONE",	/* name */
-	 false,			/* partial_inplace */
-	 0,			/* src_mask */
-	 0,			/* dst_mask */
-	 false),		/* pcrel_offset */
-
-  /* An 8 bit absolute relocation.  */
-  HOWTO (R_XC16X_ABS_8,		/* type */
-	 0,			/* rightshift */
-	 1,			/* size */
-	 8,			/* bitsize */
-	 false,			/* pc_relative */
-	 8,			/* bitpos */
-	 complain_overflow_bitfield, /* complain_on_overflow */
-	 bfd_elf_generic_reloc,	/* special_function */
-	 "R_XC16X_ABS_8",	/* name */
-	 true,			/* partial_inplace */
-	 0x0000,		/* src_mask */
-	 0x00ff,		/* dst_mask */
-	 false),		/* pcrel_offset */
-
-  /* A 16 bit absolute relocation.  */
-  HOWTO (R_XC16X_ABS_16,	/* type */
-	 0,			/* rightshift */
-	 2,			/* size */
-	 16,			/* bitsize */
-	 false,			/* pc_relative */
-	 0,			/* bitpos */
-	 complain_overflow_dont, /* complain_on_overflow */
-	 bfd_elf_generic_reloc,	/* special_function */
-	 "R_XC16X_ABS_16",	/* name */
-	 true,			/* partial_inplace */
-	 0x00000000,		/* src_mask */
-	 0x0000ffff,		/* dst_mask */
-	 false),		/* pcrel_offset */
-
-  HOWTO (R_XC16X_ABS_32,	/* type */
-	 0,			/* rightshift */
-	 4,			/* size */
-	 32,			/* bitsize */
-	 false,			/* pc_relative */
-	 0,			/* bitpos */
-	 complain_overflow_bitfield, /* complain_on_overflow */
-	 bfd_elf_generic_reloc,	/* special_function */
-	 "R_XC16X_ABS_32",	/* name */
-	 true,			/* partial_inplace */
-	 0x00000000,		/* src_mask */
-	 0xffffffff,		/* dst_mask */
-	 false),		/* pcrel_offset */
-
-
-  /* A PC relative 8 bit relocation.  */
-  HOWTO (R_XC16X_8_PCREL,	/* type */
-	 0,			/* rightshift */
-	 1,			/* size */
-	 8,			/* bitsize */
-	 true,			/* pc_relative */
-	 8,			/* bitpos */
-	 complain_overflow_signed, /* complain_on_overflow */
-	 bfd_elf_generic_reloc, /* special_function */
-	 "R_XC16X_8_PCREL",	/* name */
-	 false,			/* partial_inplace */
-	 0x0000,		/* src_mask */
-	 0x00ff,		/* dst_mask */
-	 true),		/* pcrel_offset */
-
-  /* Relocation regarding page number.  */
-    HOWTO (R_XC16X_PAG,	/* type */
-	 0,			/* rightshift */
-	 2,			/* size */
-	 16,			/* bitsize */
-	 false,			/* pc_relative */
-	 0,			/* bitpos */
-	 complain_overflow_signed, /* complain_on_overflow */
-	 bfd_elf_generic_reloc, /* special_function */
-	 "R_XC16X_PAG",	/* name */
-	 true,			/* partial_inplace */
-	 0x00000000,		/* src_mask */
-	 0x0000ffff,		/* dst_mask */
-	 false),		/* pcrel_offset */
-
-
-  /* Relocation regarding page number.  */
-      HOWTO (R_XC16X_POF,	/* type */
-	 0,			/* rightshift */
-	 2,			/* size */
-	 16,			/* bitsize */
-	 false,			/* pc_relative */
-	 0,			/* bitpos  */
-	 complain_overflow_signed, /* complain_on_overflow  */
-	 bfd_elf_generic_reloc, /* special_function  */
-	 "R_XC16X_POF",	/* name  */
-	 true,			/* partial_inplace  */
-	 0x00000000,		/* src_mask  */
-	 0x0000ffff,		/* dst_mask  */
-	 false),		/* pcrel_offset  */
-
-
-  /* Relocation regarding segment number.   */
-      HOWTO (R_XC16X_SEG,	/* type  */
-	 0,			/* rightshift  */
-	 2,			/* size  */
-	 16,			/* bitsize  */
-	 false,			/* pc_relative  */
-	 0,			/* bitpos  */
-	 complain_overflow_signed, /* complain_on_overflow  */
-	 bfd_elf_generic_reloc, /* special_function  */
-	 "R_XC16X_SEG",	/* name  */
-	 true,			/* partial_inplace  */
-	 0x00000000,		/* src_mask  */
-	 0x0000ffff,		/* dst_mask  */
-	 false),		/* pcrel_offset  */
-
-  /* Relocation regarding segment offset.  */
-      HOWTO (R_XC16X_SOF,	/* type  */
-	 0,			/* rightshift  */
-	 2,			/* size  */
-	 16,			/* bitsize  */
-	 false,			/* pc_relative  */
-	 0,			/* bitpos  */
-	 complain_overflow_signed, /* complain_on_overflow  */
-	 bfd_elf_generic_reloc, /* special_function  */
-	 "R_XC16X_SOF",	/* name */
-	 true,			/* partial_inplace  */
-	 0x00000000,		/* src_mask  */
-	 0x0000ffff,		/* dst_mask  */
-	 false)			/* pcrel_offset  */
-};
-
-
-/* Map BFD reloc types to XC16X ELF reloc types.  */
-
-struct xc16x_reloc_map
-{
-  bfd_reloc_code_real_type bfd_reloc_val;
-  unsigned int xc16x_reloc_val;
-};
-
-static const struct xc16x_reloc_map xc16x_reloc_map [] =
-{
-  { BFD_RELOC_NONE,	      R_XC16X_NONE },
-  { BFD_RELOC_8,	      R_XC16X_ABS_8 },
-  { BFD_RELOC_16,	      R_XC16X_ABS_16 },
-  { BFD_RELOC_32,	      R_XC16X_ABS_32 },
-  { BFD_RELOC_8_PCREL,	      R_XC16X_8_PCREL },
-  { BFD_RELOC_XC16X_PAG,      R_XC16X_PAG},
-  { BFD_RELOC_XC16X_POF,      R_XC16X_POF},
-  { BFD_RELOC_XC16X_SEG,      R_XC16X_SEG},
-  { BFD_RELOC_XC16X_SOF,      R_XC16X_SOF},
-};
-
-
-/* This function is used to search for correct relocation type from
-   howto structure.  */
-
-static reloc_howto_type *
-xc16x_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
-			 bfd_reloc_code_real_type code)
-{
-  unsigned int i;
-
-  for (i = ARRAY_SIZE (xc16x_reloc_map); --i;)
-    if (xc16x_reloc_map [i].bfd_reloc_val == code)
-      return & xc16x_elf_howto_table [xc16x_reloc_map[i].xc16x_reloc_val];
-
-  return NULL;
-}
-
-static reloc_howto_type *
-xc16x_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
-			 const char *r_name)
-{
-  unsigned int i;
-
-  for (i = 0; i < ARRAY_SIZE (xc16x_elf_howto_table); i++)
-    if (xc16x_elf_howto_table[i].name != NULL
-	&& strcasecmp (xc16x_elf_howto_table[i].name, r_name) == 0)
-      return &xc16x_elf_howto_table[i];
-
-  return NULL;
-}
-
-static reloc_howto_type *
-elf32_xc16x_rtype_to_howto (bfd *abfd ATTRIBUTE_UNUSED, unsigned r_type)
-{
-  if (r_type < ARRAY_SIZE (xc16x_elf_howto_table))
-    return & xc16x_elf_howto_table[r_type];
-
-  return NULL;
-}
-
-/* For a particular operand this function is
-   called to finalise the type of relocation.  */
-
-static bool
-elf32_xc16x_info_to_howto (bfd *abfd, arelent *bfd_reloc,
-			   Elf_Internal_Rela *elf_reloc)
-{
-  unsigned int r;
-  unsigned int i;
-
-  r = ELF32_R_TYPE (elf_reloc->r_info);
-  for (i = 0; i < ARRAY_SIZE (xc16x_elf_howto_table); i++)
-    if (xc16x_elf_howto_table[i].type == r)
-      {
-	bfd_reloc->howto = &xc16x_elf_howto_table[i];
-	return true;
-      }
-  /* xgettext:c-format */
-  _bfd_error_handler (_("%pB: unsupported relocation type %#x"), abfd, r);
-  bfd_set_error (bfd_error_bad_value);
-  return false;
-}
-
-static bfd_reloc_status_type
-elf32_xc16x_final_link_relocate (unsigned long r_type,
-				 bfd *input_bfd,
-				 bfd *output_bfd ATTRIBUTE_UNUSED,
-				 asection *input_section ATTRIBUTE_UNUSED,
-				 bfd_byte *contents,
-				 bfd_vma offset,
-				 bfd_vma value,
-				 bfd_vma addend,
-				 struct bfd_link_info *info ATTRIBUTE_UNUSED,
-				 asection *sym_sec ATTRIBUTE_UNUSED,
-				 int is_local ATTRIBUTE_UNUSED)
-{
-  bfd_byte *hit_data = contents + offset;
-  bfd_vma val1;
-
-  switch (r_type)
-    {
-    case R_XC16X_NONE:
-      return bfd_reloc_ok;
-
-    case R_XC16X_ABS_16:
-      value += addend;
-      bfd_put_16 (input_bfd, value, hit_data);
-      return bfd_reloc_ok;
-
-    case R_XC16X_8_PCREL:
-      bfd_put_8 (input_bfd, value, hit_data);
-      return bfd_reloc_ok;
-
-      /* Following case is to find page number from actual
-	 address for this divide value by 16k i.e. page size.  */
-
-    case R_XC16X_PAG:
-      value += addend;
-      value /= 0x4000;
-      bfd_put_16 (input_bfd, value, hit_data);
-      return bfd_reloc_ok;
-
-      /* Following case is to find page offset from actual address
-	 for this take modulo of value by 16k i.e. page size.  */
-
-    case R_XC16X_POF:
-      value += addend;
-      value %= 0x4000;
-      bfd_put_16 (input_bfd, value, hit_data);
-      return bfd_reloc_ok;
-
-      /* Following case is to find segment number from actual
-	 address for this divide value by 64k i.e. segment size.  */
-
-    case R_XC16X_SEG:
-      value += addend;
-      value /= 0x10000;
-      bfd_put_16 (input_bfd, value, hit_data);
-      return bfd_reloc_ok;
-
-      /* Following case is to find segment offset from actual address
-	 for this take modulo of value by 64k i.e. segment size.  */
-
-    case R_XC16X_SOF:
-      value += addend;
-      value %= 0x10000;
-      bfd_put_16 (input_bfd, value, hit_data);
-      return bfd_reloc_ok;
-
-    case R_XC16X_ABS_32:
-      if (!strstr (input_section->name,".debug"))
-	{
-	  value += addend;
-	  val1 = value;
-	  value %= 0x4000;
-	  val1 /= 0x4000;
-	  val1 = val1 << 16;
-	  value += val1;
-	  bfd_put_32 (input_bfd, value, hit_data);
-	}
-      else
-	{
-	  value += addend;
-	  bfd_put_32 (input_bfd, value, hit_data);
-	}
-      return bfd_reloc_ok;
-
-    default:
-      return bfd_reloc_notsupported;
-    }
-}
-
-static int
-elf32_xc16x_relocate_section (bfd *output_bfd,
-			      struct bfd_link_info *info,
-			      bfd *input_bfd,
-			      asection *input_section,
-			      bfd_byte *contents,
-			      Elf_Internal_Rela *relocs,
-			      Elf_Internal_Sym *local_syms,
-			      asection **local_sections)
-{
-  Elf_Internal_Shdr *symtab_hdr;
-  struct elf_link_hash_entry **sym_hashes;
-  Elf_Internal_Rela *rel, *relend;
-
-  symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
-  sym_hashes = elf_sym_hashes (input_bfd);
-
-  rel = relocs;
-  relend = relocs + input_section->reloc_count;
-  for (; rel < relend; rel++)
-    {
-      unsigned int r_type;
-      unsigned long r_symndx;
-      Elf_Internal_Sym *sym;
-      asection *sec;
-      struct elf_link_hash_entry *h;
-      bfd_vma relocation;
-
-      /* This is a final link.  */
-      r_symndx = ELF32_R_SYM (rel->r_info);
-      r_type = ELF32_R_TYPE (rel->r_info);
-      h = NULL;
-      sym = NULL;
-      sec = NULL;
-      if (r_symndx < symtab_hdr->sh_info)
-	{
-	  sym = local_syms + r_symndx;
-	  sec = local_sections[r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
-	}
-      else
-	{
-	  bool unresolved_reloc, warned, ignored;
-
-	  RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
-				   r_symndx, symtab_hdr, sym_hashes,
-				   h, sec, relocation,
-				   unresolved_reloc, warned, ignored);
-	}
-
-      if (sec != NULL && discarded_section (sec))
-	{
-	  /* For relocs against symbols from removed linkonce sections,
-	     or sections discarded by a linker script, we just want the
-	     section contents cleared.  Avoid any special processing.  */
-	  reloc_howto_type *howto;
-	  howto = elf32_xc16x_rtype_to_howto (input_bfd, r_type);
-	  RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
-					   rel, 1, relend, howto, 0, contents);
-	}
-
-      if (bfd_link_relocatable (info))
-	continue;
-
-      elf32_xc16x_final_link_relocate (r_type, input_bfd, output_bfd,
-				       input_section,
-				       contents, rel->r_offset,
-				       relocation, rel->r_addend,
-				       info, sec, h == NULL);
-    }
-
-  return true;
-}
-
-
-static bool
-elf32_xc16x_final_write_processing (bfd *abfd)
-{
-  unsigned long val;
-
-  switch (bfd_get_mach (abfd))
-    {
-    default:
-    case bfd_mach_xc16x:
-      val = 0x1000;
-      break;
-
-    case bfd_mach_xc16xl:
-      val = 0x1001;
-      break;
-
-    case bfd_mach_xc16xs:
-      val = 0x1002;
-      break;
-    }
-
-  elf_elfheader (abfd)->e_flags |= val;
-  return _bfd_elf_final_write_processing (abfd);
-}
-
-static unsigned long
-elf32_xc16x_mach (flagword flags)
-{
-  switch (flags)
-    {
-    case 0x1000:
-    default:
-      return bfd_mach_xc16x;
-
-    case 0x1001:
-      return bfd_mach_xc16xl;
-
-    case 0x1002:
-      return bfd_mach_xc16xs;
-    }
-}
-
-
-static bool
-elf32_xc16x_object_p (bfd *abfd)
-{
-  bfd_default_set_arch_mach (abfd, bfd_arch_xc16x,
-			     elf32_xc16x_mach (elf_elfheader (abfd)->e_flags));
-  return true;
-}
-
-
-#define ELF_ARCH		bfd_arch_xc16x
-#define ELF_MACHINE_CODE	EM_XC16X
-#define ELF_MAXPAGESIZE		0x100
-
-#define TARGET_LITTLE_SYM       xc16x_elf32_vec
-#define TARGET_LITTLE_NAME	"elf32-xc16x"
-#define elf_backend_final_write_processing	elf32_xc16x_final_write_processing
-#define elf_backend_object_p		elf32_xc16x_object_p
-#define elf_backend_can_gc_sections	1
-#define bfd_elf32_bfd_reloc_type_lookup	xc16x_reloc_type_lookup
-#define bfd_elf32_bfd_reloc_name_lookup xc16x_reloc_name_lookup
-#define elf_info_to_howto		elf32_xc16x_info_to_howto
-#define elf_info_to_howto_rel		elf32_xc16x_info_to_howto
-#define elf_backend_relocate_section	elf32_xc16x_relocate_section
-#define elf_backend_rela_normal		1
-
-#include "elf32-target.h"
diff --git a/bfd/libbfd.h b/bfd/libbfd.h
index 4a3020cc122..29e8187f95f 100644
--- a/bfd/libbfd.h
+++ b/bfd/libbfd.h
@@ -2791,10 +2791,6 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
   "BFD_RELOC_XSTORMY16_FPTR16",
   "BFD_RELOC_RELC",
 
-  "BFD_RELOC_XC16X_PAG",
-  "BFD_RELOC_XC16X_POF",
-  "BFD_RELOC_XC16X_SEG",
-  "BFD_RELOC_XC16X_SOF",
   "BFD_RELOC_VAX_GLOB_DAT",
   "BFD_RELOC_VAX_JMP_SLOT",
   "BFD_RELOC_VAX_RELATIVE",
diff --git a/bfd/po/SRC-POTFILES.in b/bfd/po/SRC-POTFILES.in
index 59251e39858..2a8187d8dee 100644
--- a/bfd/po/SRC-POTFILES.in
+++ b/bfd/po/SRC-POTFILES.in
@@ -122,7 +122,6 @@ cpu-v850_rh850.c
 cpu-vax.c
 cpu-visium.c
 cpu-wasm32.c
-cpu-xc16x.c
 cpu-xgate.c
 cpu-xstormy16.c
 cpu-xtensa.c
@@ -231,7 +230,6 @@ elf32-v850.h
 elf32-vax.c
 elf32-visium.c
 elf32-wasm32.c
-elf32-xc16x.c
 elf32-xgate.c
 elf32-xstormy16.c
 elf32-xtensa.c
diff --git a/bfd/reloc.c b/bfd/reloc.c
index eb8dba36a83..36999fe9a40 100644
--- a/bfd/reloc.c
+++ b/bfd/reloc.c
@@ -6289,17 +6289,6 @@ ENUMDOC
   Self-describing complex relocations.
 COMMENT
 
-ENUM
-  BFD_RELOC_XC16X_PAG
-ENUMX
-  BFD_RELOC_XC16X_POF
-ENUMX
-  BFD_RELOC_XC16X_SEG
-ENUMX
-  BFD_RELOC_XC16X_SOF
-ENUMDOC
-  Infineon Relocations.
-
 ENUM
   BFD_RELOC_VAX_GLOB_DAT
 ENUMX
diff --git a/bfd/targets.c b/bfd/targets.c
index f44b5c67724..3284bb88aa8 100644
--- a/bfd/targets.c
+++ b/bfd/targets.c
@@ -933,7 +933,6 @@ extern const bfd_target x86_64_mach_o_vec;
 extern const bfd_target x86_64_pe_vec;
 extern const bfd_target x86_64_pe_big_vec;
 extern const bfd_target x86_64_pei_vec;
-extern const bfd_target xc16x_elf32_vec;
 extern const bfd_target xgate_elf32_vec;
 extern const bfd_target xstormy16_elf32_vec;
 extern const bfd_target xtensa_elf32_be_vec;
@@ -1344,8 +1343,6 @@ static const bfd_target * const _bfd_target_vector[] =
 	&x86_64_pei_vec,
 #endif
 
-	&xc16x_elf32_vec,
-
 	&xgate_elf32_vec,
 
 	&xstormy16_elf32_vec,
diff --git a/binutils/readelf.c b/binutils/readelf.c
index fe0d27decc3..0f5977bc072 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -163,7 +163,6 @@
 #include "elf/visium.h"
 #include "elf/wasm32.h"
 #include "elf/x86-64.h"
-#include "elf/xc16x.h"
 #include "elf/xgate.h"
 #include "elf/xstormy16.h"
 #include "elf/xtensa.h"
@@ -1882,11 +1881,6 @@ dump_relocations (Filedata *          filedata,
 	  rtype = elf_metag_reloc_type (type);
 	  break;
 
-	case EM_XC16X:
-	case EM_C166:
-	  rtype = elf_xc16x_reloc_type (type);
-	  break;
-
 	case EM_TI_C6000:
 	  rtype = elf_tic6x_reloc_type (type);
 	  break;
@@ -14343,9 +14337,6 @@ is_32bit_abs_reloc (Filedata * filedata, unsigned int reloc_type)
     case EM_L1OM:
     case EM_K1OM:
       return reloc_type == 10; /* R_X86_64_32.  */
-    case EM_XC16X:
-    case EM_C166:
-      return reloc_type == 3; /* R_XC16C_ABS_32.  */
     case EM_XGATE:
       return reloc_type == 4; /* R_XGATE_32.  */
     case EM_XSTORMY16:
@@ -14607,9 +14598,6 @@ is_16bit_abs_reloc (Filedata * filedata, unsigned int reloc_type)
       return reloc_type == 2; /* R_C6000_ABS16.  */
     case EM_VISIUM:
       return reloc_type == 2; /* R_VISIUM_16. */
-    case EM_XC16X:
-    case EM_C166:
-      return reloc_type == 2; /* R_XC16C_ABS_16.  */
     case EM_XGATE:
       return reloc_type == 3; /* R_XGATE_16.  */
     case EM_Z80:
@@ -14811,7 +14799,6 @@ is_none_reloc (Filedata * filedata, unsigned int reloc_type)
     case EM_ARC_COMPACT2: /* R_ARC_NONE.  */
     case EM_ARC_COMPACT: /* R_ARC_NONE.  */
     case EM_ARM:     /* R_ARM_NONE.  */
-    case EM_C166:    /* R_XC16X_NONE.  */
     case EM_CRIS:    /* R_CRIS_NONE.  */
     case EM_FT32:    /* R_FT32_NONE.  */
     case EM_IA_64:   /* R_IA64_NONE.  */
@@ -14837,7 +14824,6 @@ is_none_reloc (Filedata * filedata, unsigned int reloc_type)
     case EM_TILEPRO: /* R_TILEPRO_NONE.  */
     case EM_TI_C6000:/* R_C6000_NONE.  */
     case EM_X86_64:  /* R_X86_64_NONE.  */
-    case EM_XC16X:
     case EM_Z80:     /* R_Z80_NONE. */
     case EM_WEBASSEMBLY: /* R_WASM32_NONE.  */
       return reloc_type == 0;
diff --git a/cpu/xc16x.cpu b/cpu/xc16x.cpu
deleted file mode 100644
index 4903b814c91..00000000000
--- a/cpu/xc16x.cpu
+++ /dev/null
@@ -1,3146 +0,0 @@
-; Infineon XC16X CPU description.  -*- Scheme -*-
-;
-; Copyright 2006, 2007, 2009 Free Software Foundation, Inc.
-;
-; Contributed by KPIT Cummins Infosystems Ltd.; developed under contract 
-; from Infineon Systems, GMBH , Germany.
-;
-; This file is part of the GNU Binutils.
-;
-; This program is free software; you can redistribute it and/or modify
-; it under the terms of the GNU General Public License as published by
-; the Free Software Foundation; either version 3 of the License, or
-; (at your option) any later version.
-;
-; This program is distributed in the hope that it will be useful,
-; but WITHOUT ANY WARRANTY; without even the implied warranty of
-; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-; GNU General Public License for more details.
-;
-; You should have received a copy of the GNU General Public License
-; along with this program; if not, write to the Free Software
-; Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
-; 02110-1301, USA.
-
-(define-rtl-version 0 8)
-
-(include "simplify.inc")
-
-; define-arch appears first
-
-(define-arch
-  (name xc16x) ; name of cpu family
-  (comment "Infineon XC16X")
-  (default-alignment aligned)
-  (insn-lsb0? #t)		
-  (machs xc16x)
-  (isas xc16x)
-)
-
-; Attributes.   
-; An attribute to describe which pipeline an insn runs in generally OS.
-(define-attr
-  (for insn)
-  (type enum)
-  (name PIPE)
-  (comment "parallel execution pipeline selection")
-  (values NONE OS)
-)
-
-; Instruction set parameters.
-
-(define-isa
-  (name xc16x)
-  (default-insn-bitsize 32)
-  (base-insn-bitsize 32)
-  (default-insn-word-bitsize 16)
-  (decode-assist (15 14 13 12))
-  ; The XC16X fetches 1 insn at a time.
-  (liw-insns 1)
-  (parallel-insns 1)
-)
-
-; Cpu family definitions.
-
-(define-cpu
-  ; cpu names must be distinct from the architecture name and machine names.
-  ; The "b" suffix stands for "base" and is the convention.
-  ; The "f" suffix stands for "family" and is the convention.
-  (name xc16xbf)
-  (comment "Infineon XC16X base family")
-  (endian little)
-  (insn-chunk-bitsize 32)
-  (word-bitsize 16)
-  (parallel-insns 1)
-)
-
-(define-mach
-  (name xc16x)
-  (comment "Infineon XC16X cpu")
-  (cpu xc16xbf)
-)
-
-; Model descriptions.
-
-(define-model
-  (name xc16x) (comment "XC16X") (attrs)
-  (mach xc16x)
-  
-  (pipeline p-mem "" () ((prefetch) (fetch) (decode) (address) (memory) (execute) (writeback)))
-  
-    ; `state' is a list of variables for recording model state
-    (state
-     ; bit mask of h-gr registers, =1 means value being loaded from memory
-     (h-gr UINT)
-    )
-  
-  (unit u-exec "Execution Unit" ()
-  	1 1 ; issue done
-  	() ; state
-  	((dr INT -1) (sr INT -1)) ; inputs
-  	((dr INT -1)) ; outputs
-  	() ; profile action (default)
-	)
-  (unit u-cmp "Compare Unit" ()
-  	1 1 ; issue done
-  	() ; state
-  	((src1 INT -1) (src2 INT -1)) ; inputs
-  	() ; outputs
-  	() ; profile action (default)
-	)
-  (unit u-cti "Jump & Call Unit" ()
-  	1 1 ; issue done
-  	() ; state
-  	((condbit) (sr INT -1)) ; inputs
-  	((pc)) ; outputs
-  	() ; profile action (default)
-	)
-  (unit u-mov "Data Movement Unit" ()
-  	1 1 ; issue done
-  	() ;state
-  	((dr INT -1) (sr INT -1)) ; inputs
-  	((dr INT -1)) ; output
-  	() ; profile action (default)
-  	)
- ) 
- 
-; Instruction fields.
-;
-; Attributes:
-; PCREL-ADDR: pc relative value (for reloc and disassembly purposes)
-; ABS-ADDR: absolute address (for reloc and disassembly purposes)
-; RELOC: there is a relocation associated with this field (experiment)
-
-(define-attr
-  (for ifield operand)
-  (type boolean)
-  (name RELOC)
-  (comment "there is a reloc associated with this field (experiment)")
-)
-
-(dnf f-op1       "op1"                 () 7  4)
-(dnf f-op2       "op2"                 () 3  4)
-(dnf f-condcode  "condcode"            () 7  4)  ;condition code required in other jmps and calls
-(dnf f-icondcode "indrct condcode"     () 15 4)  ;condition code required in other jmpi and calli
-(dnf f-rcond     "relative-cond"       () 7  4)  ;condition code required in JMPR 
-(dnf f-qcond     "qbit"                () 7  4)  ;used in enum of bset/bclear macro
-(dnf f-extccode  "extended condcode"   () 15 5)  ;condition code required in other jmpa and calla
-(dnf f-r0	 "r0"		       () 9  2)  ;required where 2 bit register used(only R0-R3)
-(dnf f-r1        "r1"                  () 15 4)
-(dnf f-r2        "r2"                  () 11 4)
-(dnf f-r3        "r3"                  () 12 4)
-(dnf f-r4        "r4"                  () 11 4)
-(dnf f-uimm2     "uimm2"               () 13 2)  ;used for immediate data,eg in ADD,MOV insns
-(dnf f-uimm3     "uimm3"               () 10 3)  ;used for immediate data,eg in ADD,SUB insns
-(dnf f-uimm4     "uimm4"               () 15 4)  ;used for immediate data,eg in MOV insns
-(dnf f-uimm7     "uimm7"               (PCREL-ADDR RELOC) 15 7)	;used in TRAP
-(dnf f-uimm8     "uimm8"               () 23 8)  ;used in immediate byte data,eg in ADDB,MOVB insns
-(dnf f-uimm16    "uimm16"              () 31 16) ;used for immediate word data
-(dnf f-memory    "memory"              () 31 16) ; used for memory operands 
-(dnf f-memgr8    "memory" 	       () 31 16) ; memory location of gr
-(dnf f-rel8      "rel8"                (PCREL-ADDR RELOC) 15 8)	;used in JMPR,CALLR
-(dnf f-relhi8    "relhi8"              (PCREL-ADDR RELOC) 23 8)	;used in JB,JBC,JNB,JNBS
-(dnf f-reg8      "reg8"                () 15 8)	;required where 8bit gp register used
-(dnf f-regmem8   "regmem8"             () 15 8) ;required where 8bit register used
-(dnf f-regoff8   "regoff8"             () 15 8)	;required for offset calc
-(dnf f-reghi8    "reghi8"              () 23 8)	;required where 8bit register number used
-(dnf f-regb8     "regb8"               () 15 8)	;required for byte registers RL0,RH0, till RL8,RH8
-(dnf f-seg8      "seg8"                () 15 8) ;used as segment number in JMPS,CALLS
-(dnf f-segnum8   "segnum8"             () 23 8) ;used in EXTS,EXTSR        
-(dnf f-mask8     "mask8"               () 23 8) ;used as mask in BFLDH,BFLDL insns
-(dnf f-pagenum   "page num"            () 25 10);used in EXTP,EXTPR
-(dnf f-datahi8   "datahi8"             () 31 8) ;used for filling with const data
-(dnf f-data8     "data8"               () 23 8) ;used for filling with const data
-(dnf f-offset16  "address offset16"    (ABS-ADDR RELOC) 31 16) ;used in JMPS,JMPA,CALLA,CALLS
-(dnf f-op-bit1   "gap of 1 bit"        () 11 1)	;used for filling with const data
-(dnf f-op-bit2   "gap of 2 bits"       () 11 2)	;used for filling with const data
-(dnf f-op-bit4   "gap of 4 bits"       () 11 4) ;used for filling with const data
-(dnf f-op-bit3   "gap of 3 bits"       () 10 3) ;used in CALLA, JMPA
-(dnf f-op-2bit   "gap of 2 bits"       () 10 2) ;used in CALLA
-(dnf f-op-bitone "gap of 1 bit "       () 10 1) ;used in JMPA
-(dnf f-op-onebit "gap of 1 bit "       () 9  1) ;used in JMPA
-(dnf f-op-1bit   "gap of 1 bit "       () 8  1) ;used in JMPA, CALLA
-(dnf f-op-lbit4  "gap of 4 bits"       () 15 4) ;used for filling with const data
-(dnf f-op-lbit2  "gap of 2 bits"       () 15 2) ;used for filling with const data
-(dnf f-op-bit8	 "gap of 8 bits"       () 31 8) ;used for filling with const data
-(dnf f-op-bit16	 "gap of 16 bits"      () 31 16) ;used for filling with const data
-(dnf f-qbit      "qbit"                () 7  4) ;used in bit field of bset/bclear
-(dnf f-qlobit    "qlobit"              () 31 4) ;used for filling with const data
-(dnf f-qhibit    "qhibit"              () 27 4) ;used for filling with const data
-(dnf f-qlobit2   "qlobit2"             () 27 2) ;used for filling with const data
-(dnf f-pof    "upof16"                 () 31 16) ; used for memory operands 
-
-; Enums.
-; insn-op1: bits 0-3
-(define-normal-insn-enum insn-op1 "insn format enums" () OP1_ f-op1
-  ("0" "1" "2" "3" "4" "5" "6" "7"
-   "8" "9" "10" "11" "12" "13" "14" "15")
-)
-
-; insn-op2: bits 4-7
-(define-normal-insn-enum insn-op2 "op2 enums" () OP2_ f-op2
-  ("0" "1" "2" "3" "4" "5" "6" "7"
-   "8" "9" "10" "11" "12" "13" "14" "15")
-)
-
-;/*for bclr/bset*/
-; insn-rcond: bits 0-3
-(define-normal-insn-enum insn-qcond "bit set/clear enums" () QBIT_ f-qcond
-  (("0" 0) ("1" 1) ("2" 2) ("3" 3) ("4" 4) ("5" 5) ("6" 6) ("7" 7) ("8" 8) ("9" 9) ("10" 10) 
-   ("11" 11) ("12" 12) ("13" 13) ("14" 14) ("15" 15))
-)
-;/************/
-; insn-rcond: bits 0-3
-(define-normal-insn-enum insn-rcond "relative jump condition code op2 enums" () COND_ f-rcond
-  (("UC" 0) ("NET" 1) ("Z" 2) ("NE_NZ" 3) ("V" 4)  ("NV" 5) ("N" 6) ("NN" 7)
-   ("C" 8) ("NC" 9) ("SGT" 10) ("SLE" 11) ("SLT" 12) ("SGE" 13) ("UGT" 14) ("ULE" 15)
-   ("EQ" 2) ("NE" 3) ("ULT" 8) ("UGE" 9))
-)
-
-
-
-; Hardware pieces.
-; These entries list the elements of the raw hardware.
-; They're also used to provide tables and other elements of the assembly
-; language.
-
-(dnh h-pc "program counter" (PC) (pc) () () ())
-
-(define-keyword
-  (name gr-names)
-  (enum-prefix H-GR-)
-  (values (r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7)
-	  (r8 8) (r9 9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14) (r15 15))
-
-)
-(define-hardware
-  (name h-gr)
-  (comment "general registers")
-  (attrs PROFILE CACHE-ADDR)
-  (type register HI (16))
-  (indices extern-keyword gr-names)
-)
-
-;; HACK: Various semantics refer to h-cr.
-;; This is here to keep things working.
-(define-hardware
-  (name h-cr)
-  (comment "cr registers")
-  (attrs PROFILE CACHE-ADDR)
-  (type register HI (16))
-  (indices extern-keyword gr-names)
-)
-
-(define-keyword
-  (name ext-names)
-  (enum-prefix H-EXT-)
-  (values (0x1 0) (0x2 1) (0x3 2) (0x4 3)
-          ("1" 0) ("2" 1) ("3" 2) ("4" 3))
-
-)
-
-(define-hardware
-  (name h-ext)
-  (comment "ext values")
-  (attrs PROFILE CACHE-ADDR)
-  (type register HI (8))
-  (indices extern-keyword ext-names)
-)
-
-(define-keyword
-  (name psw-names)
-  (enum-prefix H-PSW-)
-  (values ("IEN" 136) ("r0.11" 240) ("r1.11" 241) ("r2.11" 242) ("r3.11" 243) ("r4.11" 244)
-                      ("r5.11" 245) ("r6.11" 246) ("r7.11" 247) ("r8.11" 248)
-                      ("r9.11" 249) ("r10.11" 250) ("r11.11" 251) ("r12.11" 252)
-                      ("r13.11" 253) ("r14.11" 254) ("r15.11" 255))
-)
-
-(define-hardware
-  (name h-psw)
-  (comment "ext values")
-  (attrs PROFILE CACHE-ADDR)
-  (type register HI (1))
-  (indices extern-keyword psw-names)
-)
-
-(define-keyword
-  (name grb-names)
-  (enum-prefix H-GRB-)
-  (values (rl0 0) (rh0 1) (rl1 2) (rh1 3) (rl2 4) (rh2 5) (rl3 6) (rh3 7) 
-          (rl4 8) (rh4 9) (rl5 10) (rh5 11) (rl6 12) (rh6 13) (rl7 14) (rh7 15))
-)
-
-(define-hardware
-  (name h-grb)
-  (comment "general registers")
-  (attrs PROFILE CACHE-ADDR)
-  (type register QI (16))
-  (indices extern-keyword grb-names)
-)
-
-(define-keyword
-  (name conditioncode-names)
-  (enum-prefix H-CC-)
-  (values (cc_UC 0) (cc_NET 1) (cc_Z 2) (cc_EQ 2) (cc_NZ 3) (cc_NE 3) (cc_V 4) (cc_NV 5) (cc_N 6)  (cc_NN 7) (cc_ULT 8)  (cc_UGE 9) 
-	  (cc_C 8) (cc_NC 9) (cc_SGT 10) (cc_SLE 11) (cc_SLT 12) (cc_SGE 13) (cc_UGT 14) 
-          (cc_ULE 15))
-)
-(define-hardware
-  (name h-cc)
-  (comment "condition codes")
-  (attrs PROFILE CACHE-ADDR)
-  (type register QI (16))
-  (indices extern-keyword conditioncode-names)
-)
-
-(define-keyword
-  (name extconditioncode-names)
-  (enum-prefix H-ECC-)
-  (values(cc_UC 0) (cc_NET 2) (cc_Z 4) (cc_EQ 4) (cc_NZ 6) (cc_NE 6) (cc_V 8) (cc_NV 10) (cc_N 12)  (cc_NN 14) (cc_ULT 16)  (cc_UGE 18) (cc_C 16) (cc_NC 18) (cc_SGT 20) 
-         (cc_SLE 22) (cc_SLT 24) (cc_SGE 26) (cc_UGT 28) (cc_ULE 30) (cc_nusr0 1) 
-         (cc_nusr1 3) (cc_usr0 5) (cc_usr1 7))
-)
-(define-hardware
-  (name h-ecc)
-  (comment "extended condition codes")
-  (attrs PROFILE CACHE-ADDR)
-  (type register QI (4))
-  (indices extern-keyword extconditioncode-names)
-)
-
-(define-keyword
-  (name grb8-names)
-  (enum-prefix H-GRB8-)
-  (values (dpp0 0)  (dpp1 1)  (dpp2 2)  (dpp3 3)
-	  (psw 136)   (cp 8)    (mdl 7)   (mdh  6)
-	  (mdc 135)   (sp 9)    (csp 4)  (vecseg 137)
-          (stkov 10)  (stkun 11) (cpucon1 12) (cpucon2 13)
-	  (zeros 142)  (ones 143) (spseg 134) (tfr 214)
-	  (rl0 240) (rh0 241) (rl1 242) (rh1 243) (rl2 244) (rh2 245) (rl3 246) (rh3 247)
-	  (rl4 248) (rh4 249) (rl5 250) (rh5 251) (rl6 252) (rh6 253) (rl7 254) (rh7 255))
-)
-
-(define-hardware
-  (name h-grb8)
-  (comment "general byte registers")
-  (attrs PROFILE CACHE-ADDR)
-  (type register QI (36))
-  (indices extern-keyword grb8-names)
-)
-
-(define-keyword
-  (name r8-names)
-  (enum-prefix H-R8-)
-  (values (dpp0 0)  (dpp1 1)  (dpp2 2)  (dpp3 3)
-	  (psw 136)   (cp 8)    (mdl 7)   (mdh  6)
-	  (mdc 135)   (sp 9)    (csp 4)  (vecseg 137)
-          (stkov 10)  (stkun 11) (cpucon1 12) (cpucon2 13)
-	  (zeros 142)  (ones 143) (spseg 134) (tfr 214)
-	  (r0 240) (r1 241) (r2 242) (r3 243) (r4 244) (r5 245) (r6 246) (r7 247)
-	  (r8 248) (r9 249) (r10 250) (r11 251) (r12 252) (r13 253) (r14 254) (r15 255))
-)
-
-(define-hardware
-  (name h-r8)
-  (comment "registers")
-  (attrs PROFILE CACHE-ADDR)
-  (type register HI (36))
-  (indices extern-keyword r8-names)
-)
-
-(define-keyword
-  (name regmem8-names)
-  (enum-prefix H-REGMEM8-)
-  (values (dpp0 0)  (dpp1 1)  (dpp2 2)  (dpp3 3)
-	  (psw 136)   (cp 8)    (mdl 7)   (mdh  6)
-	  (mdc 135)   (sp 9)    (csp 4)  (vecseg 137)
-          (stkov 10)  (stkun 11) (cpucon1 12) (cpucon2 13)
-	  (zeros 142)  (ones 143) (spseg 134) (tfr 214)
-	  (r0 240) (r1 241) (r2 242) (r3 243) (r4 244) (r5 245) (r6 246) (r7 247)
-	  (r8 248) (r9 249) (r10 250) (r11 251) (r12 252) (r13 253) (r14 254) (r15 255))
-)
-
-(define-hardware
-  (name h-regmem8)
-  (comment "registers")
-  (attrs )
-  (type register HI (16))
-  (indices extern-keyword regmem8-names)
-)
-
-(define-keyword
-  (name regdiv8-names)
-  (enum-prefix H-REGDIV8-)
-  (values (r0 0) (r1 17) (r2 34) (r3 51) (r4 68) (r5 85) (r6 102) (r7 119)
-	  (r8 136) (r9 153) (r10 170) (r11 187) (r12 204) (r13 221) (r14 238) (r15 255))
-)
-
-(define-hardware
-  (name h-regdiv8)
-  (comment "division insn registers")
-  (attrs PROFILE CACHE-ADDR)
-  (type register HI (16))
-  (indices extern-keyword regdiv8-names)
-)
-
-(define-keyword
-  (name reg0-name)
-  (enum-prefix H-REG0-)
-  (values (0x1 1) (0x2 2) (0x3 3) (0x4 4) (0x5 5) (0x6 6) (0x7 7) (0x8 8) (0x9 9) (0xa 10) (0xb 11) 
-          (0xc 12) (0xd 13) (0xe 14) (0xf 15)
-          ("1" 1) ("2" 2) ("3" 3) ("4" 4) ("5" 5) ("6" 6) ("7" 7) ("8" 8) ("9" 9) ("10" 10) ("11" 11) 
-          ("12" 12) ("13" 13) ("14" 14) ("15" 15))
-)
-
-(define-hardware
-  (name h-r0)
-  (comment "for 4-bit data excuding 0")
-  (attrs PROFILE CACHE-ADDR)
-  (type register HI (30))
-  (indices extern-keyword reg0-name)
-)
-
-(define-keyword
-  (name reg0-name1)
-  (enum-prefix H-REG01-)
-  (values (0x1 1) (0x2 2) (0x3 3) (0x4 4) (0x5 5) (0x6 6) (0x7 7)
-          ("1" 1) ("2" 2) ("3" 3) ("4" 4) ("5" 5) ("6" 6) ("7" 7))
-)
-
-(define-hardware
-  (name h-r01)
-  (comment "for 4-bit data excuding 0")
-  (attrs PROFILE CACHE-ADDR)
-  (type register HI (14))
-  (indices extern-keyword reg0-name1)
-)
-
-(define-keyword
-  (name regbmem8-names)
-  (enum-prefix H-REGBMEM8-)
-  (values (dpp0 0)  (dpp1 1)  (dpp2 2)  (dpp3 3)
-	  (psw 136)   (cp 8)    (mdl 7)   (mdh  6)
-	  (mdc 135)   (sp 9)    (csp 4)  (vecseg 137)
-          (stkov 10)  (stkun 11) (cpucon1 12) (cpucon2 13)
-	  (zeros 142)  (ones 143) (spseg 134) (tfr 214)
-	  (rl0 240) (rh0 241) (rl1 242) (rh1 243) (rl2 244) (rh2 245) (rl3 246) (rh3 247)
-	  (rl4 248) (rh4 249) (rl5 250) (rh5 251) (rl6 252) (rh6 253) (rl7 254) (rh7 255))
-)
-
-(define-hardware
-  (name h-regbmem8)
-  (comment "registers")
-  (attrs PROFILE CACHE-ADDR)
-  (type register HI (36))
-  (indices extern-keyword regbmem8-names)
-)
-
-(define-keyword
-  (name memgr8-names)
-  (enum-prefix H-MEMGR8-)
-  (values (dpp0 65024)  (dpp1 65026)  (dpp2 65028)  (dpp3 65030)
-	  (psw 65296)   (cp 65040)    (mdl 65038)   (mdh  65036)
-	  (mdc 65294)   (sp 65042)    (csp 65032)  (vecseg 65298)
-          (stkov 65044)  (stkun 65046) (cpucon1 65048) (cpucon2 65050)
-	  (zeros 65308)  (ones 65310) (spseg 65292) (tfr 65452) )
-)
-
-(define-hardware
-  (name h-memgr8)
-  (comment "memory location of registers")
-  (attrs )
-  (type register HI (20))
-  (indices extern-keyword memgr8-names)
-)
-
-(dsh h-cond "condition bit" () (register BI))   ;any bit from PSW while comparison
-; This bit is part of the PSW register 
-(dsh h-cbit  "carry bit"		() (register BI))
-
-(dsh h-sgtdis "segmentation enable bit" () (register BI)) ;0 means segmentation enabled
-
-;Instruction operands 
-; -- layer between the assembler and the raw hardware description 
-; -- the main means of manipulating instruction fields in the semantic code 
-
-; XC16X specific operand attributes:
-
-(define-attr
-  (for operand)
-  (type boolean)
-  (name HASH-PREFIX)
-  (comment "immediates have an optional '#' prefix")
-)
-
-(define-attr
-  (for operand)
-  (type boolean)
-  (name DOT-PREFIX)
-  (comment "bit addr have an optional '.' prefix")
-)
-
-(define-attr
-  (for operand)
-  (type boolean)
-  (name POF-PREFIX)
-  (comment "page offset ")
-)
-
-(define-attr
-  (for operand)
-  (type boolean)
-  (name PAG-PREFIX)
-  (comment "page ")
-)
-
-(define-attr
-  (for operand)
-  (type boolean)
-  (name SOF-PREFIX)
-  (comment "segment offset selection")
-)
-
-(define-attr
-  (for operand)
-  (type boolean)
-  (name SEG-PREFIX)
-  (comment "segment")
-)
-
-;; Define an operand that takes a set of handlers.
-;; dowh: define-operand-with-handlers
-(define-pmacro (dowh x-name x-comment x-attrs x-type x-index x-handlers)
-  (define-operand (name x-name) (comment x-comment)
-    (.splice attrs (.unsplice x-attrs))
-    (type x-type) (index x-index)
-    (.splice handlers (.unsplice x-handlers)))
-)
-
-(dnop sr      "source register"              () h-gr    f-r2)
-(dnop dr      "destination register"         () h-gr    f-r1)
-(dnop dri     "destination register"         () h-gr    f-r4)
-(dnop srb     "source register"              () h-grb   f-r2)
-(dnop drb     "destination register"         () h-grb   f-r1)
-(dnop sr2     "2 bit source register"	     () h-gr    f-r0)
-(dnop src1    "source register 1"            () h-gr   f-r1)
-(dnop src2    "source register 2"            () h-gr   f-r2)
-(dnop srdiv   "source register 2"            () h-regdiv8   f-reg8)
-(dnop RegNam  "PSW bits"                     () h-psw f-reg8) 
-(dnop uimm2   "2 bit unsigned number"        (HASH-PREFIX) h-ext f-uimm2) 
-(dnop uimm3   "3 bit unsigned number"        (HASH-PREFIX) h-r01 f-uimm3)
-(dnop uimm4   "4 bit unsigned number"        (HASH-PREFIX) h-uint f-uimm4)
-(dnop uimm7   "7 bit trap number"            (HASH-PREFIX) h-uint f-uimm7)
-(dnop uimm8   "8 bit unsigned immediate"     (HASH-PREFIX) h-uint f-uimm8)
-(dnop uimm16  "16 bit unsigned immediate"    (HASH-PREFIX) h-uint f-uimm16)
-(dowh upof16  "16 bit unsigned immediate"    (POF-PREFIX) h-addr f-memory ((print "with_pof_prefix")))
-(dnop reg8    "8 bit word register number"   () h-r8 f-reg8)
-(dnop regmem8 "8 bit word register number"   () h-regmem8 f-regmem8)
-(dnop regbmem8 "8 bit byte register number"  () h-regbmem8 f-regmem8)
-(dnop regoff8 "8 bit word register number"   () h-r8 f-regoff8)
-(dnop reghi8  "8 bit word register number"   () h-r8 f-reghi8)
-(dnop regb8   "8 bit byte register number"   () h-grb8 f-regb8)
-(dnop genreg  "8 bit word register number"   () h-r8 f-regb8)
-(dnop seg     "8 bit segment number"         () h-uint f-seg8)
-(dnop seghi8  "8 bit hi segment number"      () h-uint f-segnum8)
-(dnop caddr   "16 bit address offset"        () h-addr f-offset16)
-(dnop rel     "8 bit signed relative offset" () h-sint f-rel8)
-(dnop relhi   "hi 8 bit signed relative offset" () h-sint f-relhi8)	
-(dnop condbit "condition bit"                (SEM-ONLY) h-cond f-nil)
-(dnop bit1    "gap of 1 bit"    	     () h-uint f-op-bit1)
-(dnop bit2    "gap of 2 bits"	             () h-uint f-op-bit2)
-(dnop bit4    "gap of 4 bits"                () h-uint f-op-bit4)
-(dnop lbit4   "gap of 4 bits"                () h-uint f-op-lbit4)
-(dnop lbit2   "gap of 2 bits"                () h-uint f-op-lbit2)
-(dnop bit8    "gap of 8 bits"	             () h-uint f-op-bit8)
-(dnop u4      "gap of 4 bits"	             () h-r0   f-uimm4)
-(dnop bitone  "field of 1 bit"	             () h-uint f-op-onebit)
-(dnop bit01   "field of 1 bit"	             () h-uint f-op-1bit)
-(dnop cond    "condition code" 	             () h-cc   f-condcode)
-(dnop icond   "indirect condition code"      () h-cc   f-icondcode)
-(dnop extcond "extended condition code"      () h-ecc  f-extccode)
-(dnop memory  "16 bit memory" 		     () h-addr f-memory)
-(dnop memgr8  "16 bit memory"		     () h-memgr8 f-memgr8)
-(dnop cbit    "carry bit"                    (SEM-ONLY) h-cbit  f-nil)
-(dowh qbit    "bit addr"               	     (DOT-PREFIX) h-uint f-qbit ((print "with_dot_prefix")))
-(dowh qlobit  "bit addr"                     (DOT-PREFIX) h-uint f-qlobit ((print "with_dot_prefix")))
-(dowh qhibit  "bit addr"                     (DOT-PREFIX) h-uint f-qhibit ((print "with_dot_prefix")))
-(dnop mask8   "8 bit mask"     		     (HASH-PREFIX) h-uint f-mask8)
-(dnop masklo8 "8 bit mask"     		     (HASH-PREFIX) h-uint f-datahi8)
-(dnop pagenum "10 bit page number"     	     (HASH-PREFIX) h-uint f-pagenum)
-(dnop data8   "8 bit data"     		     (HASH-PREFIX) h-uint f-data8)
-(dnop datahi8 "8 bit data"     	             (HASH-PREFIX) h-uint f-datahi8)
-(dnop sgtdisbit "segmentation enable bit"    (SEM-ONLY) h-sgtdis f-nil)
-(dowh upag16  "16 bit unsigned immediate"    (PAG-PREFIX) h-uint f-uimm16 ((print "with_pag_prefix")))
-(dnop useg8   "8 bit segment "    	     (SEG-PREFIX) h-uint f-seg8)
-(dnop useg16  "16 bit address offset"        (SEG-PREFIX) h-uint f-offset16)
-(dnop usof16  "16 bit address offset"        (SOF-PREFIX) h-uint f-offset16)
-
-; define hash operator
-(define-operand (name hash) (comment "# prefix") (attrs)
-  (type h-sint)  
-  (index f-nil)
-  (handlers (parse "hash") (print "hash"))
-)
-
-; define dot operator
-(define-operand (name dot) (comment ". prefix") (attrs)
-  (type h-sint)  
-  (index f-nil)
-  (handlers (parse "dot") (print "dot"))
-)
-
-; define pof operator
-(define-operand (name pof) (comment "pof: prefix") (attrs)
-  (type h-sint)  
-  (index f-nil)
-  (handlers (parse "pof") (print "pof"))
-)
-
-; define pag operator
-(define-operand (name pag) (comment "pag: prefix") (attrs)
-  (type h-sint)
-  (index f-nil)
-  (handlers (parse "pag") (print "pag"))
-)
-
-; define sof operator
-(define-operand (name sof) (comment "sof: prefix") (attrs)
-  (type h-sint)  
-  (index f-nil)
-  (handlers (parse "sof") (print "sof"))
-)
-
-; define seg operator
-(define-operand (name segm) (comment "seg: prefix") (attrs)
-  (type h-sint)
-  (index f-nil)
-  (handlers (parse "seg") (print "seg"))
-)
-
-; IDOC attribute for instruction documentation.
-(define-attr
-  (for insn)
-  (type enum)
-  (name IDOC)
-  (comment "insn kind for documentation")
-  (attrs META)
-  (values
-   (MOVE - () "Data Movement")
-   (ALU  - () "Arithmatic & logical")
-   (CMP  - () "Compare")
-   (JMP  - () "Jump & Call")
-   (MISC - () "Miscellaneous")
-   (SYSC - () "System control")
-  )
-)
-
-; Include the instruction set descriptions from their respective
-; source files.
-
-;Arithmatic insns
-;******************************************************************
-
-;add/sub register and immediate
-(define-pmacro (arithmetic16 name insn insn1 opc1 opc2 op1 op2 mode dir)
-  (dni name 
-       (.str name "arithmetic" )
-       ((PIPE OS) (IDOC ALU))
-       (.str insn " $"op1 ",$"dir"$"op2)
-       (+ opc1 opc2 op1 op2)
-       (set mode op1 (insn1 mode op1 (mem HI op2)))
-       ()
-  )
-)
-(arithmetic16 addrpof add add OP1_0 OP2_2 reg8 upof16 HI "pof")
-(arithmetic16 subrpof sub sub OP1_2 OP2_2 reg8 upof16 HI "pof")
-(arithmetic16 addbrpof addb add OP1_0 OP2_3 regb8 upof16 QI "pof")
-(arithmetic16 subbrpof subb sub OP1_2 OP2_3 regb8 upof16 QI "pof")
-(arithmetic16 addrpag add add OP1_0 OP2_2 reg8 upag16 HI "pag")
-(arithmetic16 subrpag sub sub OP1_2 OP2_2 reg8 upag16 HI "pag")
-(arithmetic16 addbrpag addb add OP1_0 OP2_3 regb8 upag16 QI "pag")
-(arithmetic16 subbrpag subb sub OP1_2 OP2_3 regb8 upag16 QI "pag")
-
-;add/sub register and immediate
-(define-pmacro (arithmetic17 name insn insn1 opc1 opc2 op1 op2 mode dir)
-  (dni name 
-       (.str name "arithmetic" )
-       ((PIPE OS) (IDOC ALU))
-       (.str insn " $"op1 ",$"dir"$"op2)
-       (+ opc1 opc2 op1 op2)
-       (set mode op1 (insn1 mode op1 (mem HI op2) cbit))
-       ()
-  )
-)
-(arithmetic17 addcrpof addc addc OP1_1 OP2_2 reg8 upof16 HI "pof")
-(arithmetic17 subcrpof subc subc OP1_3 OP2_2 reg8 upof16 HI "pof")
-(arithmetic17 addcbrpof addcb addc OP1_1 OP2_3 regb8 upof16 QI "pof")
-(arithmetic17 subcbrpof subcb subc OP1_3 OP2_3 regb8 upof16 QI "pof")
-(arithmetic17 addcrpag addc addc OP1_1 OP2_2 reg8 upag16 HI "pag")
-(arithmetic17 subcrpag subc subc OP1_3 OP2_2 reg8 upag16 HI "pag")
-(arithmetic17 addcbrpag addcb addc OP1_1 OP2_3 regb8 upag16 QI "pag")
-(arithmetic17 subcbrpag subcb subc OP1_3 OP2_3 regb8 upag16 QI "pag")
-
-;add/sub register and immediate
-(define-pmacro (arithmetic18 name insn insn1 opc1 opc2 op1 op2 mode dir)
-  (dni name 
-       (.str name "arithmetic" )
-       ((PIPE OS) (IDOC ALU))
-       (.str insn " $"dir"$"op1 ",$"op2)
-       (+ opc1 opc2 op2 op1)
-       (set (mem HI op1) (insn1 (mem HI op1) op2 ))
-       ()
-  )
-)
-(arithmetic18 addrpofr add add OP1_0 OP2_4 upof16 reg8 HI "pof")
-(arithmetic18 subrpofr sub sub OP1_2 OP2_4 upof16 reg8 HI "pof")
-(arithmetic18 addbrpofr addb add OP1_0 OP2_5 upof16 regb8 QI "pof")
-(arithmetic18 subbrpofr subb sub OP1_2 OP2_5 upof16 regb8 QI "pof")
-
-;add/sub register and immediate
-(define-pmacro (arithmetic19 name insn insn1 opc1 opc2 op1 op2 mode dir)
-  (dni name 
-       (.str name "arithmetic" )
-       ((PIPE OS) (IDOC ALU))
-       (.str insn " $"dir"$"op1 ",$"op2)
-       (+ opc1 opc2 op2 op1)
-       (set (mem HI op1) (insn1 mode (mem HI op1) op2 cbit))
-       ()
-  )
-)
-(arithmetic19 addcrpofr addc addc OP1_1 OP2_4 upof16 reg8 HI "pof")
-(arithmetic19 subcrpofr subc subc OP1_3 OP2_4 upof16 reg8 HI "pof")
-(arithmetic19 addcbrpofr addcb addc OP1_1 OP2_5 upof16 regb8 QI "pof")
-(arithmetic19 subcbrpofr subcb subc OP1_3 OP2_5 upof16 regb8 QI "pof")
-
-;add/sub register and immediate
-(define-pmacro (arithmetic20 name insn insn1 opc1 opc2 op1 op2 mode dir)
-  (dni name 
-       (.str name "arithmetic" )
-       ((PIPE OS) (IDOC ALU))
-       (.str insn " $"op1 ",$hash$"dir"$"op2)
-       (+ opc1 opc2 op1 op2)
-       (set mode op1 (insn1 mode op1 op2))
-       ()
-  )
-)
-(arithmetic20 addrhpof add add OP1_0 OP2_6 reg8 uimm16 HI "pof")
-(arithmetic20 subrhpof sub sub OP1_2 OP2_6 reg8 uimm16 HI "pof")
-(arithmetic20 addbrhpof add add OP1_0 OP2_6 reg8 uimm16 HI "pag")
-(arithmetic20 subbrhpof sub sub OP1_2 OP2_6 reg8 uimm16 HI "pag")
-
-;add/sub register and immediate
-(define-pmacro (arithmetic21 name insn insn1 opc1 opc2 op1 op2 mode dir)
-  (dni name 
-       (.str name "arithmetic" )
-       ((PIPE OS) (IDOC ALU))
-       (.str insn " $"op1 ",$hash$"dir"$"op2)
-       (+ opc1 opc2 op1 (f-op-bit1 0) op2)
-       (set mode op1 (insn1 mode op1 op2))
-       ()
-  )
-)
-(arithmetic21 addrhpof3 add add OP1_0 OP2_8 dr uimm3 HI "pof")
-(arithmetic21 subrhpof3 sub sub OP1_2 OP2_8 dr uimm3 HI "pof")
-(arithmetic21 addbrhpag3 addb add OP1_0 OP2_9 drb uimm3 QI "pag")
-(arithmetic21 subbrhpag3 subb sub OP1_2 OP2_9 drb uimm3 QI "pag")
-(arithmetic21 addrhpag3 add add OP1_0 OP2_8 dr uimm3 HI "pag")
-(arithmetic21 subrhpag3 sub sub OP1_2 OP2_8 dr uimm3 HI "pag")
-(arithmetic21 addbrhpof3 addb add OP1_0 OP2_9 drb uimm3 QI "pof")
-(arithmetic21 subbrhpof3 subb sub OP1_2 OP2_9 drb uimm3 QI "pof")
-
-;add/sub register and immediate
-(define-pmacro (arithmetic22 name insn insn1 opc1 opc2 op1 op2 mode dir)
-  (dni name 
-       (.str name "arithmetic" )
-       ((PIPE OS) (IDOC ALU))
-       (.str insn " $"op1 ",$hash$"dir"$"op2)
-       (+ opc1 opc2 op1 op2 (f-op-bit8 0))
-       (set mode op1 (insn1 mode op1 op2))
-       ()
-  )
-)
-(arithmetic22 addrbhpof addb add OP1_0 OP2_7 regb8 uimm8 QI "pof")
-(arithmetic22 subrbhpof subb sub OP1_2 OP2_7 regb8 uimm8 QI "pof")
-(arithmetic22 addbrhpag addb add OP1_0 OP2_7 regb8 uimm8 QI "pag")
-(arithmetic22 subbrhpag subb sub OP1_2 OP2_7 regb8 uimm8 QI "pag")
-
-;add/sub register and immediate
-(define-pmacro (arithmetic23 name insn insn1 opc1 opc2 op1 op2 mode dir)
-  (dni name 
-       (.str name "arithmetic" )
-       ((PIPE OS) (IDOC ALU))
-       (.str insn " $"op1 ",$hash$"dir"$"op2)
-       (+ opc1 opc2 op1 op2)
-       (set mode op1 (insn1 mode op1 op2 cbit))
-       ()
-  )
-)
-(arithmetic23 addcrhpof addc addc OP1_1 OP2_6 reg8 uimm16 HI "pof")
-(arithmetic23 subcrhpof subc subc OP1_3 OP2_6 reg8 uimm16 HI "pof")
-(arithmetic23 addcbrhpof addc addc OP1_1 OP2_6 reg8 uimm16 HI "pag")
-(arithmetic23 subcbrhpof subc subc OP1_3 OP2_6 reg8 uimm16 HI "pag")
-
-;add/sub register and immediate
-(define-pmacro (arithmetic24 name insn insn1 opc1 opc2 op1 op2 mode dir)
-  (dni name 
-       (.str name "arithmetic" )
-       ((PIPE OS) (IDOC ALU))
-       (.str insn " $"op1 ",$hash$"dir"$"op2)
-       (+ opc1 opc2 op1 (f-op-bit1 0) op2)
-       (set mode op1 (insn1 mode op1 op2 cbit))
-       ()
-  )
-)
-(arithmetic24 addcrhpof3 addc addc OP1_1 OP2_8 dr uimm3 HI "pof")
-(arithmetic24 subcrhpof3 subc subc OP1_3 OP2_8 dr uimm3 HI "pof")
-(arithmetic24 addcbrhpag3 addcb addc OP1_1 OP2_9 drb uimm3 QI "pag")
-(arithmetic24 subcbrhpag3 subcb subc OP1_3 OP2_9 drb uimm3 QI "pag")
-(arithmetic24 addcrhpag3 addc addc OP1_1 OP2_8 dr uimm3 HI "pag")
-(arithmetic24 subcrhpag3 subc subc OP1_3 OP2_8 dr uimm3 HI "pag")
-(arithmetic24 addcbrhpof3 addcb addc OP1_1 OP2_9 drb uimm3 QI "pof")
-(arithmetic24 subcbrhpof3 subcb subc OP1_3 OP2_9 drb uimm3 QI "pof")
-
-;add/sub register and immediate
-(define-pmacro (arithmetic25 name insn insn1 opc1 opc2 op1 op2 mode dir)
-  (dni name 
-       (.str name "arithmetic" )
-       ((PIPE OS) (IDOC ALU))
-       (.str insn " $"op1 ",$hash$"dir"$"op2)
-       (+ opc1 opc2 op1 op2 (f-op-bit8 0))
-       (set mode op1 (insn1 mode op1 op2 cbit))
-       ()
-  )
-)
-(arithmetic25 addcrbhpof addcb addc OP1_1 OP2_7 regb8 uimm8 QI "pof")
-(arithmetic25 subcrbhpof subcb subc OP1_3 OP2_7 regb8 uimm8 QI "pof")
-(arithmetic25 addcbrhpag addcb addc OP1_1 OP2_7 regb8 uimm8 QI "pag")
-(arithmetic25 subcbrhpag subcb subc OP1_3 OP2_7 regb8 uimm8 QI "pag")
-
-;add/sub register and immediate
-(define-pmacro (arithmetic10 name insn insn1 opc1 opc2 op1 op2 mode)
-  (dni name 
-       (.str name "arithmetic" )
-       ((PIPE OS) (IDOC ALU))
-       (.str insn " $"op1 ",$hash$"op2)
-       (+ opc1 opc2 op1 (f-op-bit1 0) op2)
-       (set mode op1 (insn1 mode op1 op2))
-       ()
-  )
-)
-(arithmetic10 addri add add OP1_0 OP2_8 dr uimm3 HI)
-(arithmetic10 subri sub sub OP1_2 OP2_8 dr uimm3 HI)
-(arithmetic10 addbri addb add OP1_0 OP2_9 drb uimm3 QI)
-(arithmetic10 subbri subb sub OP1_2 OP2_9 drb uimm3 QI)
-
-;add/sub register and immediate
-(define-pmacro (arithmetic11 name insn insn1 opc1 opc2 op1 op2 mode)
-  (dni name 
-       (.str name "arithmetic" )
-       ((PIPE OS) (IDOC ALU))
-       (.str insn " $"op1 ",$hash$"op2)
-       (+ opc1 opc2 op1 op2)
-       (set mode op1 (insn1 mode op1 op2))
-       ()
-  )
-)
-(arithmetic11 addrim add add OP1_0 OP2_6 reg8 uimm16 HI)
-(arithmetic11 subrim sub sub OP1_2 OP2_6 reg8 uimm16 HI)
-
-;add/sub register and immediate
-(define-pmacro (arithmetic12 name insn insn1 opc1 opc2 op1 op2 mode)
-  (dni name 
-       (.str name "arithmetic" )
-       ((PIPE OS) (IDOC ALU))
-       (.str insn " $"op1 ",$hash$"op2)
-       (+ opc1 opc2 op1 op2 (f-op-bit8 0))
-       (set mode op1 (insn1 mode op1 op2))
-       ()
-  )
-)
-(arithmetic12 addbrim addb add OP1_0 OP2_7 regb8 uimm8 QI)
-(arithmetic12 subbrim subb sub OP1_2 OP2_7 regb8 uimm8 QI)
-
-;add/sub register and immediate with carry
-(define-pmacro (arithmetic13 name insn insn1 opc1 opc2 op1 op2 mode)
-  (dni name 
-       (.str name "arithmetic" )
-       ((PIPE OS) (IDOC ALU))
-       (.str insn " $"op1 ",$hash$"op2)
-       (+ opc1 opc2 op1 (f-op-bit1 0) op2)
-       (set mode op1 (insn1 mode op1 op2 cbit))
-       ()
-  )
-)
-(arithmetic13 addcri addc addc OP1_1 OP2_8 dr uimm3 HI)
-(arithmetic13 subcri subc subc OP1_3 OP2_8 dr uimm3 HI)
-(arithmetic13 addcbri addcb addc OP1_1 OP2_9 drb uimm3 QI)
-(arithmetic13 subcbri subcb subc OP1_3 OP2_9 drb uimm3 QI)
-
-;add/sub register and immediate with carry
-(define-pmacro (arithmetic14 name insn insn1 opc1 opc2 op1 op2 mode)
-  (dni name 
-       (.str name "arithmetic" )
-       ((PIPE OS) (IDOC ALU))
-       (.str insn " $"op1 ",$hash$"op2)
-       (+ opc1 opc2 op1 op2)
-       (set mode op1 (insn1 mode op1 op2 cbit))
-       ()
-  )
-)
-(arithmetic14 addcrim addc addc OP1_1 OP2_6 reg8 uimm16 HI)
-(arithmetic14 subcrim subc subc OP1_3 OP2_6 reg8 uimm16 HI)
-
-;add/sub register and immediate with carry
-(define-pmacro (arithmetic15 name insn insn1 opc1 opc2 op1 op2 mode)
-  (dni name 
-       (.str name "arithmetic" )
-       ((PIPE OS) (IDOC ALU))
-       (.str insn " $"op1 ",$hash$"op2)
-       (+ opc1 opc2 op1 op2 (f-op-bit8 0))
-       (set mode op1 (insn1 mode op1 op2 cbit))
-       ()
-  )
-)
-(arithmetic15 addcbrim addcb addc OP1_1 OP2_7 regb8 uimm8 QI)
-(arithmetic15 subcbrim subcb subc OP1_3 OP2_7 regb8 uimm8 QI)
-
-
-;add/sub registers
-(define-pmacro (arithmetic name insn insn1 opc1 opc2 op1 op2 mode)
-  (dni name 
-       (.str name "arithmetic" )
-       ((PIPE OS) (IDOC ALU))
-       (.str insn " $"op1 ",$"op2)
-       (+ opc1 opc2 op1 op2)
-       (set mode op1 (insn1 mode op1 op2))
-       ()
-  )
-)
-(arithmetic addr add add OP1_0 OP2_0 dr sr HI)
-(arithmetic subr sub sub OP1_2 OP2_0 dr sr HI)
-(arithmetic addbr addb add OP1_0 OP2_1 drb srb QI)
-(arithmetic subbr subb sub OP1_2 OP2_1 drb srb QI)
-
-;add/sub register and indirect memory
-(define-pmacro (arithmetic1 name insn insn1 opc1 opc2 op1 op2 mode)
-  (dni name
-       (.str name "arithmetic" )
-       ((PIPE OS) (IDOC ALU))
-       (.str insn " $"op1 ",[$"op2"]")
-       (+ opc1 opc2 op1 (f-op-bit2 2) op2)
-       (set mode op1 (insn1 mode op1 (mem HI op2)))
-       ()
-  )
-)
-(arithmetic1 add2 add add OP1_0 OP2_8 dr sr2 HI)
-(arithmetic1 sub2 sub sub OP1_2 OP2_8 dr sr2 HI)
-(arithmetic1 addb2 addb add OP1_0 OP2_9 drb sr2 QI)
-(arithmetic1 subb2 subb sub OP1_2 OP2_9 drb sr2 QI)
-
-;add/sub register and indirect memory post increment
-(define-pmacro (arithmetic2 name insn insn1 opc1 opc2 op1 op2 mode)
-  (dni name
-       (.str name "arithmetic" )
-       ((PIPE OS) (IDOC ALU))
-       (.str insn " $"op1 ",[$"op2"+]")
-       (+ opc1 opc2 op1 (f-op-bit2 3) op2)
-       (sequence ()
-	   (set mode op1 (insn1 mode op1 (mem HI op2)))
-	   (set HI op2 (add HI op2 (const 2)))
-       )
-       ()
-  )
-)
-(arithmetic2 add2i add add OP1_0 OP2_8 dr sr2 HI)
-(arithmetic2 sub2i sub sub OP1_2 OP2_8 dr sr2 HI)
-(arithmetic2 addb2i addb add OP1_0 OP2_9 drb sr2 QI)
-(arithmetic2 subb2i subb sub OP1_2 OP2_9 drb sr2 QI)
-
-;add/sub registers with carry
-(define-pmacro (arithmetic3 name insn insn1 opc1 opc2 op1 op2 mode)
-  (dni name 
-       (.str name "arithmetic" )
-       ((PIPE OS) (IDOC ALU))
-       (.str insn " $"op1 ",$"op2)
-       (+ opc1 opc2 op1 op2)
-       (set mode op1 (insn1 mode op1 op2 cbit))
-       ()
-  )
-)
-(arithmetic3 addcr addc addc OP1_1 OP2_0 dr sr HI)
-(arithmetic3 subcr subc subc OP1_3 OP2_0 dr sr HI)
-(arithmetic3 addbcr addcb addc OP1_1 OP2_1 drb srb QI) 
-(arithmetic3 subbcr subcb subc OP1_3 OP2_1 drb srb QI)
-
-
-;add/sub register and indirect memory
-(define-pmacro (arithmetic4 name insn insn1 opc1 opc2 op1 op2 mode)
-  (dni name
-       (.str name "arithmetic" )
-       ((PIPE OS) (IDOC ALU))
-       (.str insn " $"op1 ",[$"op2"]")
-       (+ opc1 opc2 op1 (f-op-bit2 2) op2)
-       (set mode op1 (insn1 mode op1 (mem HI op2) cbit))
-       ()
-  )
-)
-(arithmetic4 addcr2 addc addc OP1_1 OP2_8 dr sr2 HI)
-(arithmetic4 subcr2 subc subc OP1_3 OP2_8 dr sr2 HI)
-(arithmetic4 addbcr2 addcb addc OP1_1 OP2_9 drb sr2 QI)
-(arithmetic4 subbcr2 subcb subc OP1_3 OP2_9 drb sr2 QI)
-
-;add/sub register and indirect memory post increment
-(define-pmacro (arithmetic5 name insn insn1 opc1 opc2 op1 op2 mode)
-  (dni name
-       (.str name "arithmetic" )
-       ((PIPE OS) (IDOC ALU))
-       (.str insn " $"op1 ",[$"op2"+]")
-       (+ opc1 opc2 op1 (f-op-bit2 3) op2)
-       (sequence ()
-           (set mode op1 (insn1 mode op1 (mem HI op2) cbit))
-           (set HI op2 (add HI op2 (const 2)))
-       )
-       ()
-  )
-)
-(arithmetic5 addcr2i addc addc OP1_1 OP2_8 dr sr2 HI)
-(arithmetic5 subcr2i subc subc OP1_3 OP2_8 dr sr2 HI)
-(arithmetic5 addbcr2i addcb addc OP1_1 OP2_9 drb sr2 QI)
-(arithmetic5 subbcr2i subcb subc OP1_3 OP2_9 drb sr2 QI)
-
-;add/sub register and direct memory
-(define-pmacro (arithmetic6 name insn insn1 opc1 opc2 op1 op2 mode)
-  (dni name 
-       (.str name "arithmetic" )
-       ((PIPE OS) (IDOC ALU))
-       (.str insn " $"op1 ",$"op2)
-       (+ opc1 opc2 op1 op2)
-       (set mode op1 (insn1 mode op1 op2))
-       ()
-  )
-)
-
-;add/sub register and direct memory
-(define-pmacro (arithmetic7 name insn insn1 opc1 opc2 op1 op2 mode)
-  (dni name 
-       (.str name "arithmetic" )
-       ((PIPE OS) (IDOC ALU))
-       (.str insn " $"op1 ",$"op2)
-       (+ opc1 opc2 op2 op1)
-       (set (mem HI op1) (insn1 (mem HI op1) op2))
-       ()
-  )
-)
-(arithmetic6 addrm2 add add OP1_0 OP2_2 regmem8 memgr8 HI)
-(arithmetic7 addrm3 add add OP1_0 OP2_4 memgr8 regmem8 HI)
-(arithmetic6 addrm add add OP1_0 OP2_2 reg8 memory HI)
-(arithmetic7 addrm1 add add OP1_0 OP2_4 memory reg8 HI)
-(arithmetic6 subrm3 sub sub OP1_2 OP2_2 regmem8 memgr8 HI)
-(arithmetic7 subrm2 sub sub OP1_2 OP2_4 memgr8 regmem8 HI)
-(arithmetic6 subrm1 sub sub OP1_2 OP2_2 reg8 memory HI)
-(arithmetic7 subrm sub sub OP1_2 OP2_4 memory reg8 HI)
-(arithmetic6 addbrm2 addb add OP1_0 OP2_3 regbmem8 memgr8 QI)
-(arithmetic7 addbrm3 addb add OP1_0 OP2_5 memgr8 regbmem8 QI)
-(arithmetic6 addbrm addb add OP1_0 OP2_3 regb8 memory QI)
-(arithmetic7 addbrm1 addb add OP1_0 OP2_5 memory regb8 QI)
-(arithmetic6 subbrm3 subb sub OP1_2 OP2_3 regbmem8 memgr8 QI)
-(arithmetic7 subbrm2 subb sub OP1_2 OP2_5 memgr8 regbmem8 QI)
-(arithmetic6 subbrm1 subb sub OP1_2 OP2_3 regb8 memory QI)
-(arithmetic7 subbrm subb sub OP1_2 OP2_5 memory regb8 QI)
-
-;add/sub registers with carry
-(define-pmacro (arithmetic8 name insn insn1 opc1 opc2 op1 op2 mode)
-  (dni name 
-       (.str name "arithmetic" )
-       ((PIPE OS) (IDOC ALU))
-       (.str insn " $"op1 ",$"op2)
-       (+ opc1 opc2 op1 op2)
-       (set mode op1 (insn1 mode op1 op2 cbit))
-       ()
-  )
-)
-
-;add/sub registers with carry
-(define-pmacro (arithmetic9 name insn insn1 opc1 opc2 op1 op2 mode)
-  (dni name 
-       (.str name "arithmetic" )
-       ((PIPE OS) (IDOC ALU))
-       (.str insn " $"op1 ",$"op2)
-       (+ opc1 opc2 op2 op1)
-       (set (mem HI op1) (insn1 (mem HI op1) op2 cbit))
-       ()
-  )
-)
-(arithmetic8 addcrm2 addc addc OP1_1 OP2_2 regmem8 memgr8 HI)
-(arithmetic9 addcrm3 addc addc OP1_1 OP2_4  memgr8 regmem8 HI)
-(arithmetic8 addcrm addc addc OP1_1 OP2_2 reg8 memory HI)
-(arithmetic9 addcrm1 addc addc OP1_1 OP2_4  memory reg8 HI)
-(arithmetic8 subcrm3 subc subc OP1_3 OP2_2  regmem8 memgr8 HI)
-(arithmetic9 subcrm2 subc subc OP1_3 OP2_4 memgr8 regmem8 HI)
-(arithmetic8 subcrm1 subc subc OP1_3 OP2_2  reg8 memory HI)
-(arithmetic9 subcrm subc subc OP1_3 OP2_4 memory reg8 HI)
-(arithmetic8 addcbrm2 addcb addc OP1_1 OP2_3 regbmem8 memgr8 QI)
-(arithmetic9 addcbrm3 addcb addc OP1_1 OP2_5  memgr8 regbmem8 QI)
-(arithmetic8 addcbrm addcb addc OP1_1 OP2_3 regb8 memory QI)
-(arithmetic9 addcbrm1 addcb addc OP1_1 OP2_5  memory regb8 QI)
-(arithmetic8 subcbrm3 subcb subc OP1_3 OP2_3  regbmem8 memgr8 QI)
-(arithmetic9 subcbrm2 subcb subc OP1_3 OP2_5 memgr8 regbmem8 QI)
-(arithmetic8 subcbrm1 subcb subc OP1_3 OP2_3  regb8 memory QI)
-(arithmetic9 subcbrm subcb subc OP1_3 OP2_5 memory regb8 QI)
-
-; MUL Rwn,Rwm
-(dni muls "signed multiplication"
-     ((PIPE OS) (IDOC ALU))
-     "mul $src1,$src2"
-     (+ OP1_0 OP2_11 src1 src2)
-     (nop) ;; FIXME: (reg SI h-md 0)
-     ()
-)
-; MULU Rwn,Rwm
-(dni mulu "unsigned multiplication"
-     ((PIPE OS) (IDOC ALU))
-     "mulu $src1,$src2"
-     (+ OP1_1 OP2_11 src1 src2)
-     (nop) ;; FIXME: (reg SI h-md 0)
-     ()
-)
-; DIV Rwn
-(dni div "16-by-16 signed division"
-     ((PIPE OS) (IDOC ALU))
-     "div $srdiv"
-     (+ OP1_4 OP2_11 srdiv )
-     (sequence ()
-         (set HI (reg HI h-cr 6) (div HI (reg HI h-cr 6) srdiv))
-         (set HI (reg HI h-cr 7) (mod HI (reg HI h-cr 6) srdiv))
-     )
-     ()
-) 
-; DIVL Rwn
-(dni divl "32-by16 signed division"
-     ((PIPE OS) (IDOC ALU))
-     "divl $srdiv"
-     (+ OP1_6 OP2_11 srdiv )
-     (sequence ()
-         (set HI (reg HI h-cr 6) 0) ;; FIXME: (div SI (reg SI h-md 0) srdiv))
-	 (set HI (reg HI h-cr 7) 0) ;; FIXME: (mod SI (reg SI h-md 0) srdiv))
-     )
-     ()
-)
-; DIVLU Rwn 
-(dni divlu "32-by16 unsigned division"
-     ((PIPE OS) (IDOC ALU))
-     "divlu $srdiv"
-     (+ OP1_7 OP2_11 srdiv )
-     (sequence ()
-         (set HI (reg HI h-cr 6) 0) ;; FIXME: (udiv SI (reg SI h-md 0) srdiv))
-	 (set HI (reg HI h-cr 7) 0) ;; FIXME: (umod SI (reg SI h-md 0) srdiv))
-     )
-     ()
-)
-; DIVU Rwn
-(dni divu "16-by-16 unsigned division"
-     ((PIPE OS) (IDOC ALU))
-     "divu $srdiv"
-     (+ OP1_5 OP2_11 srdiv )
-     (sequence ()
-         (set HI (reg HI h-cr 6) (udiv HI (reg HI h-cr 6) srdiv))
-         (set HI (reg HI h-cr 7) (umod HI (reg HI h-cr 6) srdiv))
-     )
-     ()
-)
-
-;Integer one's complement
-; CPL Rwn
-(dni cpl "Integer Ones complement"
-     ((PIPE OS) (IDOC MISC))
-     "cpl $dr"
-     (+ OP1_9 OP2_1 dr (f-op-bit4 0))
-     (set dr (inv HI dr))
-     ()
-)
-
-;Bytes one's complement
-; CPLB Rbn
-(dni cplb "Byte Ones complement"
-     ((PIPE OS) (IDOC MISC))
-     "cplb $drb"
-     (+ OP1_11 OP2_1 drb (f-op-bit4 0))
-     (set drb (inv QI drb))
-     ()
-)
-;Integer two's complement
-; NEG Rwn
-(dni neg "Integer two's complement"
-     ((PIPE OS) (IDOC MISC))
-     "neg $dr"
-     (+ OP1_8 OP2_1 dr (f-op-bit4 0))
-     (set dr (neg HI dr))
-     ()
-)
-;Bytes two's complement
-; NEGB Rbn
-(dni negb "byte twos complement"
-     ((PIPE OS) (IDOC MISC))
-     "negb $drb"
-     (+ OP1_10 OP2_1 drb (f-op-bit4 0))
-     (set drb (neg QI drb))
-     ()
-)
-
-;****************************************************************
-;logical insn
-;****************************************************************
-;and/or/xor registers
-(define-pmacro (logical name insn insn1 opc1 opc2 op1 op2 mode)
-  (dni name 
-       (.str name "logical" )
-       ((PIPE OS) (IDOC ALU))
-       (.str insn " $"op1 ",$"op2)
-       (+ opc1 opc2 op1 op2)
-       (set mode op1 (insn1 mode op1 op2))
-       ()
-  )
-)
-
-(logical andr and and OP1_6 OP2_0 dr sr HI)
-(logical orr or or OP1_7 OP2_0 dr sr HI)
-(logical xorr xor xor OP1_5 OP2_0 dr sr HI)
-(logical andbr andb and OP1_6 OP2_1 drb srb QI)
-(logical orbr orb or OP1_7 OP2_1 drb srb QI)
-(logical xorbr xorb xor OP1_5 OP2_1 drb srb QI)
-
-;and/or/xor register and immediate
-(define-pmacro (logical1 name insn insn1 opc1 opc2 op1 op2 mode)
-  (dni name 
-       (.str name "logical" )
-       ((PIPE OS) (IDOC ALU))
-       (.str insn " $"op1 ",$hash$"op2)
-       (+ opc1 opc2 op1 (f-op-bit1 0) op2)
-       (set mode op1 (insn1 mode op1 op2))
-       ()
-  )
-)
-(logical1 andri and and OP1_6 OP2_8 dr uimm3 HI)
-(logical1 orri or or OP1_7 OP2_8 dr uimm3 HI)
-(logical1 xorri xor xor OP1_5 OP2_8 dr uimm3 HI)
-(logical1 andbri andb and OP1_6 OP2_9 drb uimm3 QI)
-(logical1 orbri orb or OP1_7 OP2_9 drb uimm3 QI)
-(logical1 xorbri xorb xor OP1_5 OP2_9 drb uimm3 QI)
-
-;and/or/xor register and immediate
-(define-pmacro (logical2 name insn insn1 opc1 opc2 op1 op2 mode)
-  (dni name 
-       (.str name "logical" )
-       ((PIPE OS) (IDOC ALU))
-       (.str insn " $"op1 ",$hash$"op2)
-       (+ opc1 opc2 op1 op2)
-       (set mode op1 (insn1 mode op1 op2))
-       ()
-  )
-)
-(logical2 andrim and and OP1_6 OP2_6 reg8 uimm16 HI)
-(logical2 orrim or or OP1_7 OP2_6 reg8 uimm16 HI)
-(logical2 xorrim xor xor OP1_5 OP2_6 reg8 uimm16 HI)
-
-;and/or/xor register and immediate
-(define-pmacro (logical3 name insn insn1 opc1 opc2 op1 op2 mode)
-  (dni name 
-       (.str name "logical" )
-       ((PIPE OS) (IDOC ALU))
-       (.str insn " $"op1 ",$hash$"op2)
-       (+ opc1 opc2 op1 op2 (f-op-bit8 0))
-       (set mode op1 (insn1 mode op1 op2))
-       ()
-  )
-)
-(logical3 andbrim andb and OP1_6 OP2_7 regb8 uimm8 QI)
-(logical3 orbrim orb or OP1_7 OP2_7 regb8 uimm8 QI)
-(logical3 xorbrim xorb xor OP1_5 OP2_7 regb8 uimm8 QI)
-
-;and/or/xor register and indirect memory
-(define-pmacro (logical4 name insn insn1 opc1 opc2 op1 op2 mode)
-  (dni name
-       (.str name "logical" )
-       ((PIPE OS) (IDOC ALU))
-       (.str insn " $"op1 ",[$"op2"]")
-       (+ opc1 opc2 op1 (f-op-bit2 2) op2)
-       (set mode op1 (insn1 mode op1 (mem HI op2)))
-       ()
-  )
-)
-(logical4 and2 and and OP1_6 OP2_8 dr sr2 HI)
-(logical4 or2 or or OP1_7 OP2_8 dr sr2 HI)
-(logical4 xor2 xor xor OP1_5 OP2_8 dr sr2 HI)
-(logical4 andb2 andb and OP1_6 OP2_9 drb sr2 QI)
-(logical4 orb2 orb or OP1_7 OP2_9 drb sr2 QI)
-(logical4 xorb2 xorb xor OP1_5 OP2_9 drb sr2 QI)
-
-;and/or/xor register and indirect memory post increment
-(define-pmacro (logical5 name insn insn1 opc1 opc2 op1 op2 mode)
-  (dni name
-       (.str name "logical" )
-       ((PIPE OS) (IDOC ALU))
-       (.str insn " $"op1 ",[$"op2"+]")
-       (+ opc1 opc2 op1 (f-op-bit2 3) op2)
-       (sequence ()
-	   (set mode op1 (insn1 mode op1 (mem HI op2)))
-	   (set HI op2 (add HI op2 (const 2)))
-       )
-       ()
-  )
-)
-(logical5 and2i and and OP1_6 OP2_8 dr sr2 HI)
-(logical5 or2i or or OP1_7 OP2_8 dr sr2 HI)
-(logical5 xor2i xor xor OP1_5 OP2_8 dr sr2 HI)
-(logical5 andb2i andb and OP1_6 OP2_9 drb sr2 QI)
-(logical5 orb2i orb or OP1_7 OP2_9 drb sr2 QI)
-(logical5 xorb2i xorb xor OP1_5 OP2_9 drb sr2 QI)
-
-;add/sub register and immediate
-(define-pmacro (logical7 name insn insn1 opc1 opc2 op1 op2 mode dir)
-  (dni name 
-       (.str name "arithmetic" )
-       ((PIPE OS) (IDOC ALU))
-       (.str insn " $"dir"$"op1 ",$"op2)
-       (+ opc1 opc2 op1 op2)
-       (set (mem HI op1) (insn1 (mem HI op1) op2 ))
-       ()
-  )
-)
-(logical7 andpofr and and OP1_6 OP2_2 reg8 upof16 HI "pof")
-(logical7 orpofr or or OP1_7 OP2_2 reg8 upof16 HI "pof")
-(logical7 xorpofr xor xor OP1_5 OP2_2 reg8 upof16 HI "pof")
-(logical7 andbpofr andb and OP1_6 OP2_3 regb8 upof16 QI "pof")
-(logical7 orbpofr orb or OP1_7 OP2_3 regb8 upof16 QI "pof")
-(logical7 xorbpofr xorb xor OP1_5 OP2_3 regb8 upof16 QI "pof")
-
-;add/sub register and immediate
-(define-pmacro (logical8 name insn insn1 opc1 opc2 op1 op2 mode dir)
-  (dni name 
-       (.str name "arithmetic" )
-       ((PIPE OS) (IDOC ALU))
-       (.str insn " $"dir"$"op1 ",$"op2)
-       (+ opc1 opc2 op1 op2)
-       (set (mem HI op1) (insn1 (mem HI op1) op2 ))
-       ()
-  )
-)
-(logical8 andrpofr and and OP1_6 OP2_4 upof16 reg8 HI "pof")
-(logical8 orrpofr or or OP1_7 OP2_4 upof16 reg8 HI "pof")
-(logical8 xorrpofr xor xor OP1_5 OP2_4 upof16 reg8 HI "pof")
-(logical8 andbrpofr andb and OP1_6 OP2_5 upof16 regb8 QI "pof")
-(logical8 orbrpofr orb or OP1_7 OP2_5 upof16 regb8 QI "pof")
-(logical8 xorbrpofr xorb xor OP1_5 OP2_5 upof16 regb8 QI "pof")
-
-;and/or/xor register and direct memory
-(define-pmacro (logical6 name insn insn1 opc1 opc2 op1 op2 mode)
-  (dni name 
-       (.str name "arithmetic" )
-       ((PIPE OS) (IDOC ALU))
-       (.str insn " $"op1 ",$"op2)
-       (+ opc1 opc2 op1 op2)
-       (set mode op1 (insn1 mode op1 op2))
-       ()
-  )
-)
-
-;and/or/xor register and direct memory
-(define-pmacro (logical7 name insn insn1 opc1 opc2 op1 op2 mode)
-  (dni name 
-       (.str name "arithmetic" )
-       ((PIPE OS) (IDOC ALU))
-       (.str insn " $"op1 ",$"op2)
-       (+ opc1 opc2 op2 op1)
-       (set (mem HI op1) (insn1 (mem HI op1) op2))
-       ()
-  )
-)
-(logical6 andrm2 and and OP1_6 OP2_2 regmem8 memgr8 HI)
-(logical7 andrm3 and and OP1_6 OP2_4 memgr8 regmem8 HI)
-(logical6 andrm and and OP1_6 OP2_2 reg8 memory HI)
-(logical7 andrm1 and and OP1_6 OP2_4 memory reg8 HI)
-(logical6 orrm3 or or OP1_7 OP2_2 regmem8 memgr8 HI)
-(logical7 orrm2 or or OP1_7 OP2_4 memgr8 regmem8 HI)
-(logical6 orrm1 or or OP1_7 OP2_2 reg8 memory HI)
-(logical7 orrm or or OP1_7 OP2_4 memory reg8 HI)
-(logical6 xorrm3 xor xor OP1_5 OP2_2 regmem8 memgr8 HI)
-(logical7 xorrm2 xor xor OP1_5 OP2_4 memgr8 regmem8 HI)
-(logical6 xorrm1 xor xor OP1_5 OP2_2 reg8 memory HI)
-(logical7 xorrm xor xor OP1_5 OP2_4 memory reg8 HI)
-(logical6 andbrm2 andb and OP1_6 OP2_3 regbmem8 memgr8 QI)
-(logical7 andbrm3 andb and OP1_6 OP2_5 memgr8 regbmem8 QI)
-(logical6 andbrm andb and OP1_6 OP2_3 regb8 memory QI)
-(logical7 andbrm1 andb and OP1_6 OP2_5 memory regb8 QI)
-(logical6 orbrm3 orb or OP1_7 OP2_3 regbmem8 memgr8 QI)
-(logical7 orbrm2 orb or OP1_7 OP2_5 memgr8 regbmem8 QI)
-(logical6 orbrm1 orb or OP1_7 OP2_3 regb8 memory QI)
-(logical7 orbrm orb or OP1_7 OP2_5 memory regb8 QI)
-(logical6 xorbrm3 xorb xor OP1_5 OP2_3 regbmem8 memgr8 QI)
-(logical7 xorbrm2 xorb xor OP1_5 OP2_5 memgr8 regbmem8 QI)
-(logical6 xorbrm1 xorb xor OP1_5 OP2_3 regb8 memory QI)
-(logical7 xorbrm xorb xor OP1_5 OP2_5 memory regb8 QI)
-
-;****************************************************************
-;logical insn
-;****************************************************************
-;mov registers
-(define-pmacro (move name insn opc1 opc2 op1 op2 mode)
-  (dni name 
-       (.str name "mov registers" )
-       ((PIPE OS) (IDOC MOVE))
-       (.str insn " $"op1 ",$"op2)
-       (+ opc1 opc2 op1 op2)
-       (set mode op1 op2)
-       ()
-  )
-)
-(move movr mov OP1_15 OP2_0 dr sr HI)
-(move movrb movb OP1_15 OP2_1 drb srb HI)
-
-;mov register and immediate
-(define-pmacro (move1 name insn opc1 opc2 op1 op2 mode)
-  (dni name 
-       (.str name "move" )
-       ((PIPE OS) (IDOC MOVE))
-       (.str insn " $"op1 ",$hash$"op2)
-       (+ opc1 opc2 op2 op1)
-       (set mode op1 op2)
-       ()
-  )
-)
-(move1 movri mov  OP1_14 OP2_0 dri u4 HI)
-(move1 movbri movb  OP1_14 OP2_1 srb u4 QI)
-
-; MOV Rwn,#data16
-(dni movi "move immediate to register"
-     ((PIPE OS) (IDOC MOVE))
-     "mov $reg8,$hash$uimm16"
-     (+ OP1_14 OP2_6 reg8 uimm16)
-     (set HI reg8 uimm16)
-     ()
-)
-
-; MOVB reg,#data8
-(dni movbi "move immediate to register"
-     ((PIPE OS) (IDOC MOVE))
-     "movb $regb8,$hash$uimm8"
-     (+ OP1_14 OP2_7 regb8 uimm8 (f-op-bit8 0))
-     (set QI regb8 uimm8)
-     ()
-)
-
-;move and indirect memory
-(define-pmacro (mov2 name insn opc1 opc2 op1 op2 mode)
-  (dni name
-       (.str name "move" )
-       ((PIPE OS) (IDOC MOVE))
-       (.str insn " $"op1 ",[$"op2"]")
-       (+ opc1 opc2 op1 op2)
-       (set mode op1 (mem HI op2))
-       ()
-  )
-)
-(mov2 movr2 mov OP1_10 OP2_8 dr sr HI)
-(mov2 movbr2 movb OP1_10 OP2_9 drb sr QI)
-
-;move and indirect memory
-(define-pmacro (mov3 name insn opc1 opc2 op1 op2 mode)
-  (dni name
-       (.str name "move" )
-       ((PIPE OS) (IDOC MOVE))
-       (.str insn " [$"op2 "],$"op1)
-       (+ opc1 opc2 op1 op2)
-       (set mode op1 (mem HI op2))
-       ()
-  )
-)
-(mov3 movri2 mov OP1_11 OP2_8 dr sr HI)
-(mov3 movbri2 movb OP1_11 OP2_9 drb sr QI)
-
-;move and indirect memory
-(define-pmacro (mov4 name insn opc1 opc2 op1 op2 mode)
-  (dni name
-       (.str name "move" )
-       ((PIPE OS) (IDOC MOVE))
-       (.str insn " [-$"op2 "],$"op1)
-       (+ opc1 opc2 op1 op2)
-       (sequence ()
-	  (set op1 (sub op2 (const HI 2)))
-	  (set HI (mem HI op2) op1)
-       )
-       ()
-  )
-)
-(mov4 movri3 mov OP1_8 OP2_8 dr sr HI)
-(mov4 movbri3 movb OP1_8 OP2_9 drb sr QI)
-
-;mov register and indirect memory post increment
-(define-pmacro (mov5 name insn opc1 opc2 op1 op2 mode)
-  (dni name
-       (.str name "move" )
-       ((PIPE OS) (IDOC MOVE))
-       (.str insn " $"op1 ",[$"op2"+]")
-       (+ opc1 opc2 op1 op2)
-       (sequence ()
-	   (set mode op1 (mem HI op2))
-	   (set HI op2 (add HI op2 (const 2)))
-       )
-       ()
-  )
-)
-(mov5 mov2i mov OP1_9 OP2_8 dr sr HI)
-(mov5 movb2i movb OP1_9 OP2_9 drb sr HI)
-
-;mov indirect memory
-(define-pmacro (mov6 name insn opc1 opc2 op1 op2 mode)
-  (dni name
-       (.str name "move" )
-       ((PIPE OS) (IDOC MOVE))
-       (.str insn " [$"op1 "],[$"op2"]")
-       (+ opc1 opc2 op1 op2)
-       (set HI (mem HI op1) (mem HI op2))
-       ()
-  )
-)
-(mov6 mov6i mov OP1_12 OP2_8 dr sr HI)
-(mov6 movb6i movb OP1_12 OP2_9 dr sr HI)
-
-;mov indirect memory
-(define-pmacro (mov7 name insn opc1 opc2 op1 op2 mode)
-  (dni name
-       (.str name "move" )
-       ((PIPE OS) (IDOC MOVE))
-       (.str insn " [$"op1 "+],[$"op2"]")
-       (+ opc1 opc2 op1 op2)
-       (sequence ()
-          (set mode (mem mode op1) (mem mode op2))
-          (set mode op1 (add mode op1 (const mode 2)))
-       )
-       ()
-  )
-)
-(mov7 mov7i mov OP1_13 OP2_8 dr sr HI)
-(mov7 movb7i movb OP1_13 OP2_9 dr sr HI)
-
-;mov indirect memory
-(define-pmacro (mov8 name insn opc1 opc2 op1 op2 mode)
-  (dni name
-       (.str name "move" )
-       ((PIPE OS) (IDOC MOVE))
-       (.str insn " [$"op1 "],[$"op2"+]")
-       (+ opc1 opc2 op1 op2)
-       (sequence ()
-          (set mode (mem mode op1) (mem mode op2))
-          (set mode op2 (add mode op2 (const mode 2)))
-       )
-       ()
-  )
-)
-(mov8 mov8i mov OP1_14 OP2_8 dr sr HI)
-(mov8 movb8i movb OP1_14 OP2_9 dr sr HI)
-
-;mov indirect memory
-(define-pmacro (mov9 name insn opc1 opc2 op1 op2 mode)
-  (dni name
-       (.str name "move" )
-       ((PIPE OS) (IDOC MOVE))
-       (.str insn " $"op1 ",[$"op2"+$hash$"uimm16"]")
-       (+ opc1 opc2 op1 op2 uimm16)
-       (sequence ((mode tmp1))
-	   (set mode tmp1 (add HI op2 uimm16))
-	   (set mode op1 (mem HI tmp1))
-       )
-       ()
-  )
-)
-(mov9 mov9i mov OP1_13 OP2_4 dr sr HI)
-(mov9 movb9i movb OP1_15 OP2_4 drb sr QI)
-
-;mov indirect memory
-(define-pmacro (mov10 name insn opc1 opc2 op1 op2 mode)
-  (dni name
-       (.str name "move" )
-       ((PIPE OS) (IDOC MOVE))
-       (.str insn " [$"op2"+$hash$"uimm16 "],$"op1)
-       (+ opc1 opc2 op1 op2 uimm16)
-       (sequence ((mode tmp1))
-	   (set mode tmp1 (add HI op1 uimm16))
-	   (set mode (mem HI tmp1) op1)
-       )
-       ()
-  )
-)
-(mov10 mov10i mov OP1_12 OP2_4 dr sr HI)
-(mov10 movb10i movb OP1_14 OP2_4 drb sr QI)
-
-;move and indirect memory
-(define-pmacro (mov11 name insn opc1 opc2 op1 op2 mode)
-  (dni name
-       (.str name "move" )
-       ((PIPE OS) (IDOC MOVE))
-       (.str insn " [$"op1 "],$"op2)
-       (+ opc1 opc2 (f-op-lbit4 0) op1 op2)
-       (set (mem mode op1) (mem HI op2))
-       ()
-  )
-)
-(mov11 movri11 mov OP1_8 OP2_4 src2 memory HI)
-(mov11 movbri11 movb OP1_10 OP2_4 src2 memory HI)
-
-;move and indirect memory
-(define-pmacro (mov12 name insn opc1 opc2 op1 op2 mode)
-  (dni name
-       (.str name "move" )
-       ((PIPE OS) (IDOC MOVE))
-       (.str insn " $"op2 ",[$"op1"]")
-       (+ opc1 opc2 (f-op-lbit4 0) op1 op2)
-       (set (mem HI op2) (mem mode op1))
-       ()
-  )
-)
-(mov12 movri12 mov OP1_9 OP2_4 src2 memory HI)
-(mov12 movbri12 movb OP1_11 OP2_4 src2 memory HI)
-
-(define-pmacro (movemem3 name insn opc1 opc2 op1 op2  dir)
-  (dni name 
-       (.str name "move" )
-       ((PIPE OS) (IDOC MOVE))
-       (.str insn " $"op1 ",$hash$"dir"$"op2)
-       (+ opc1 opc2 op1 op2)
-       (set HI op1 op2)
-       ()
-  )
-)
-(movemem3 movehm5 mov OP1_14 OP2_6 regoff8 upof16 "pof")
-(movemem3 movehm6 mov OP1_14 OP2_6 regoff8 upag16 "pag")
-(movemem3 movehm7 mov OP1_14 OP2_6 regoff8 useg16 "segm")
-(movemem3 movehm8 mov OP1_14 OP2_6 regoff8 usof16 "sof")
-
-(define-pmacro (movemem4 name insn opc1 opc2 op1 op2 dir)
-  (dni name 
-       (.str name "move" )
-       ((PIPE OS) (IDOC MOVE))
-       (.str insn " $"op1 ",$hash$"dir"$"op2)
-       (+ opc1 opc2 op1 op2 (f-op-bit8 0))
-       (set QI op1 op2)
-       ()
-  )
-)
-(movemem4 movehm9 movb OP1_14 OP2_7 regb8 uimm8 "pof")
-(movemem4 movehm10 movb OP1_14 OP2_7 regoff8 uimm8 "pag")
-
-(define-pmacro (movemem name insn opc1 opc2 op1 op2 mode dir)
-  (dni name 
-       (.str name "move" )
-       ((PIPE OS) (IDOC MOVE))
-       (.str insn " $"op1 ",$"dir"$"op2)
-       (+ opc1 opc2 op1 op2)
-       (set mode op1 (mem HI op2))
-       ()
-  )
-)
-(movemem movrmp mov OP1_15 OP2_2 regoff8 upof16 HI "pof")
-(movemem movrmp1 movb OP1_15 OP2_3 regb8 upof16 QI "pof")
-(movemem movrmp2 mov OP1_15 OP2_2 regoff8 upag16 HI "pag")
-(movemem movrmp3 movb OP1_15 OP2_3 regb8 upag16 QI "pag")
-
-(define-pmacro (movemem1 name insn opc1 opc2 op1 op2 dir)
-  (dni name 
-       (.str name "move" )
-       ((PIPE OS) (IDOC MOVE))
-       (.str insn " $"dir"$"op1 ",$"op2)
-       (+ opc1 opc2 op2 op1)
-       (set (mem HI op1) op2 )
-       ()
-  )
-)
-(movemem1 movrmp4 mov OP1_15 OP2_6  upof16 regoff8 "pof")
-(movemem1 movrmp5 movb OP1_15 OP2_7 upof16 regb8 "pof")
-
-(define-pmacro (movemem2 name insn opc1 opc2 op1 op2 mode dir)
-  (dni name 
-       (.str name "move" )
-       ((PIPE OS) (IDOC MOVE))
-       (.str insn " $"op1 ",$hash$"dir"$"op2)
-       (+ opc1 opc2 op2 op1)
-       (set mode op1 op2)
-       ()
-  )
-)
-(movemem2 movehm1 mov OP1_14 OP2_0 dri u4 HI "pof")
-(movemem2 movehm2 movb OP1_14 OP2_1 srb u4 QI "pof")
-(movemem2 movehm3 mov OP1_14 OP2_0 dri u4 HI "pag")
-(movemem2 movehm4 movb OP1_14 OP2_1 srb u4 QI "pag")
-
-;move register and direct memory
-(define-pmacro (move12 name insn opc1 opc2 op1 op2 mode)
-  (dni name 
-       (.str name "move" )
-       ((PIPE OS) (IDOC MOVE))
-       (.str insn " $"op1 ",$"op2)
-       (+ opc1 opc2 op1 op2)
-       (set mode op1 (mem HI op2))
-       ()
-  )
-)
-
-;move register and direct memory
-(define-pmacro (move13 name insn opc1 opc2 op1 op2 mode)
-  (dni name 
-       (.str name "move" )
-       ((PIPE OS) (IDOC MOVE))
-       (.str insn " $"op1 ",$"op2)
-       (+ opc1 opc2 op2 op1)
-       (set (mem HI op1) op2)
-       ()
-  )
-)
-(move12 mve12 mov OP1_15 OP2_2 regmem8 memgr8 HI)
-(move13 mve13 mov OP1_15 OP2_6 memgr8 regmem8 HI)
-(move12 mover12 mov OP1_15 OP2_2 reg8 memory HI)
-(move13 mvr13 mov OP1_15 OP2_6 memory reg8 HI)
-(move12 mver12 movb OP1_15 OP2_3 regbmem8 memgr8 QI)
-(move13 mver13 movb OP1_15 OP2_7 memgr8 regbmem8 QI)
-(move12 movr12 movb OP1_15 OP2_3 regb8 memory QI)
-(move13 movr13 movb OP1_15 OP2_7 memory regb8 QI)
-
-; MOVBS Rw,Rb
-(dni movbsrr "mov byte register with sign extension to word register"
-     ((PIPE OS) (IDOC MOVE))
-     "movbs $sr,$drb"
-     (+ OP1_13 OP2_0 drb sr)
-     (sequence ()
-         (if (and QI drb (const 128))
-	     (set HI sr (or HI (const HI 65280) drb)))
-         (set HI sr (and HI (const HI 255) drb)) 
-     )
-     ()
-)
-
-; MOVBZ Rw,Rb
-(dni movbzrr "mov byte register with zero extension to word register"
-     ((PIPE OS) (IDOC MOVE))
-     "movbz $sr,$drb"
-     (+ OP1_12 OP2_0 drb sr)
-     (set HI sr (and HI (const HI 255) drb))
-     ()
-)
-
-; MOVBS reg,POF mem
-(dni movbsrpofm "mov memory to byte register"
-     ((PIPE OS) (IDOC MOVE))
-     "movbs $regmem8,$pof$upof16"
-     (+ OP1_13 OP2_2 regmem8 upof16)
-     (set QI regmem8 (mem HI upof16))
-     ()
-)
-
-; MOVBS pof,reg
-(dni movbspofmr "mov memory to byte register"
-     ((PIPE OS) (IDOC MOVE))
-     "movbs $pof$upof16,$regbmem8"
-     (+ OP1_13 OP2_5 upof16 regbmem8 )
-     (set QI  (mem HI upof16) regbmem8)
-     ()
-)
-
-; MOVBZ reg,POF mem
-(dni movbzrpofm "mov memory to byte register"
-     ((PIPE OS) (IDOC MOVE))
-     "movbz $reg8,$pof$upof16"
-     (+ OP1_12 OP2_2 reg8 upof16)
-     (set QI reg8 (mem HI upof16))
-     ()
-)
-
-; MOVBZ pof,reg
-(dni movbzpofmr "mov memory to byte register"
-     ((PIPE OS) (IDOC MOVE))
-     "movbz $pof$upof16,$regb8"
-     (+ OP1_12 OP2_5 upof16 regb8 )
-     (set QI  (mem HI upof16) regb8)
-     ()
-)
-
-;move register and direct memory
-(define-pmacro (move14 name insn opc1 opc2 op1 op2 )
-  (dni name 
-       (.str name "move" )
-       ((PIPE OS) (IDOC MOVE))
-       (.str insn " $"op1 ",$"op2)
-       (+ opc1 opc2 op1 op2)
-       (set HI op1 (and HI (const HI 255) (mem QI op2)))
-       ()
-  )
-)
-
-;move register and direct memory
-(define-pmacro (move15 name insn opc1 opc2 op1 op2 )
-  (dni name 
-       (.str name "move" )
-       ((PIPE OS) (IDOC MOVE))
-       (.str insn " $"op1 ",$"op2)
-       (+ opc1 opc2 op2 op1)
-       (set HI (mem HI op1) (and HI (const HI 255) op2))
-       ()
-  )
-)
-(move14 movebs14 movbs OP1_13 OP2_2 regmem8 memgr8 )
-(move15 movebs15 movbs OP1_13 OP2_5 memgr8 regbmem8 )
-(move14 moverbs14 movbs OP1_13 OP2_2 reg8 memory )
-(move15 movrbs15 movbs OP1_13 OP2_5 memory regb8 )
-(move14 movebz14 movbz OP1_12 OP2_2 regmem8 memgr8 )
-(move15 movebz15 movbz OP1_12 OP2_5 memgr8 regbmem8 )
-(move14 moverbz14 movbz OP1_12 OP2_2 reg8 memory )
-(move15 movrbz15 movbz OP1_12 OP2_5 memory regb8 )
-
-
-;mov registers
-(define-pmacro (moveb1 name insn opc1 opc2 op1 op2)
-  (dni name 
-       (.str name "move" )
-       ((PIPE OS) (IDOC MOVE))
-       (.str insn " $"op2 ",$"op1)
-       (+ opc1 opc2 op1 op2)
-       (sequence ()
-           (if (and QI op1 (const 128))
-	       (set HI op2 (or HI (const HI 65280) op1)))
-           (set HI op2 (and HI (const HI 255) op1)) 
-       )
-       ()
-  )
-)
-(moveb1 movrbs movbs OP1_13 OP2_0 drb sr )
-(moveb1 movrbz movbz OP1_12 OP2_0 drb sr )
-
-
-
-;jump and call insns
-;******************************************************************
-;Absolute conditional jump
-(define-pmacro (jmpabs name insn)
-  (dni name
-     (.str name "Absolute conditional jump" )
-     ((PIPE OS) (IDOC JMP))
-     (.str insn " $extcond,$caddr")
-     (+ OP1_14 OP2_10 extcond (f-op-bitone 0) bitone bit01 caddr)
-     (sequence ((HI tmp1) (HI tmp2))
-        (set tmp1 (mem HI caddr))
-        (set tmp2 (sub HI pc (mem HI caddr)))
-        (if (gt tmp2 (const 0)) ;; FIXME: (lt tmp2 (const 32)) (eq tmp2 (const 32))
-            (set bitone (const 1)))
-	(if (lt tmp2 (const 0)) ;; FIXME: (eq tmp2 (const 0)) (gt tmp2 (const 32))
-            (set bitone (const 0)))
-        (if (eq extcond (const 1)) ;; FIXME: (ne extcond cc_Z))
-             (set bit01 (const 0))    
-             (set HI pc (mem HI caddr)))
-	(if (ne extcond (const 1)) ;; FIXME: (eq extcond cc_Z))
-             (set bit01 (const 1))
-             (set HI pc (add HI pc (const 2))))
-     )
-     ()
-  )
-)
-
-(jmpabs jmpa0 jmpa+)
-(jmpabs jmpa1 jmpa)
-
-; JMPA- cc,caddr
-(dni jmpa- "Absolute conditional jump"
-     (COND-CTI (PIPE OS) (IDOC JMP))
-     "jmpa- $extcond,$caddr"
-     (+ OP1_14 OP2_10 extcond (f-op-bitone 0) bitone (f-op-1bit 1) caddr)
-     (sequence ((HI tmp1) (HI tmp2))
-        (set tmp1 (mem HI caddr))
-        (set tmp2 (sub HI pc (mem HI caddr)))
-        (if (gt tmp2 (const 0)) ;; FIXME: (lt tmp2 (const 32)) (eq tmp2 (const 32))
-            (set bitone (const 1)))
-	(if (lt tmp2 (const 0)) ;; FIXME: (eq tmp2 (const 0)) (gt tmp2 (const 32))
-            (set bitone (const 0)))
-        (set HI pc (add HI pc (const 2)))
-     )
-     ()
-)
-
-; JMPI cc,[Rwn]
-(dni jmpi "Indirect conditional jump"
-     (COND-CTI (PIPE OS) (IDOC JMP))
-     "jmpi $icond,[$sr]"
-     (+ OP1_9 OP2_12 icond sr)
-     (sequence ()
-        (if (eq icond (const 1))
-             (set HI pc (mem HI sr)))
-             (set HI pc (add HI pc (const 2)))
-     )
-     ()
-)
-
-(define-pmacro (jmprel name insn opc1)
-  (dni name
-       (.str name "conditional" )
-       (COND-CTI (PIPE OS) (IDOC JMP))
-       (.str insn " $cond,$rel")
-       (+ opc1 OP2_13 rel)
-       (sequence ()
-           (if (eq cond (const 1))
-               (sequence ()
-		    (if (lt QI rel (const 0))
-			(sequence ()
-				  ;; FIXME: (neg QI rel)
-				  ;; FIXME: (add QI rel (const 1))
-				  ;; FIXME: (mul QI rel (const 2))
-				  (set HI pc (sub HI pc rel))
-				  ))
-                    (set HI pc (add HI pc (mul QI rel (const 2))))
-               )
-            )
-            (set HI pc pc)
-       )
-       ()
-  )
-)
-
-(jmprel jmpr_nenz jmpr  COND_NE_NZ )
-(jmprel jmpr_sgt jmpr  COND_SGT )
-(jmprel jmpr_z jmpr  COND_Z )
-(jmprel jmpr_v jmpr  COND_V )
-(jmprel jmpr_nv jmpr  COND_NV )
-(jmprel jmpr_n jmpr  COND_N )
-(jmprel jmpr_nn jmpr  COND_NN )
-(jmprel jmpr_c jmpr  COND_C )
-(jmprel jmpr_nc jmpr  COND_NC )
-(jmprel jmpr_eq jmpr  COND_EQ )
-(jmprel jmpr_ne jmpr  COND_NE )
-(jmprel jmpr_ult jmpr  COND_ULT )
-(jmprel jmpr_ule jmpr  COND_ULE )
-(jmprel jmpr_uge jmpr  COND_UGE )
-(jmprel jmpr_ugt jmpr  COND_UGT )
-(jmprel jmpr_sle jmpr  COND_SLE )
-(jmprel jmpr_sge jmpr  COND_SGE )
-(jmprel jmpr_net jmpr  COND_NET )
-(jmprel jmpr_uc jmpr  COND_UC )
-(jmprel jmpr_slt jmpr  COND_SLT )
-
-
-
-
-; JMPS seg,caddr
-(dni jmpseg "absolute inter-segment jump"
-     (UNCOND-CTI(PIPE OS) (IDOC JMP))
-     "jmps $hash$segm$useg8,$hash$sof$usof16"
-     (+ OP1_15 OP2_10 seg usof16)
-     (sequence ()
-          (if (eq BI sgtdisbit (const BI 0))
-	      (set QI (reg h-cr 10) useg8))
-	  ;; FIXME: previous indentation suggested this nop was the `else'
-	  ;; clause of the previous `if'.
-	  (nop)
-          (set HI pc usof16)
-     )
-     ()
-)
-
-; JMPS seg,caddr
-(dni jmps "absolute inter-segment jump"
-     (UNCOND-CTI(PIPE OS) (IDOC JMP))
-     "jmps $seg,$caddr"
-     (+ OP1_15 OP2_10 seg caddr)
-     (sequence ()
-          (if (eq BI sgtdisbit (const BI 0))
-	      (set QI (reg h-cr 10) seg))
-	  ;; FIXME: previous indentation suggested this nop was the `else'
-	  ;; clause of the previous `if'.
-	  (nop)
-          (set HI pc caddr)
-     )
-     ()
-)
-
-
-;relative jump if bit set
-;JB bitaddrQ.q,rel
-(dni jb "relative jump if bit set"
-     ((PIPE OS) (IDOC JMP))
-     "jb $genreg$dot$qlobit,$relhi"
-     (+ OP1_8 OP2_10 genreg relhi qlobit (f-qhibit 0))
-     (sequence ((HI tmp1) (HI tmp2))
-          (set HI tmp1 genreg)
-          (set HI tmp2 (const 1))
-          ;;(sll HI tmp2 qlobit) - FIXME: missing (set ...)
-          (set HI tmp2 (and tmp1 tmp2))
-          (if (eq tmp2 (const 1)) ;; FIXME: (ne tmp2 0)?
-             (sequence ()
-                (if (lt QI relhi (const 0))
-		    (set HI pc (add HI pc (mul QI relhi (const 2)))))
-             ))
-         (set HI pc (add HI pc (const 4))) ;; FIXME: Is this right?
-     )
-     ()
-)
-
-;relative jump if bit set and clear bit
-;JBC bitaddrQ.q,rel
-(dni jbc "relative jump if bit set and clear bit"
-     ((PIPE OS) (IDOC JMP))
-     "jbc $genreg$dot$qlobit,$relhi"
-     (+ OP1_10 OP2_10 genreg relhi qlobit (f-qhibit 0))
-     (sequence ((HI tmp1) (HI tmp2))
-          (set HI tmp1 genreg)
-          (set HI tmp2 (const 1))
-          ;;(sll HI tmp2 qlobit) - FIXME: missing (set ...)
-          (set HI tmp2 (and tmp1 tmp2))
-          (if (eq tmp2 (const 1)) ;; FIXME: (ne tmp2 0)?
-             (sequence ()
-		;; FIXME: The `else' clause has several statements.
-                (if (lt QI relhi (const 0))
-		    (set tmp2 (const 1))
-		    (set tmp1 genreg)
-		    ;; FIXME: (sll tmp2 qlobit)
-		    ;; FIXME: (inv tmp2)
-		    (set HI tmp1 (and tmp1 tmp2))
-		    (set HI genreg tmp1)
-		    (set HI pc (add HI pc (mul QI relhi (const 2)))))
-             ))
-          (set HI pc (add HI pc (const 4))) ;; FIXME: Is this right?
-     )
-   [...]

[diff truncated at 100000 bytes]


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