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* [binutils-gdb/binutils-2_39-branch] x86: correct VMOVSH attributes
@ 2022-07-18 15:32 Jan Beulich
0 siblings, 0 replies; only message in thread
From: Jan Beulich @ 2022-07-18 15:32 UTC (permalink / raw)
To: bfd-cvs
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=b8b9506514c9d77670f92121c27a0a24d0c7aa13
commit b8b9506514c9d77670f92121c27a0a24d0c7aa13
Author: Jan Beulich <jbeulich@suse.com>
Date: Mon Jul 18 17:31:57 2022 +0200
x86: correct VMOVSH attributes
Both forms were missing VexW0 (thus allowing Evex.W=1 to be encoded by
suitable means, which would cause #UD). The memory operand form further
was using the wrong Masking value, thus allowing zeroing-masking to be
encoded for the store form (which would again cause #UD).
(cherry picked from commit 7e864bf71d55626dce94df26ebaf11f65b4d7b65)
Diff:
---
gas/testsuite/gas/i386/evex-wig.s | 12 ++++++++++++
gas/testsuite/gas/i386/evex-wig1-intel.d | 9 +++++++++
gas/testsuite/gas/i386/evex-wig1.d | 9 +++++++++
opcodes/i386-opc.tbl | 4 ++--
opcodes/i386-tbl.h | 6 +++---
5 files changed, 35 insertions(+), 5 deletions(-)
diff --git a/gas/testsuite/gas/i386/evex-wig.s b/gas/testsuite/gas/i386/evex-wig.s
index df73c78eb4f..de8c16c7c20 100644
--- a/gas/testsuite/gas/i386/evex-wig.s
+++ b/gas/testsuite/gas/i386/evex-wig.s
@@ -62,6 +62,18 @@ _start:
{evex} vpinsrw $0, %eax, %xmm0, %xmm0
{evex} vpinsrw $0, 2(%eax), %xmm0, %xmm0
+ vmovss %xmm0, %xmm0, %xmm0{%k7}
+ vmovss (%eax), %xmm0{%k7}
+ vmovss %xmm0, (%eax){%k7}
+
+ vmovsd %xmm0, %xmm0, %xmm0{%k7}
+ vmovsd (%eax), %xmm0{%k7}
+ vmovsd %xmm0, (%eax){%k7}
+
+ vmovsh %xmm0, %xmm0, %xmm0{%k7}
+ vmovsh (%eax), %xmm0{%k7}
+ vmovsh %xmm0, (%eax){%k7}
+
vpmovsxbd %xmm5, %zmm6{%k7} # AVX512
vpmovsxbd %xmm5, %zmm6{%k7}{z} # AVX512
vpmovsxbd (%ecx), %zmm6{%k7} # AVX512
diff --git a/gas/testsuite/gas/i386/evex-wig1-intel.d b/gas/testsuite/gas/i386/evex-wig1-intel.d
index 0bf2be8fc9b..202c4f5c024 100644
--- a/gas/testsuite/gas/i386/evex-wig1-intel.d
+++ b/gas/testsuite/gas/i386/evex-wig1-intel.d
@@ -45,6 +45,15 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 62 f3 fd 08 22 40 01 00 vpinsrd xmm0,xmm0,DWORD PTR \[eax\+0x4\],0x0
[ ]*[a-f0-9]+: 62 f1 fd 08 c4 c0 00 vpinsrw xmm0,xmm0,eax,0x0
[ ]*[a-f0-9]+: 62 f1 fd 08 c4 40 01 00 vpinsrw xmm0,xmm0,WORD PTR \[eax\+0x2\],0x0
+[ ]*[a-f0-9]+: 62 f1 7e 0f 10 c0 vmovss xmm0\{k7\},xmm0,xmm0
+[ ]*[a-f0-9]+: 62 f1 7e 0f 10 00 vmovss xmm0\{k7\},DWORD PTR \[eax\]
+[ ]*[a-f0-9]+: 62 f1 7e 0f 11 00 vmovss DWORD PTR \[eax\]\{k7\},xmm0
+[ ]*[a-f0-9]+: 62 f1 ff 0f 10 c0 vmovsd xmm0\{k7\},xmm0,xmm0
+[ ]*[a-f0-9]+: 62 f1 ff 0f 10 00 vmovsd xmm0\{k7\},QWORD PTR \[eax\]
+[ ]*[a-f0-9]+: 62 f1 ff 0f 11 00 vmovsd QWORD PTR \[eax\]\{k7\},xmm0
+[ ]*[a-f0-9]+: 62 f5 7e 0f 10 c0 vmovsh xmm0\{k7\},xmm0,xmm0
+[ ]*[a-f0-9]+: 62 f5 7e 0f 10 00 vmovsh xmm0\{k7\},WORD PTR \[eax\]
+[ ]*[a-f0-9]+: 62 f5 7e 0f 11 00 vmovsh WORD PTR \[eax\]\{k7\},xmm0
[ ]*[a-f0-9]+: 62 f2 fd 4f 21 f5 vpmovsxbd zmm6\{k7\},xmm5
[ ]*[a-f0-9]+: 62 f2 fd cf 21 f5 vpmovsxbd zmm6\{k7\}\{z\},xmm5
[ ]*[a-f0-9]+: 62 f2 fd 4f 21 31 vpmovsxbd zmm6\{k7\},XMMWORD PTR \[ecx\]
diff --git a/gas/testsuite/gas/i386/evex-wig1.d b/gas/testsuite/gas/i386/evex-wig1.d
index def41b32868..0a9a534d957 100644
--- a/gas/testsuite/gas/i386/evex-wig1.d
+++ b/gas/testsuite/gas/i386/evex-wig1.d
@@ -45,6 +45,15 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 62 f3 fd 08 22 40 01 00 vpinsrd \$0x0,0x4\(%eax\),%xmm0,%xmm0
[ ]*[a-f0-9]+: 62 f1 fd 08 c4 c0 00 vpinsrw \$0x0,%eax,%xmm0,%xmm0
[ ]*[a-f0-9]+: 62 f1 fd 08 c4 40 01 00 vpinsrw \$0x0,0x2\(%eax\),%xmm0,%xmm0
+[ ]*[a-f0-9]+: 62 f1 7e 0f 10 c0 vmovss %xmm0,%xmm0,%xmm0\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7e 0f 10 00 vmovss \(%eax\),%xmm0\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 7e 0f 11 00 vmovss %xmm0,\(%eax\)\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 ff 0f 10 c0 vmovsd %xmm0,%xmm0,%xmm0\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 ff 0f 10 00 vmovsd \(%eax\),%xmm0\{%k7\}
+[ ]*[a-f0-9]+: 62 f1 ff 0f 11 00 vmovsd %xmm0,\(%eax\)\{%k7\}
+[ ]*[a-f0-9]+: 62 f5 7e 0f 10 c0 vmovsh %xmm0,%xmm0,%xmm0\{%k7\}
+[ ]*[a-f0-9]+: 62 f5 7e 0f 10 00 vmovsh \(%eax\),%xmm0\{%k7\}
+[ ]*[a-f0-9]+: 62 f5 7e 0f 11 00 vmovsh %xmm0,\(%eax\)\{%k7\}
[ ]*[a-f0-9]+: 62 f2 fd 4f 21 f5 vpmovsxbd %xmm5,%zmm6\{%k7\}
[ ]*[a-f0-9]+: 62 f2 fd cf 21 f5 vpmovsxbd %xmm5,%zmm6\{%k7\}\{z\}
[ ]*[a-f0-9]+: 62 f2 fd 4f 21 31 vpmovsxbd \(%ecx\),%zmm6\{%k7\}
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 859412e410b..b788f803797 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3684,8 +3684,8 @@ vmaxsh, 0xf35f, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap5|VexVVVV|V
vminph, 0x5d, None, CpuAVX512_FP16, Modrm|VexVVVV|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
vminsh, 0xf35d, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap5|VexVVVV|VexW0|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM }
-vmovsh, 0xf310, None, CpuAVX512_FP16, D|Modrm|EVexLIG|Masking=3|EVexMap5|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex, RegXMM }
-vmovsh, 0xf310, None, CpuAVX512_FP16, D|Modrm|EVexLIG|Masking=3|EVexMap5|VexVVVV|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
+vmovsh, 0xf310, None, CpuAVX512_FP16, D|Modrm|EVexLIG|MaskingMorZ|EVexMap5|VexW0|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex, RegXMM }
+vmovsh, 0xf310, None, CpuAVX512_FP16, D|Modrm|EVexLIG|Masking=3|EVexMap5|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
vmovw, 0x666e, None, CpuAVX512_FP16, D|Modrm|EVex128|VexWIG|EVexMap5|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex, RegXMM }
vmovw, 0x667e, None, CpuAVX512_FP16, D|RegMem|EVex128|VexWIG|EVexMap5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Reg32 }
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 1f72da042d8..5b11d0ccfb0 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -58553,8 +58553,8 @@ const insn_template i386_optab[] =
1, 0, 0, 0, 0, 0 } } } },
{ "vmovsh", 0x10, None, 2,
{ 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5, 2, 0, 0,
- 0, 4, 3, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 5, 2, 0, 0,
+ 0, 4, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -58568,7 +58568,7 @@ const insn_template i386_optab[] =
1, 0, 0, 0, 0, 0 } } } },
{ "vmovsh", 0x10, None, 3,
{ 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 5, 2, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 5, 2, 0, 0,
0, 4, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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