From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7867) id 58AC73858028; Mon, 1 Aug 2022 08:03:15 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 58AC73858028 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: liu & zhensong To: bfd-cvs@sourceware.org Subject: [binutils-gdb] opcodes: LoongArch: add "ret" instruction to reduce typing X-Act-Checkin: binutils-gdb X-Git-Author: WANG Xuerui X-Git-Refname: refs/heads/master X-Git-Oldrev: 3f6e97039ec6f476b6fe09768f4b89722ffef10f X-Git-Newrev: 20f2e2686c79a5ac951f0cc283f385c16bda5d50 Message-Id: <20220801080315.58AC73858028@sourceware.org> Date: Mon, 1 Aug 2022 08:03:15 +0000 (GMT) X-BeenThere: binutils-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 01 Aug 2022 08:03:15 -0000 https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D20f2e2686c79= a5ac951f0cc283f385c16bda5d50 commit 20f2e2686c79a5ac951f0cc283f385c16bda5d50 Author: WANG Xuerui Date: Wed Jul 27 19:07:57 2022 +0800 opcodes: LoongArch: add "ret" instruction to reduce typing =20 This syntactic sugar is present in both classical and emerging architectures, like Alpha, SPARC and RISC-V, and assembler macros doing the same thing can already be found in the wild e.g. [1], proving the feature's popularity. It's better to provide support directly in the assembler so downstream users wouldn't have to re-invent this over and over again. =20 [1]: https://sourceware.org/git/?p=3Dglibc.git;a=3Dblob;f=3Dsysdeps/uni= x/sysv/linux/loongarch/sysdep.h;h=3Dc586df819cd90;hb=3DHEAD#l28 Diff: --- gas/testsuite/gas/loongarch/jmp_op.d | 1 + gas/testsuite/gas/loongarch/jmp_op.s | 1 + ld/testsuite/ld-loongarch-elf/jmp_op.d | 1 + ld/testsuite/ld-loongarch-elf/jmp_op.s | 1 + opcodes/loongarch-opc.c | 1 + 5 files changed, 5 insertions(+) diff --git a/gas/testsuite/gas/loongarch/jmp_op.d b/gas/testsuite/gas/loong= arch/jmp_op.d index b10390f640f..218c13f9398 100644 --- a/gas/testsuite/gas/loongarch/jmp_op.d +++ b/gas/testsuite/gas/loongarch/jmp_op.d @@ -28,3 +28,4 @@ Disassembly of section .text: [ ]+48:[ ]+6bffb8a4[ ]+[ ]+bltu[ ]+\$a1, \$a0, -72\(0x3ffb8\)[ ]+# 0= x0 [ ]+4c:[ ]+6fffb485[ ]+[ ]+bgeu[ ]+\$a0, \$a1, -76\(0x3ffb4\)[ ]+# 0= x0 [ ]+50:[ ]+6fffb0a4[ ]+[ ]+bgeu[ ]+\$a1, \$a0, -80\(0x3ffb0\)[ ]+# 0= x0 +[ ]+54:[ ]+4c000020[ ]+[ ]+jirl[ ]+\$zero, \$ra, 0 diff --git a/gas/testsuite/gas/loongarch/jmp_op.s b/gas/testsuite/gas/loong= arch/jmp_op.s index 1deb165aeba..56f986784e2 100644 --- a/gas/testsuite/gas/loongarch/jmp_op.s +++ b/gas/testsuite/gas/loongarch/jmp_op.s @@ -20,3 +20,4 @@ bltu $r4,$r5,.L1 bgtu $r4,$r5,.L1 bgeu $r4,$r5,.L1 bleu $r4,$r5,.L1 +ret diff --git a/ld/testsuite/ld-loongarch-elf/jmp_op.d b/ld/testsuite/ld-loong= arch-elf/jmp_op.d index b10390f640f..218c13f9398 100644 --- a/ld/testsuite/ld-loongarch-elf/jmp_op.d +++ b/ld/testsuite/ld-loongarch-elf/jmp_op.d @@ -28,3 +28,4 @@ Disassembly of section .text: [ ]+48:[ ]+6bffb8a4[ ]+[ ]+bltu[ ]+\$a1, \$a0, -72\(0x3ffb8\)[ ]+# 0= x0 [ ]+4c:[ ]+6fffb485[ ]+[ ]+bgeu[ ]+\$a0, \$a1, -76\(0x3ffb4\)[ ]+# 0= x0 [ ]+50:[ ]+6fffb0a4[ ]+[ ]+bgeu[ ]+\$a1, \$a0, -80\(0x3ffb0\)[ ]+# 0= x0 +[ ]+54:[ ]+4c000020[ ]+[ ]+jirl[ ]+\$zero, \$ra, 0 diff --git a/ld/testsuite/ld-loongarch-elf/jmp_op.s b/ld/testsuite/ld-loong= arch-elf/jmp_op.s index 1deb165aeba..56f986784e2 100644 --- a/ld/testsuite/ld-loongarch-elf/jmp_op.s +++ b/ld/testsuite/ld-loongarch-elf/jmp_op.s @@ -20,3 +20,4 @@ bltu $r4,$r5,.L1 bgtu $r4,$r5,.L1 bgeu $r4,$r5,.L1 bleu $r4,$r5,.L1 +ret diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c index 35bae8c3ed4..1b510048c29 100644 --- a/opcodes/loongarch-opc.c +++ b/opcodes/loongarch-opc.c @@ -841,6 +841,7 @@ static struct loongarch_opcode loongarch_jmp_opcodes[] = =3D { 0x0, 0x0, "bgtu", "r,r,la", "bltu %2,%1,%%b16(%3)", 0, 0, 0 }, { 0x0, 0x0, "bleu", "r,r,la", "bgeu %2,%1,%%b16(%3)", 0, 0, 0 }, { 0x0, 0x0, "jr", "r", "jirl $r0,%1,0", 0, 0, 0 }, + { 0x0, 0x0, "ret", "", "jirl $r0,$r1,0", 0, 0, 0 }, { 0 } /* Terminate the list. */ };