[binutils-gdb] ppc/svp64: support LibreSOC architecture

[Alan Modra <amodra@sourceware.org>]

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=33ae8a3ae31d8ea787d79d2a677d960721ffe682

commit 33ae8a3ae31d8ea787d79d2a677d960721ffe682
Author: Dmitry Selyutin <ghostmansd@gmail.com>
Date:   Mon Jul 25 16:10:14 2022 +0300

    ppc/svp64: support LibreSOC architecture
    
    This patch adds support for LibreSOC machine and SVP64 extension flag
    for PowerPC architecture. SV (Simple-V) is a strict RISC-paradigm
    Scalable Vector Extension for the Power ISA. SVP64 is the 64-bit
    Prefixed instruction format implementing SV. Funded by NLnet through EU
    Grants No: 825310 and 825322, SV is in DRAFT form and is to be publicly
    submitted via the OpenPOWER Foundation ISA Working Group via the
    newly-created External RFC Process.
    
    For more details, visit https://libre-soc.org.

Diff:
---
 gas/config/tc-ppc.c  |  2 ++
 include/opcode/ppc.h |  3 +++
 opcodes/ppc-dis.c    |  5 +++++
 opcodes/ppc-opc.c    | 17 +++++++++--------
 4 files changed, 19 insertions(+), 8 deletions(-)

diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
index 452fab1cbfc..ffc99857e39 100644
--- a/gas/config/tc-ppc.c
+++ b/gas/config/tc-ppc.c
@@ -1382,6 +1382,8 @@ PowerPC options:\n"));
   fprintf (stream, _("\
 -mpower10, -mpwr10      generate code for Power10 architecture\n"));
   fprintf (stream, _("\
+-mlibresoc              generate code for Libre-SOC architecture\n"));
+  fprintf (stream, _("\
 -mcell                  generate code for Cell Broadband Engine architecture\n"));
   fprintf (stream, _("\
 -mcom                   generate code for Power/PowerPC common instructions\n"));
diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h
index 7bc6ee216e1..cf72db6069d 100644
--- a/include/opcode/ppc.h
+++ b/include/opcode/ppc.h
@@ -237,6 +237,9 @@ extern const unsigned int spe2_num_opcodes;
 /* Opcode is only supported by power10 architecture.  */
 #define PPC_OPCODE_POWER10  0x400000000000ull
 
+/* Opcode is only supported by SVP64 extensions (LibreSOC architecture).  */
+#define PPC_OPCODE_SVP64    0x800000000000ull
+
 /* A macro to extract the major opcode from an instruction.  */
 #define PPC_OP(i) (((i) >> 26) & 0x3f)
 
diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c
index 7c7dde87f00..db03dce4613 100644
--- a/opcodes/ppc-dis.c
+++ b/opcodes/ppc-dis.c
@@ -200,6 +200,11 @@ struct ppc_mopt ppc_opts[] = {
 		| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
 		| PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
     0 },
+  { "libresoc",(PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
+		| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
+		| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
+		| PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX | PPC_OPCODE_SVP64),
+    0 },
   { "future",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 		| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 		| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 7637d3e349e..7ad58038319 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -4819,19 +4819,20 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
 #define PPCEFS2	PPC_OPCODE_EFS2
 #define PPCBRLK PPC_OPCODE_BRLOCK
 #define PPCPMR	PPC_OPCODE_PMR
-#define PPCTMR  PPC_OPCODE_TMR
+#define PPCTMR	PPC_OPCODE_TMR
 #define PPCCHLK PPC_OPCODE_CACHELCK
 #define PPCRFMCI PPC_OPCODE_RFMCI
-#define E500MC  PPC_OPCODE_E500MC
+#define E500MC	PPC_OPCODE_E500MC
 #define PPCA2	PPC_OPCODE_A2
-#define TITAN   PPC_OPCODE_TITAN
-#define MULHW   PPC_OPCODE_405 | PPC_OPCODE_440 | PPC_OPCODE_476 | TITAN
+#define TITAN	PPC_OPCODE_TITAN
+#define MULHW	PPC_OPCODE_405 | PPC_OPCODE_440 | PPC_OPCODE_476 | TITAN
 #define E500	PPC_OPCODE_E500
 #define E6500	PPC_OPCODE_E6500
-#define PPCVLE  PPC_OPCODE_VLE
-#define PPCHTM  PPC_OPCODE_POWER8
-#define E200Z4  PPC_OPCODE_E200Z4
-#define PPCLSP  PPC_OPCODE_LSP
+#define PPCVLE	PPC_OPCODE_VLE
+#define PPCHTM	PPC_OPCODE_POWER8
+#define E200Z4	PPC_OPCODE_E200Z4
+#define PPCLSP	PPC_OPCODE_LSP
+#define SVP64	PPC_OPCODE_SVP64
 /* Used to mark extended mnemonic in deprecated field so that -Mraw
    won't use this variant in disassembly.  */
 #define EXT	PPC_OPCODE_RAW