From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1386) id 5AD64385841A; Tue, 16 Aug 2022 07:13:31 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5AD64385841A Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Jan Beulich To: bfd-cvs@sourceware.org Subject: [binutils-gdb] x86: template-ize packed/scalar vector floating point insns X-Act-Checkin: binutils-gdb X-Git-Author: Jan Beulich X-Git-Refname: refs/heads/master X-Git-Oldrev: 33b6a20af3854e1aa144fbfca6ff98fccd0ef86d X-Git-Newrev: 73d214b268a95d06a0eff0f2347049820d1ae320 Message-Id: <20220816071331.5AD64385841A@sourceware.org> Date: Tue, 16 Aug 2022 07:13:31 +0000 (GMT) X-BeenThere: binutils-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 16 Aug 2022 07:13:31 -0000 https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D73d214b268a9= 5d06a0eff0f2347049820d1ae320 commit 73d214b268a95d06a0eff0f2347049820d1ae320 Author: Jan Beulich Date: Tue Aug 16 09:11:59 2022 +0200 x86: template-ize packed/scalar vector floating point insns =20 The vast majority of vector FP insns comes in single/double pairs. Many pairs follow certain encoding patterns. Introduce an "sd" template to reduce redundancy. Similarly, to further cover similarities between AVX512F and AVX512-FP16, introduce an "sdh" template. =20 For element-size Disp8 shift generalize i386-gen's broadcast size determination, allowing Disp8MemShift to be specified without an operand in the affected templated templates. While doing the adjustment also eliminate an unhelpful (lost information) diagnostic combined with a use after free in what is now get_element_size(). =20 Note that in the course of the conversion - the AVX512F form of VMOVUPD has a stray (leftover) Load attribute dropped, - VMOVSH has a benign IgnoreSize added (the attribute is still strictly necessary for VMOVSD, and necessary for VMOVSS as long as we permit strange combinations like "-march=3Di286+avx"), - VFPCLASSPH is properly split to separate AT&T and Intel syntax forms, matching VFPCLASSP{S,D}. Diff: --- opcodes/i386-gen.c | 43 +- opcodes/i386-opc.tbl | 593 +--- opcodes/i386-tbl.h | 8746 +++++++++++++++++++++++++---------------------= ---- 3 files changed, 4575 insertions(+), 4807 deletions(-) diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index eaeb207e444..181ea53b7ab 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -1111,18 +1111,21 @@ output_opcode_modifier (FILE *table, bitfield *modi= fier, unsigned int size) fprintf (table, "%d },\n", modifier[i].value); } =20 +/* Returns LOG2 of element size. */ static int -adjust_broadcast_modifier (char **opnd) +get_element_size (char **opnd, int lineno) { char *str, *next, *last, *op; - int bcst_type =3D INT_MAX; + const char *full =3D opnd[0]; + int elem_size =3D INT_MAX; =20 - /* Skip the immediate operand. */ - op =3D opnd[0]; - if (strcasecmp(op, "Imm8") =3D=3D 0) - op =3D opnd[1]; + /* Find the memory operand. */ + while (full !=3D NULL && strstr(full, "BaseIndex") =3D=3D NULL) + full =3D *++opnd; + if (full =3D=3D NULL) + fail (_("%s: %d: no memory operand\n"), filename, lineno); =20 - op =3D xstrdup (op); + op =3D xstrdup (full); last =3D op + strlen (op); for (next =3D op; next && next < last; ) { @@ -1131,34 +1134,34 @@ adjust_broadcast_modifier (char **opnd) { if (strcasecmp(str, "Byte") =3D=3D 0) { - /* The smalest broadcast type, no need to check + /* The smallest element size, no need to check further. */ - bcst_type =3D BYTE_BROADCAST; + elem_size =3D 0; break; } else if (strcasecmp(str, "Word") =3D=3D 0) { - if (bcst_type > WORD_BROADCAST) - bcst_type =3D WORD_BROADCAST; + if (elem_size > 1) + elem_size =3D 1; } else if (strcasecmp(str, "Dword") =3D=3D 0) { - if (bcst_type > DWORD_BROADCAST) - bcst_type =3D DWORD_BROADCAST; + if (elem_size > 2) + elem_size =3D 2; } else if (strcasecmp(str, "Qword") =3D=3D 0) { - if (bcst_type > QWORD_BROADCAST) - bcst_type =3D QWORD_BROADCAST; + if (elem_size > 3) + elem_size =3D 3; } } } free (op); =20 - if (bcst_type =3D=3D INT_MAX) - fail (_("unknown broadcast operand: %s\n"), op); + if (elem_size =3D=3D INT_MAX) + fail (_("%s: %d: unknown element size: %s\n"), filename, lineno, full); =20 - return bcst_type; + return elem_size; } =20 static void @@ -1185,7 +1188,9 @@ process_i386_opcode_modifier (FILE *table, char *mod,= unsigned int space, { int val =3D 1; if (strcasecmp(str, "Broadcast") =3D=3D 0) - val =3D adjust_broadcast_modifier (opnd); + val =3D get_element_size (opnd, lineno) + BYTE_BROADCAST; + else if (strcasecmp(str, "Disp8MemShift") =3D=3D 0) + val =3D get_element_size (opnd, lineno); =20 set_bitfield (str, modifiers, val, ARRAY_SIZE (modifiers), lineno); diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 12779e651d7..d894056ebbd 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -1339,19 +1339,14 @@ pabsd, 0x0f381e, None, , Modrm||No_bSuf // SSE4.1 instructions. =20 - -blendpd, 0x660f3a0d, None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspe= cified|BaseIndex, RegXMM } -blendps, 0x660f3a0c, None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspe= cified|BaseIndex, RegXMM } -blendvpd, 0x664b, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=3D1|VexW=3D1|V= exSources=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { A= cc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } -blendvpd, 0x664b, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=3D1|VexW=3D1|V= exSources=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Implicit1stX= mm0|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM } -blendvpd, 0x660f3815, None, CpuSSE4_1, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } -blendvpd, 0x660f3815, None, CpuSSE4_1, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -blendvps, 0x664a, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=3D1|VexW=3D1|V= exSources=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { A= cc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } -blendvps, 0x664a, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=3D1|VexW=3D1|V= exSources=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Implicit1stX= mm0|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM } -blendvps, 0x660f3814, None, CpuSSE4_1, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } -blendvps, 0x660f3814, None, CpuSSE4_1, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -dppd, 0x660f3a41, None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecif= ied|BaseIndex, RegXMM } -dpps, 0x660f3a40, None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecif= ied|BaseIndex, RegXMM } + + +blendp, 0x660f3a0c | , None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8= , RegXMM|Unspecified|BaseIndex, RegXMM } +blendvp, 0x664a | , None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV= =3D1|VexW=3D1|VexSources=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS= uf|SSE2AVX, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } +blendvp, 0x664a | , None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV= =3D1|VexW=3D1|VexSources=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS= uf|Implicit1stXmm0|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM } +blendvp, 0x660f3814 | , None, CpuSSE4_1, Modrm|No_bSuf|No_wSuf= |No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Acc|Xmmword, RegXMM|Unspecified|BaseIn= dex, RegXMM } +blendvp, 0x660f3814 | , None, CpuSSE4_1, Modrm|No_bSuf|No_wSuf= |No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +dpp, 0x660f3a40 | , None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, R= egXMM|Unspecified|BaseIndex, RegXMM } extractps, 0x6617, None, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|IgnoreSize|No_= bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM, Reg3= 2|Dword|Unspecified|BaseIndex } extractps, 0x6617, None, CpuAVX|Cpu64, RegMem|Vex|Space0F3A|VexWIG|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM, Reg64 } extractps, 0x660f3a17, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|N= o_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|Ba= seIndex } @@ -1402,10 +1397,8 @@ pmovzxdq, 0x660f3835, None, , Modr= m||No_bSuf|No_wS pmuldq, 0x660f3828, None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|= BaseIndex, RegXMM } pmulld, 0x660f3840, None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|= BaseIndex, RegXMM } ptest, 0x660f3817, None, , Modrm||No_bSuf|No= _wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, Reg= XMM } -roundpd, 0x660f3a09, None, , Modrm||No_bSuf|= No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIn= dex, RegXMM } -roundps, 0x660f3a08, None, , Modrm||No_bSuf|= No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIn= dex, RegXMM } -roundsd, 0x660f3a0b, None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, Qwor= d|Unspecified|BaseIndex|RegXMM, RegXMM } -roundss, 0x660f3a0a, None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IgnoreSize, { Imm8, D= word|Unspecified|BaseIndex|RegXMM, RegXMM } +roundp, 0x660f3a08 | , None, , Modrm||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unsp= ecified|BaseIndex, RegXMM } +rounds, 0x660f3a0a | , None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|, { Imm8, |Unspecified|BaseIndex|RegXMM, RegXMM } =20 // SSE4.2 instructions. =20 @@ -1484,33 +1477,22 @@ gf2p8mulb, 0x660f38cf, None, CpuGFN= I, Modrm||No_bSuf|No nge_uq:19:, ngt_uq:1a:, false_os:1b:C, neq_os:1c:C, ge_oq:1d:, gt_oq:1= e:, + true_us:1f:C> =20 -vaddpd, 0x6658, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|CheckRe= gSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseI= ndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vaddps, 0x58, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|CheckRegS= ize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseInd= ex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vaddsd, 0xf258, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Re= gXMM, RegXMM, RegXMM } -vaddss, 0xf358, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Re= gXMM, RegXMM, RegXMM } +vaddp, 0x58, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|C= heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified= |BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vadds, 0x58, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexWI= G|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { |Unspecified= |BaseIndex|RegXMM, RegXMM, RegXMM } vaddsubpd, 0x66d0, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|Chec= kRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|Ba= seIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vaddsubps, 0xf2d0, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|Chec= kRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|Ba= seIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vandnpd, 0x6655, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|CheckR= egSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Unspeci= fied|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vandnps, 0x55, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|CheckReg= Size|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Unspecifi= ed|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vandpd, 0x6654, None, CpuAVX, Modrm|C|Vex|Space0F|VexVVVV=3D1|VexWIG|Check= RegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|Bas= eIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vandps, 0x54, None, CpuAVX, Modrm|C|Vex|Space0F|VexVVVV=3D1|VexWIG|CheckRe= gSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseI= ndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vblendpd, 0x660d, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=3D1|VexWIG|Che= ckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspeci= fied|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vblendps, 0x660c, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=3D1|VexWIG|Che= ckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspeci= fied|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vblendvpd, 0x664b, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=3D1|VexW=3D1|= VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSu= f, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, Reg= XMM|RegYMM } -vblendvps, 0x664a, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=3D1|VexW=3D1|= VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSu= f, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, Reg= XMM|RegYMM } +vandnp, 0x55, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|= CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { U= nspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vandp, 0x54, None, CpuAVX, Modrm|C|Vex|Space0F|VexVVVV|VexWIG= |CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifi= ed|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vblendp, 0x660c | , None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV|= VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm= 8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vblendvp, 0x664a | , None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV= |VexW0|VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|= No_ldSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegY= MM, RegXMM|RegYMM } vbroadcastf128, 0x661a, None, CpuAVX, Modrm|Vex=3D2|Space0F38|VexW=3D1|No_= bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIn= dex, RegYMM } vbroadcastsd, 0x6619, None, CpuAVX, Modrm|Vex=3D2|Space0F38|VexW=3D1|Ignor= eSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified= |BaseIndex, RegYMM } vbroadcastss, 0x6618, None, CpuAVX, Modrm|Vex|Space0F38|VexW=3D1|IgnoreSiz= e|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|Bas= eIndex, RegXMM|RegYMM } -vcmppd, 0x66c2, 0x, CpuAVX, Modrm||= Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_= qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM,= RegXMM|RegYMM } -vcmpps, 0xc2, 0x, CpuAVX, Modrm||Ve= x|Space0F|VexVVVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS= uf|No_ldSuf|ImmExt, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, R= egXMM|RegYMM } -vcmpsd, 0xf2c2, 0x, CpuAVX, Modrm||= VexLIG|Space0F|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld= Suf|ImmExt, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM } -vcmpss, 0xf3c2, 0x, CpuAVX, Modrm||= VexLIG|Space0F|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld= Suf|ImmExt, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } -vcmppd, 0x66c2, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|CheckRe= gSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified= |BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vcmpps, 0xc2, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|CheckRegS= ize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|B= aseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vcmpsd, 0xf2c2, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Qword|Unspecified|BaseIn= dex|RegXMM, RegXMM, RegXMM } -vcmpss, 0xf3c2, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|Unspecified|BaseIn= dex|RegXMM, RegXMM, RegXMM } -vcomisd, 0x662f, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexWIG|No_bSuf|No_wSu= f|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, R= egXMM } -vcomiss, 0x2f, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexWIG|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, Reg= XMM } +vcmpp, 0xc2, 0x, CpuAVX, Modrm||Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|Unspecified|BaseIndex, RegX= MM|RegYMM, RegXMM|RegYMM } +vcmps, 0xc2, 0x, CpuAVX, Modrm||VexLIG|Space0F|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_= qSuf|No_ldSuf|ImmExt, { RegXMM||Unspecified|BaseIndex, RegXMM, Reg= XMM } +vcmpp, 0xc2, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|C= heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspe= cified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vcmps, 0xc2, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexWI= G|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, |Unspe= cified|BaseIndex|RegXMM, RegXMM, RegXMM } +vcomis, 0x2f, None, CpuAVX, Modrm|VexLIG|Space0F|VexWIG|No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { |Unspecified|BaseIn= dex|RegXMM, RegXMM } vcvtdq2pd, 0xf3e6, None, CpuAVX, Modrm|Vex128|Space0F|VexWIG|No_bSuf|No_wS= uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, = RegXMM } vcvtdq2pd, 0xf3e6, None, CpuAVX, Modrm|Vex256|Space0F|VexWIG|No_bSuf|No_wS= uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegYMM= } vcvtdq2ps, 0x5b, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM= |RegYMM, RegXMM|RegYMM } @@ -1527,10 +1509,8 @@ vcvtps2pd, 0x5a, None, CpuAVX, Modrm|Vex128|Space0F|= VexWIG|No_bSuf|No_wSuf|No_lS vcvtps2pd, 0x5a, None, CpuAVX, Modrm|Vex256|Space0F|VexWIG|No_bSuf|No_wSuf= |No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } vcvtsd2si, 0xf22d, None, CpuAVX, Modrm|Vex=3D3|Space0F|IgnoreSize|No_bSuf|= No_wSuf|No_sSuf|No_ldSuf|ToDword, { Qword|Unspecified|BaseIndex|RegXMM, Reg= 32|Reg64 } vcvtsd2ss, 0xf25a, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No_b= Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex= |RegXMM, RegXMM, RegXMM } -vcvtsi2sd, 0xf22a, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|IgnoreSize|N= o_bSuf|No_wSuf|No_sSuf|No_ldSuf|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIn= dex, RegXMM, RegXMM } -vcvtsi2sd, 0xf22a, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|No_bSuf|No_w= Suf|No_sSuf|No_ldSuf|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegX= MM, RegXMM } -vcvtsi2ss, 0xf32a, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|IgnoreSize|N= o_bSuf|No_wSuf|No_sSuf|No_ldSuf|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIn= dex, RegXMM, RegXMM } -vcvtsi2ss, 0xf32a, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|No_bSuf|No_w= Suf|No_sSuf|No_ldSuf|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegX= MM, RegXMM } +vcvtsi2s, 0x2a, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|Ig= noreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ATTSyntax, { Reg32|Reg64|Unspecif= ied|BaseIndex, RegXMM, RegXMM } +vcvtsi2s, 0x2a, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|No= _bSuf|No_wSuf|No_sSuf|No_ldSuf|IntelSyntax, { Reg32|Reg64|Unspecified|BaseI= ndex, RegXMM, RegXMM } vcvtss2sd, 0xf35a, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No_b= Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex= |RegXMM, RegXMM, RegXMM } vcvtss2si, 0xf32d, None, CpuAVX, Modrm|Vex=3D3|Space0F|No_bSuf|No_wSuf|No_= sSuf|No_ldSuf|ToQword, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } vcvttpd2dq, 0x66e6, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wSuf= |No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { RegXMM|RegYMM|Unspecified|= BaseIndex, RegXMM } @@ -1540,10 +1520,8 @@ vcvttpd2dqy, 0x66e6, None, CpuAVX, Modrm|Vex=3D2|Spa= ce0F|VexWIG|No_bSuf|No_wSuf|No vcvttps2dq, 0xf35b, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wSuf= |No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, R= egXMM|RegYMM } vcvttsd2si, 0xf22c, None, CpuAVX, Modrm|Vex=3D3|Space0F|IgnoreSize|No_bSuf= |No_wSuf|No_sSuf|No_ldSuf|ToDword, { Qword|Unspecified|BaseIndex|RegXMM, Re= g32|Reg64 } vcvttss2si, 0xf32c, None, CpuAVX, Modrm|Vex=3D3|Space0F|No_bSuf|No_wSuf|No= _sSuf|No_ldSuf|ToQword, { Dword|Unspecified|BaseIndex|RegXMM, Reg32|Reg64 } -vdivpd, 0x665e, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|CheckRe= gSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseI= ndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vdivps, 0x5e, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|CheckRegS= ize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseInd= ex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vdivsd, 0xf25e, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Re= gXMM, RegXMM, RegXMM } -vdivss, 0xf35e, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Re= gXMM, RegXMM, RegXMM } +vdivp, 0x5e, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|C= heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified= |BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vdivs, 0x5e, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexWI= G|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { |Unspecified= |BaseIndex|RegXMM, RegXMM, RegXMM } vdppd, 0x6641, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=3D1|VexWIG|No_bSu= f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|R= egXMM, RegXMM, RegXMM } vdpps, 0x6640, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=3D1|VexWIG|CheckR= egSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecifie= d|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vextractf128, 0x6619, None, CpuAVX, Modrm|Vex=3D2|Space0F3A|VexW=3D1|No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, Unspecified|Ba= seIndex|RegXMM } @@ -1558,20 +1536,13 @@ vinsertps, 0x6621, None, CpuAVX, Modrm|Vex|Space0F3= A|VexVVVV|VexWIG|No_bSuf|No_w vlddqu, 0xf2f0, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|No_bSu= f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Ymmword|Unspecified|B= aseIndex, RegXMM|RegYMM } vldmxcsr, 0xae, 2, CpuAVX, Modrm|Vex128|Space0F|VexWIG|IgnoreSize|No_bSuf|= No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex } vmaskmovdqu, 0x66f7, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wSu= f|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM } -vmaskmovpd, 0x662f, None, CpuAVX, Modrm|Vex|Space0F38|VexVVVV=3D1|VexW=3D1= |CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Re= gYMM, RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex } -vmaskmovpd, 0x662d, None, CpuAVX, Modrm|Vex|Space0F38|VexVVVV=3D1|VexW=3D1= |CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Y= mmword|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } -vmaskmovps, 0x662e, None, CpuAVX, Modrm|Vex|Space0F38|VexVVVV=3D1|VexW=3D1= |CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Re= gYMM, RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex } -vmaskmovps, 0x662c, None, CpuAVX, Modrm|Vex|Space0F38|VexVVVV=3D1|VexW=3D1= |CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Y= mmword|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } -vmaxpd, 0x665f, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|CheckRe= gSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseI= ndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vmaxps, 0x5f, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|CheckRegS= ize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseInd= ex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vmaxsd, 0xf25f, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Re= gXMM, RegXMM, RegXMM } -vmaxss, 0xf35f, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Re= gXMM, RegXMM, RegXMM } -vminpd, 0x665d, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|CheckRe= gSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseI= ndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vminps, 0x5d, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|CheckRegS= ize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseInd= ex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vminsd, 0xf25d, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Re= gXMM, RegXMM, RegXMM } -vminss, 0xf35d, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Re= gXMM, RegXMM, RegXMM } -vmovapd, 0x6628, None, CpuAVX, D|Modrm|Vex|Space0F|VexWIG|CheckRegSize|No_= bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegX= MM|RegYMM, RegXMM|RegYMM } -vmovaps, 0x28, None, CpuAVX, D|Modrm|Vex|Space0F|VexWIG|CheckRegSize|No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM= |RegYMM, RegXMM|RegYMM } +vmaskmovp, 0x662e | , None, CpuAVX, Modrm|Vex|Space0F38|VexVVV= V|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Re= gXMM|RegYMM, RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex } +vmaskmovp, 0x662c | , None, CpuAVX, Modrm|Vex|Space0F38|VexVVV= V|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xm= mword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } +vmaxp, 0x5f, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|C= heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified= |BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vmaxs, 0x5f, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexWI= G|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { |Unspecified= |BaseIndex|RegXMM, RegXMM, RegXMM } +vminp, 0x5d, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|C= heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified= |BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vmins, 0x5d, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexWI= G|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { |Unspecified= |BaseIndex|RegXMM, RegXMM, RegXMM } +vmovap, 0x28, None, CpuAVX, D|Modrm|Vex|Space0F|VexWIG|CheckR= egSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|Base= Index|RegXMM|RegYMM, RegXMM|RegYMM } // vmovd really shouldn't allow for 64bit operand (vmovq is the right // mnemonic for copying between Reg64/Mem64 and RegXMM, as is mandated // by Intel AVX spec). To avoid extra template in gcc x86 backend and @@ -1584,39 +1555,27 @@ vmovddup, 0xf212, None, CpuAVX, Modrm|Vex=3D2|Space= 0F|VexWIG|No_bSuf|No_wSuf|No_lS vmovdqa, 0x666f, None, CpuAVX, D|Modrm|Vex|Space0F|VexWIG|CheckRegSize|No_= bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegX= MM|RegYMM, RegXMM|RegYMM } vmovdqu, 0xf36f, None, CpuAVX, D|Modrm|Vex|Space0F|VexWIG|CheckRegSize|No_= bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegX= MM|RegYMM, RegXMM|RegYMM } vmovhlps, 0x12, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM } -vmovhpd, 0x6616, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|Ignore= Size|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|= BaseIndex, RegXMM, RegXMM } -vmovhpd, 0x6617, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|IgnoreSize|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|Base= Index } -vmovhps, 0x16, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|IgnoreSi= ze|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|Ba= seIndex, RegXMM, RegXMM } -vmovhps, 0x17, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|IgnoreSize|No_bSuf|N= o_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIn= dex } +vmovhp, 0x16, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|= IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspec= ified|BaseIndex, RegXMM, RegXMM } +vmovhp, 0x17, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|IgnoreSi= ze|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspec= ified|BaseIndex } vmovlhps, 0x16, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM } -vmovlpd, 0x6612, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|Ignore= Size|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|= BaseIndex, RegXMM, RegXMM } -vmovlpd, 0x6613, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|IgnoreSize|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|Base= Index } -vmovlps, 0x12, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|IgnoreSi= ze|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|Ba= seIndex, RegXMM, RegXMM } -vmovlps, 0x13, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|IgnoreSize|No_bSuf|N= o_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIn= dex } -vmovmskpd, 0x6650, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wSuf|= No_sSuf|No_ldSuf, { RegXMM|RegYMM, Reg32|Reg64 } -vmovmskps, 0x50, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wSuf|No= _sSuf|No_ldSuf, { RegXMM|RegYMM, Reg32|Reg64 } +vmovlp, 0x12, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|= IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspec= ified|BaseIndex, RegXMM, RegXMM } +vmovlp, 0x13, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|IgnoreSi= ze|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspec= ified|BaseIndex } +vmovmskp, 0x50, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|No_bSu= f|No_wSuf|No_sSuf|No_ldSuf, { RegXMM|RegYMM, Reg32|Reg64 } vmovntdq, 0x66e7, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|No_b= Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Xmmword|Ymmw= ord|Unspecified|BaseIndex } vmovntdqa, 0x662a, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexWIG|CheckR= egSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Ymmword|= Unspecified|BaseIndex, RegXMM|RegYMM } -vmovntpd, 0x662b, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|No_b= Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Xmmword|Ymmw= ord|Unspecified|BaseIndex } -vmovntps, 0x2b, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|No_bSu= f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Xmmword|Ymmwor= d|Unspecified|BaseIndex } +vmovntp, 0x2b, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRe= gSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Xm= mword|Ymmword|Unspecified|BaseIndex } vmovq, 0xf37e, None, CpuAVX, Load|Modrm|Vex=3D1|Space0F|VexWIG|No_bSuf|No_= wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM= , RegXMM } vmovq, 0x66d6, None, CpuAVX, Modrm|Vex=3D1|Space0F|VexWIG|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Reg= XMM } vmovq, 0x666e, None, CpuAVX|Cpu64, D|Modrm|Vex=3D1|Space0F|VexW=3D2|Ignore= Size|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|Unspe= cified|BaseIndex, RegXMM } -vmovsd, 0xf210, None, CpuAVX, D|Modrm|Vex=3D3|Space0F|VexWIG|IgnoreSize|No= _bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseInd= ex, RegXMM } -vmovsd, 0xf210, None, CpuAVX, D|Modrm|Vex=3D3|Space0F|VexVVVV=3D1|VexWIG|N= o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM } +vmovs, 0x10, None, CpuAVX, D|Modrm|VexLIG|Space0F|VexWIG|Igno= reSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { |Unspec= ified|BaseIndex, RegXMM } +vmovs, 0x10, None, CpuAVX, D|Modrm|VexLIG|Space0F|VexVVVV|Vex= WIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, Reg= XMM } vmovshdup, 0xf316, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|No_= bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegX= MM|RegYMM, RegXMM|RegYMM } vmovsldup, 0xf312, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|No_= bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegX= MM|RegYMM, RegXMM|RegYMM } -vmovss, 0xf310, None, CpuAVX, D|Modrm|Vex=3D3|Space0F|VexWIG|IgnoreSize|No= _bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseInd= ex, RegXMM } -vmovss, 0xf310, None, CpuAVX, D|Modrm|Vex=3D3|Space0F|VexVVVV=3D1|VexWIG|N= o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM } -vmovupd, 0x6610, None, CpuAVX, D|Modrm|Vex|Space0F|VexWIG|CheckRegSize|No_= bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegX= MM|RegYMM, RegXMM|RegYMM } -vmovups, 0x10, None, CpuAVX, D|Modrm|Vex|Space0F|VexWIG|CheckRegSize|No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM= |RegYMM, RegXMM|RegYMM } +vmovup, 0x10, None, CpuAVX, D|Modrm|Vex|Space0F|VexWIG|CheckR= egSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|Base= Index|RegXMM|RegYMM, RegXMM|RegYMM } vmpsadbw, 0x6642, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F3A|VexVVVV|VexWIG= |CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Uns= pecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vmulpd, 0x6659, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|CheckRe= gSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseI= ndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vmulps, 0x59, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|CheckRegS= ize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseInd= ex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vmulsd, 0xf259, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Re= gXMM, RegXMM, RegXMM } -vmulss, 0xf359, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Re= gXMM, RegXMM, RegXMM } -vorpd, 0x6656, None, CpuAVX, Modrm|C|Vex|Space0F|VexVVVV=3D1|VexWIG|CheckR= egSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|Base= Index|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vorps, 0x56, None, CpuAVX, Modrm|C|Vex|Space0F|VexVVVV=3D1|VexWIG|CheckReg= Size|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIn= dex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vmulp, 0x59, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|C= heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified= |BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vmuls, 0x59, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexWI= G|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { |Unspecified= |BaseIndex|RegXMM, RegXMM, RegXMM } +vorp, 0x56, None, CpuAVX, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|= CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifie= d|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vpabsb, 0x661c, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexWIG|CheckRegS= ize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseInd= ex|RegXMM|RegYMM, RegXMM|RegYMM } vpabsd, 0x661e, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexWIG|CheckRegS= ize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseInd= ex|RegXMM|RegYMM, RegXMM|RegYMM } vpabsw, 0x661d, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexWIG|CheckRegS= ize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseInd= ex|RegXMM|RegYMM, RegXMM|RegYMM } @@ -1654,10 +1613,8 @@ vpcmpgtw, 0x6665, None, CpuAVX|CpuAVX2, Modrm|Vex|Sp= ace0F|VexVVVV|VexWIG|CheckRe vpcmpistri, 0x6663, None, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|No_bSuf|No_wS= uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM, = RegXMM } vpcmpistrm, 0x6662, None, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|No_bSuf|No_wS= uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM, = RegXMM } vperm2f128, 0x6606, None, CpuAVX, Modrm|Vex=3D2|Space0F3A|VexVVVV=3D1|VexW= =3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|= BaseIndex|RegYMM, RegYMM, RegYMM } -vpermilpd, 0x660d, None, CpuAVX, Modrm|Vex|Space0F38|VexVVVV=3D1|VexW=3D1|= CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifie= d|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpermilpd, 0x6605, None, CpuAVX, Modrm|Vex|Space0F3A|VexW=3D1|CheckRegSize= |No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|Base= Index|RegXMM|RegYMM, RegXMM|RegYMM } -vpermilps, 0x660c, None, CpuAVX, Modrm|Vex|Space0F38|VexVVVV=3D1|VexW=3D1|= CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifie= d|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpermilps, 0x6604, None, CpuAVX, Modrm|Vex|Space0F3A|VexW=3D1|CheckRegSize= |No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|Base= Index|RegXMM|RegYMM, RegXMM|RegYMM } +vpermilp, 0x660c | , None, CpuAVX, Modrm|Vex|Space0F38|VexVVVV= |VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Uns= pecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpermilp, 0x6604 | , None, CpuAVX, Modrm|Vex|Space0F3A|VexW0|C= heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspe= cified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } vpextrb, 0x6614, None, CpuAVX, RegMem|Vex|Space0F3A|VexWIG|No_bSuf|No_wSuf= |No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64 } vpextrb, 0x6614, None, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Byte|Unspecified|BaseInde= x } vpextrd, 0x6616, None, CpuAVX, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_w= Suf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspecifi= ed|BaseIndex } @@ -1759,33 +1716,21 @@ vpunpcklwd, 0x6661, None, CpuAVX|CpuAVX2, Modrm|Vex= |Space0F|VexVVVV|VexWIG|Check vpxor, 0x66ef, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|Ch= eckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Uns= pecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vrcpps, 0x53, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|No_bSuf|= No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|Re= gYMM, RegXMM|RegYMM } vrcpss, 0xf353, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Re= gXMM, RegXMM, RegXMM } -vroundpd, 0x6609, None, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|CheckRegSize|No= _bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseInd= ex|RegXMM|RegYMM, RegXMM|RegYMM } -vroundps, 0x6608, None, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|CheckRegSize|No= _bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseInd= ex|RegXMM|RegYMM, RegXMM|RegYMM } -vroundsd, 0x660b, None, CpuAVX, Modrm|Vex=3D3|Space0F3A|VexVVVV|VexWIG|No_= bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Qword|Unspecified|Ba= seIndex|RegXMM, RegXMM, RegXMM } -vroundss, 0x660a, None, CpuAVX, Modrm|Vex=3D3|Space0F3A|VexVVVV|VexWIG|No_= bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|Unspecified|Ba= seIndex|RegXMM, RegXMM, RegXMM } +vroundp, 0x6608 | , None, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|C= heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspe= cified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vrounds, 0x660a | , None, CpuAVX, Modrm|VexLIG|Space0F3A|VexVV= VV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } vrsqrtps, 0x52, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|No_bSu= f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|= RegYMM, RegXMM|RegYMM } vrsqrtss, 0xf352, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|= RegXMM, RegXMM, RegXMM } -vshufpd, 0x66c6, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|CheckR= egSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecifie= d|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vshufps, 0xc6, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|CheckReg= Size|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|= BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vsqrtpd, 0x6651, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM= |RegYMM, RegXMM|RegYMM } -vsqrtps, 0x51, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckRegSize|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|R= egYMM, RegXMM|RegYMM } -vsqrtsd, 0xf251, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No_bSu= f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|R= egXMM, RegXMM, RegXMM } -vsqrtss, 0xf351, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No_bSu= f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|R= egXMM, RegXMM, RegXMM } +vshufp, 0xc6, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|= CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unsp= ecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vsqrtp, 0x51, None, CpuAVX, Modrm|Vex|Space0F|VexWIG|CheckReg= Size|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIn= dex|RegXMM|RegYMM, RegXMM|RegYMM } +vsqrts, 0x51, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexW= IG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { |Unspecifie= d|BaseIndex|RegXMM, RegXMM, RegXMM } vstmxcsr, 0xae, 3, CpuAVX, Modrm|Vex128|Space0F|VexWIG|IgnoreSize|No_bSuf|= No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex } -vsubpd, 0x665c, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|CheckRe= gSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseI= ndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vsubps, 0x5c, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|CheckRegS= ize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseInd= ex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vsubsd, 0xf25c, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Re= gXMM, RegXMM, RegXMM } -vsubss, 0xf35c, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexVVVV|VexWIG|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Re= gXMM, RegXMM, RegXMM } -vtestpd, 0x660f, None, CpuAVX, Modrm|Vex|Space0F38|VexW=3D1|CheckRegSize|N= o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|Re= gXMM|RegYMM, RegXMM|RegYMM } -vtestps, 0x660e, None, CpuAVX, Modrm|Vex|Space0F38|VexW=3D1|CheckRegSize|N= o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|Re= gXMM|RegYMM, RegXMM|RegYMM } -vucomisd, 0x662e, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexWIG|No_bSuf|No_wS= uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, = RegXMM } -vucomiss, 0x2e, None, CpuAVX, Modrm|Vex=3D3|Space0F|VexWIG|No_bSuf|No_wSuf= |No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, Re= gXMM } -vunpckhpd, 0x6615, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|Chec= kRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|Ba= seIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vunpckhps, 0x15, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|CheckR= egSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|Base= Index|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vunpcklpd, 0x6614, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|Chec= kRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|Ba= seIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vunpcklps, 0x14, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|CheckR= egSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|Base= Index|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vxorpd, 0x6657, None, CpuAVX, Modrm|C|Vex|Space0F|VexVVVV=3D1|VexWIG|Check= RegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Unspec= ified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vxorps, 0x57, None, CpuAVX, Modrm|C|Vex|Space0F|VexVVVV=3D1|VexWIG|CheckRe= gSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Unspecif= ied|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vsubp, 0x5c, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|C= heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified= |BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vsubs, 0x5c, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexWI= G|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { |Unspecified= |BaseIndex|RegXMM, RegXMM, RegXMM } +vtestp, 0x660e | , None, CpuAVX, Modrm|Vex|Space0F38|VexW0|Che= ckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|B= aseIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vucomis, 0x2e, None, CpuAVX, Modrm|VexLIG|Space0F|VexWIG|No_b= Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { |Unspecified|BaseI= ndex|RegXMM, RegXMM } +vunpckhp, 0x15, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWI= G|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecif= ied|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vunpcklp, 0x14, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWI= G|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecif= ied|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vxorp, 0x57, None, CpuAVX, Modrm|C|Vex|Space0F|VexVVVV|VexWIG= |CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { = Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vzeroall, 0x77, None, CpuAVX, Vex=3D2|Space0F|VexWIG|No_bSuf|No_wSuf|No_lS= uf|No_sSuf|No_qSuf|No_ldSuf, {} vzeroupper, 0x77, None, CpuAVX, Vex|Space0F|VexWIG|No_bSuf|No_wSuf|No_lSuf= |No_sSuf|No_qSuf|No_ldSuf, {} =20 @@ -1835,9 +1780,8 @@ vpsrlvq, 0x6645, None, CpuAVX2, Modrm|Vex|Space0F38|V= exVVVV=3D1|VexW=3D2|CheckRegSiz vgatherdpd, 0x6692, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW1|Check= RegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXM= M|RegYMM, Qword|Unspecified|BaseIndex, RegXMM|RegYMM } vgatherdps, 0x6692, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW0|No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM, Dword|Unsp= ecified|BaseIndex, RegXMM } vgatherdps, 0x6692, None, CpuAVX2, Modrm|Vex=3D2|Space0F38|VexVVVV|VexW0|N= o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB256, { RegYMM, Dword|= Unspecified|BaseIndex, RegYMM } -vgatherqpd, 0x6693, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW1|No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM, Qword|Unsp= ecified|BaseIndex, RegXMM } +vgatherqp, 0x6693, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM, |Unspecified|BaseIndex, RegXMM } vgatherqpd, 0x6693, None, CpuAVX2, Modrm|Vex=3D2|Space0F38|VexVVVV|VexW1|N= o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB256, { RegYMM, Qword|= Unspecified|BaseIndex, RegYMM } -vgatherqps, 0x6693, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW0|No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM, Dword|Unsp= ecified|BaseIndex, RegXMM } vgatherqps, 0x6693, None, CpuAVX2, Modrm|Vex=3D2|Space0F38|VexVVVV|VexW0|N= o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB256, { RegXMM, Dword|= Unspecified|BaseIndex, RegXMM } vpgatherdd, 0x6690, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW0|No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM, Dword|Unsp= ecified|BaseIndex, RegXMM } vpgatherdd, 0x6690, None, CpuAVX2, Modrm|Vex=3D2|Space0F38|VexVVVV|VexW0|N= o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB256, { RegYMM, Dword|= Unspecified|BaseIndex, RegYMM } @@ -1886,26 +1830,16 @@ vcvtps2ph, 0x661d, None, CpuF16C, Modrm|Vex=3D2|Spa= ce0F3A|VexW=3D1|No_bSuf|No_wSuf|N =20 =20 -vfmaddpd, 0x6688 | 0x, None, CpuFMA, Modrm|Vex|Space0F38|Vex= VVVV|VexW1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {= Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfmaddps, 0x6688 | 0x, None, CpuFMA, Modrm|Vex|Space0F38|Vex= VVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {= Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfmaddsd, 0x6689 | 0x, None, CpuFMA, Modrm|VexLIG|Space0F38|= VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Uns= pecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vfmaddss, 0x6689 | 0x, None, CpuFMA, Modrm|VexLIG|Space0F38|= VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Uns= pecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vfmaddsubpd, 0x6686 | 0x, None, CpuFMA, Modrm|Vex|Space0F38|= VexVVVV|VexW1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf= , { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfmaddsubps, 0x6686 | 0x, None, CpuFMA, Modrm|Vex|Space0F38|= VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf= , { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfmsubpd, 0x668a | 0x, None, CpuFMA, Modrm|Vex|Space0F38|Vex= VVVV|VexW1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {= Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfmsubps, 0x668a | 0x, None, CpuFMA, Modrm|Vex|Space0F38|Vex= VVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {= Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfmsubsd, 0x668b | 0x, None, CpuFMA, Modrm|VexLIG|Space0F38|= VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Uns= pecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vfmsubss, 0x668b | 0x, None, CpuFMA, Modrm|VexLIG|Space0F38|= VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Uns= pecified|BaseIndex|RegXMM, RegXMM, RegXMM } -vfmsubaddpd, 0x6687 | 0x, None, CpuFMA, Modrm|Vex|Space0F38|= VexVVVV|VexW1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf= , { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfmsubaddps, 0x6687 | 0x, None, CpuFMA, Modrm|Vex|Space0F38|= VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf= , { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfnmaddpd, 0x668c | 0x, None, CpuFMA, Modrm|Vex|Space0F38|Ve= xVVVV|VexW1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, = { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfnmaddps, 0x668c | 0x, None, CpuFMA, Modrm|Vex|Space0F38|Ve= xVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, = { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfnmaddsd, 0x668d | 0x, None, CpuFMA, Modrm|VexLIG|Space0F38= |VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Un= specified|BaseIndex|RegXMM, RegXMM, RegXMM } -vfnmaddss, 0x668d | 0x, None, CpuFMA, Modrm|VexLIG|Space0F38= |VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Un= specified|BaseIndex|RegXMM, RegXMM, RegXMM } -vfnmsubpd, 0x668e | 0x, None, CpuFMA, Modrm|Vex|Space0F38|Ve= xVVVV|VexW1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, = { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfnmsubps, 0x668e | 0x, None, CpuFMA, Modrm|Vex|Space0F38|Ve= xVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, = { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfnmsubsd, 0x668f | 0x, None, CpuFMA, Modrm|VexLIG|Space0F38= |VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Un= specified|BaseIndex|RegXMM, RegXMM, RegXMM } -vfnmsubss, 0x668f | 0x, None, CpuFMA, Modrm|VexLIG|Space0F38= |VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Un= specified|BaseIndex|RegXMM, RegXMM, RegXMM } +vfmaddp, 0x6688 | 0x, None, CpuFMA, Modrm|Vex|Space0F38|= VexVVVV||CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_l= dSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vfmadds, 0x6689 | 0x, None, CpuFMA, Modrm|VexLIG|Space0F= 38|VexVVVV||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vfmaddsubp, 0x6686 | 0x, None, CpuFMA, Modrm|Vex|Space0F= 38|VexVVVV||CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N= o_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYM= M } +vfmsubp, 0x668a | 0x, None, CpuFMA, Modrm|Vex|Space0F38|= VexVVVV||CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_l= dSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vfmsubs, 0x668b | 0x, None, CpuFMA, Modrm|VexLIG|Space0F= 38|VexVVVV||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vfmsubaddp, 0x6687 | 0x, None, CpuFMA, Modrm|Vex|Space0F= 38|VexVVVV||CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N= o_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYM= M } +vfnmaddp, 0x668c | 0x, None, CpuFMA, Modrm|Vex|Space0F38= |VexVVVV||CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_= ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vfnmadds, 0x668d | 0x, None, CpuFMA, Modrm|VexLIG|Space0= F38|VexVVVV||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <= sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } +vfnmsubp, 0x668e | 0x, None, CpuFMA, Modrm|Vex|Space0F38= |VexVVVV||CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_= ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vfnmsubs, 0x668f | 0x, None, CpuFMA, Modrm|VexLIG|Space0= F38|VexVVVV||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <= sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } =20 // HLE prefixes =20 @@ -1930,26 +1864,16 @@ shrx, 0xf2f7, None, CpuBMI2, Modrm|CheckRegSize|Vex= 128|Space0F38|VexVVVV=3D1|SwapS =20 // FMA4 instructions =20 -vfmaddpd, 0x6669, None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSo= urces=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {U= nspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|Re= gYMM } -vfmaddps, 0x6668, None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSo= urces=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {U= nspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|Re= gYMM } -vfmaddsd, 0x666b, None, CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|Ve= xSources=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unsp= ecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } -vfmaddss, 0x666a, None, CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|Ve= xSources=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unsp= ecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } -vfmaddsubpd, 0x665d, None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|Ve= xSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,= {Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM= |RegYMM } -vfmaddsubps, 0x665c, None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|Ve= xSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,= {Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM= |RegYMM } -vfmsubaddpd, 0x665f, None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|Ve= xSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,= {Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM= |RegYMM } -vfmsubaddps, 0x665e, None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|Ve= xSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,= {Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM= |RegYMM } -vfmsubpd, 0x666d, None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSo= urces=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {U= nspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|Re= gYMM } -vfmsubps, 0x666c, None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSo= urces=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {U= nspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|Re= gYMM } -vfmsubsd, 0x666f, None, CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|Ve= xSources=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unsp= ecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } -vfmsubss, 0x666e, None, CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|Ve= xSources=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unsp= ecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } -vfnmaddpd, 0x6679, None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexS= ources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {= Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|R= egYMM } -vfnmaddps, 0x6678, None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexS= ources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {= Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|R= egYMM } -vfnmaddsd, 0x667b, None, CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|V= exSources=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Uns= pecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } -vfnmaddss, 0x667a, None, CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|V= exSources=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Uns= pecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } -vfnmsubpd, 0x667d, None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexS= ources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {= Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|R= egYMM } -vfnmsubps, 0x667c, None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexS= ources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {= Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|R= egYMM } -vfnmsubsd, 0x667f, None, CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|V= exSources=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Uns= pecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } -vfnmsubss, 0x667e, None, CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|V= exSources=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Uns= pecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } +vfmaddp, 0x6668 | , None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVV= VV|VexW1|VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu= f|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|Re= gYMM, RegXMM|RegYMM } +vfmadds, 0x666a | , None, CpuFMA4, D|Modrm|VexLIG|Space0F3A|Ve= xVVVV|VexW1|VexSources=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf= , { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } +vfmaddsubp, 0x665c | , None, CpuFMA4, D|Modrm|Vex|Space0F3A|Ve= xVVVV|VexW1|VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_= qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM= |RegYMM, RegXMM|RegYMM } +vfmsubaddp, 0x665e | , None, CpuFMA4, D|Modrm|Vex|Space0F3A|Ve= xVVVV|VexW1|VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_= qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM= |RegYMM, RegXMM|RegYMM } +vfmsubp, 0x666c | , None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVV= VV|VexW1|VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu= f|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|Re= gYMM, RegXMM|RegYMM } +vfmsubs, 0x666e | , None, CpuFMA4, D|Modrm|VexLIG|Space0F3A|Ve= xVVVV|VexW1|VexSources=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf= , { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } +vfnmaddp, 0x6678 | , None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexV= VVV|VexW1|VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS= uf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|R= egYMM, RegXMM|RegYMM } +vfnmadds, 0x667a | , None, CpuFMA4, D|Modrm|VexLIG|Space0F3A|V= exVVVV|VexW1|VexSources=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSu= f, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } +vfnmsubp, 0x667c | , None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexV= VVV|VexW1|VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS= uf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|R= egYMM, RegXMM|RegYMM } +vfnmsubs, 0x667e | , None, CpuFMA4, D|Modrm|VexLIG|Space0F3A|V= exVVVV|VexW1|VexSources=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSu= f, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } =20 // XOP instructions =20 @@ -1957,17 +1881,13 @@ vfnmsubss, 0x667e, None, CpuFMA4, D|Modrm|VexLIG|Sp= ace0F3A|VexVVVV|VexW1|VexSour =20 -vfrczpd, 0x81, None, CpuXOP, Modrm|SpaceXOP09|VexW=3D1|CheckRegSize|No_bSu= f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Unspecified|BaseIndex|Reg= XMM|RegYMM, RegXMM|RegYMM } -vfrczps, 0x80, None, CpuXOP, Modrm|SpaceXOP09|VexW=3D1|CheckRegSize|No_bSu= f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Unspecified|BaseIndex|Reg= XMM|RegYMM, RegXMM|RegYMM } -vfrczsd, 0x83, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_lSu= f|No_sSuf|No_qSuf|No_ldSuf|Vex, { Qword|RegXMM|Unspecified|BaseIndex, RegXM= M } -vfrczss, 0x82, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_lSu= f|No_sSuf|No_qSuf|No_ldSuf|Vex, { Dword|RegXMM|Unspecified|BaseIndex, RegXM= M } +vfrczp, 0x80 | , None, CpuXOP, Modrm|SpaceXOP09|VexW0|CheckReg= Size|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Unspecified|Ba= seIndex|RegXMM|RegYMM, RegXMM|RegYMM } +vfrczs, 0x82 | , None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|= No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { |RegXMM|Unspecifie= d|BaseIndex, RegXMM } vpcmov, 0xa2, None, CpuXOP, D|Modrm|SpaceXOP08|VexSources=3D2|VexVVVV|VexW= 0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegX= MM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYM= M } vpcom, 0xcc | 0x | , None,= CpuXOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_s= Suf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } vpcom, 0xcc | 0x | , , CpuXOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|No_bSuf|= No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Unspecified|BaseI= ndex, RegXMM, RegXMM } -vpermil2pd, 0x6649, None, CpuXOP, Modrm|Space0F3A|VexVVVV=3D1|VexW=3D1|Vex= |VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS= uf, { Imm8, RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegY= MM, RegXMM|RegYMM } -vpermil2pd, 0x6649, None, CpuXOP, Modrm|Space0F3A|VexVVVV=3D1|VexW=3D2|Vex= |VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS= uf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegY= MM, RegXMM|RegYMM } -vpermil2ps, 0x6648, None, CpuXOP, Modrm|Space0F3A|VexVVVV=3D1|VexW=3D1|Vex= |VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS= uf, { Imm8, RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegY= MM, RegXMM|RegYMM } -vpermil2ps, 0x6648, None, CpuXOP, Modrm|Space0F3A|VexVVVV=3D1|VexW=3D2|Vex= |VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS= uf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegY= MM, RegXMM|RegYMM } +vpermil2p, 0x6648 | , None, CpuXOP, Modrm|Space0F3A|VexVVVV|Ve= xW0|Vex|VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf= |No_ldSuf, { Imm8, RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegX= MM|RegYMM, RegXMM|RegYMM } +vpermil2p, 0x6648 | , None, CpuXOP, Modrm|Space0F3A|VexVVVV|Ve= xW1|Vex|VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf= |No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegX= MM|RegYMM, RegXMM|RegYMM } vphaddbd, 0xc2, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_lS= uf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } vphaddbq, 0xc3, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_lS= uf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } vphaddbw, 0xc1, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_lS= uf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } @@ -2165,6 +2085,11 @@ vpclmulhqhqdq, 0x6644, 0x11, CpuVPCLMULQDQ, Modrm|Ve= x=3D2|Space0F3A|VexWIG|VexVVVV #define Disp8ShiftVL Disp8MemShift=3DDISP8_SHIFT_VL #define MaskingMorZ Masking=3DDYNAMIC_MASKING =20 + + kandnw, 0x42, None, CpuAVX512F, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW=3D1= |No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegM= ask } kandw, 0x41, None, CpuAVX512F, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW=3D1|= No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMa= sk } korw, 0x45, None, CpuAVX512F, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW=3D1|N= o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMas= k } @@ -2183,27 +2108,17 @@ kshiftrw, 0x6630, None, CpuAVX512F, Modrm|Vex=3D1|S= pace0F3A|VexW=3D2|No_bSuf|No_wSuf =20 kunpckbw, 0x664B, None, CpuAVX512F, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW= =3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, = RegMask } =20 -vaddpd, 0x6658, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|VexW1|= Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf= |No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|Base= Index, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vdivpd, 0x665E, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|VexW1|= Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf= |No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|Base= Index, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vmulpd, 0x6659, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|VexW1|= Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf= |No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|Base= Index, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vsubpd, 0x665C, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|VexW1|= Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf= |No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|Base= Index, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } - -vaddps, 0x58, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|VexW0|Br= oadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N= o_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIn= dex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vdivps, 0x5E, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|VexW0|Br= oadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N= o_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIn= dex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vmulps, 0x59, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|VexW0|Br= oadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N= o_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIn= dex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vsubps, 0x5C, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|VexW0|Br= oadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N= o_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIn= dex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vaddp, 0x58, None, , Modrm|Masking=3D3||= VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_l= Suf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vdivp, 0x5e, None, , Modrm|Masking=3D3||= VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_l= Suf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vmulp, 0x59, None, , Modrm|Masking=3D3||= VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_l= Suf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vsqrtp, 0x51, None, , Modrm|Masking=3D3|= ||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_= sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|= |Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vsubp, 0x5c, None, , Modrm|Masking=3D3||= VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_l= Suf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } =20 -vaddsd, 0xF258, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F|VexVVV= V|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|= StaticRounding|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM } -vdivsd, 0xF25E, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F|VexVVV= V|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|= StaticRounding|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM } -vmulsd, 0xF259, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F|VexVVV= V|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|= StaticRounding|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM } -vsqrtsd, 0xF251, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F|VexVV= VV|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf= |StaticRounding|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM } -vsubsd, 0xF25C, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F|VexVVV= V|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|= StaticRounding|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM } - -vaddss, 0xF358, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F|VexVVV= V|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|= StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } -vdivss, 0xF35E, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F|VexVVV= V|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|= StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } -vmulss, 0xF359, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F|VexVVV= V|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|= StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } -vsqrtss, 0xF351, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F|VexVV= VV|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf= |StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } -vsubss, 0xF35C, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F|VexVVV= V|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|= StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } +vadds, 0x58, None, , Modrm|EVexLIG|Masking=3D3||VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseInde= x, RegXMM, RegXMM } +vdivs, 0x5e, None, , Modrm|EVexLIG|Masking=3D3||VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseInde= x, RegXMM, RegXMM } +vmuls, 0x59, None, , Modrm|EVexLIG|Masking=3D3||VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseInde= x, RegXMM, RegXMM } +vsqrts, 0x51, None, , Modrm|EVexLIG|Masking=3D3||VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N= o_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseInd= ex, RegXMM, RegXMM } +vsubs, 0x5C, None, , Modrm|EVexLIG|Masking=3D3||VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseInde= x, RegXMM, RegXMM } =20 valignd, 0x6603, None, CpuAVX512F, Modrm|Masking=3D3|Space0F3A|VexVVVV=3D1= |VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseInd= ex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vpternlogd, 0x6625, None, CpuAVX512F, Modrm|Masking=3D3|Space0F3A|VexVVVV= =3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|Bas= eIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } @@ -2211,11 +2126,11 @@ vpternlogd, 0x6625, None, CpuAVX512F, Modrm|Masking= =3D3|Space0F3A|VexVVVV=3D1|VexW=3D1 valignq, 0x6603, None, CpuAVX512F, Modrm|Masking=3D3|Space0F3A|VexVVVV=3D1= |VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseInd= ex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vpternlogq, 0x6625, None, CpuAVX512F, Modrm|Masking=3D3|Space0F3A|VexVVVV= =3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|Bas= eIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } =20 -vblendmpd, 0x6665, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vblendmp, 0x6665, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVV= V||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_= sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseInd= ex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vpblendmq, 0x6664, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpermi2pd, 0x6677, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpermi2p, 0x6677, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVV= V||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_= sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseInd= ex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vpermi2q, 0x6676, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=3D= 1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_s= Suf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, R= egXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpermt2pd, 0x667F, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpermt2p, 0x667F, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVV= V||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_= sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseInd= ex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vpermt2q, 0x667E, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=3D= 1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_s= Suf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, R= egXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vpmaxsq, 0x663D, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=3D1= |VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, Re= gXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vpmaxuq, 0x663F, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=3D1= |VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, Re= gXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } @@ -2228,12 +2143,9 @@ vpsllvq, 0x6647, None, CpuAVX512F, Modrm|Masking=3D3= |Space0F38|VexVVVV=3D1|VexW=3D2|Br vpsravq, 0x6646, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=3D1= |VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, Re= gXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vpsrlvq, 0x6645, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=3D1= |VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, Re= gXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } =20 -vblendmps, 0x6665, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vpblendmd, 0x6664, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vpermi2d, 0x6676, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=3D= 1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_s= Suf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, R= egXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpermi2ps, 0x6677, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vpermt2d, 0x667E, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=3D= 1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_s= Suf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, R= egXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpermt2ps, 0x667F, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vpmaxsd, 0x663D, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=3D1= |VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, Re= gXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vpmaxud, 0x663F, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=3D1= |VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, Re= gXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vpminsd, 0x6639, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=3D1= |VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, Re= gXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } @@ -2257,23 +2169,14 @@ vbroadcastsd, 0x6619, None, CpuAVX512F, Modrm|Maski= ng=3D3|Space0F38|VexW1|Disp8Mem vpbroadcastd, 0x6658, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexW0|= Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXM= M|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } vpbroadcastd, 0x667C, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|No_bSu= f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, RegXMM|RegYMM|RegZMM } =20 -vcmppd, 0x66C2, 0x, CpuAVX512F, Modrm|Masking=3D2|= Space0F|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|N= o_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE|ImmExt, { RegXMM|RegYMM|RegZMM|Qword|Un= specified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vcmppd, 0x66C2, None, CpuAVX512F, Modrm|Masking=3D2|Space0F|VexVVVV=3D1|Ve= xW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_= qSuf|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegMask } - -vcmpps, 0xC2, 0x, CpuAVX512F, Modrm|Masking=3D2|Sp= ace0F|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_= lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unsp= ecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vcmpps, 0xC2, None, CpuAVX512F, Modrm|Masking=3D2|Space0F|VexVVVV=3D1|VexW= 0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS= uf|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, = RegXMM|RegYMM|RegZMM, RegMask } - -vcmpsd, 0xF2C2, 0x, CpuAVX512F, Modrm|EVexLIG|Mask= ing=3D2|Space0F|VexVVVV|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_= sSuf|No_qSuf|No_ldSuf|SAE|ImmExt, { RegXMM|Qword|Unspecified|BaseIndex, Reg= XMM, RegMask } -vcmpsd, 0xF2C2, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D2|Space0F|VexVVV= V|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|= SAE, { Imm8, RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegMask } +vcmpp, 0xC2, 0x, CpuAVX512F, Modrm|Ma= sking=3D2|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_= bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, { RegXMM|RegYMM|R= egZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vcmpp, 0xC2, None, CpuAVX512F, Modrm|Masking=3D2|Space0F|VexV= VVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM||Unspeci= fied|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } =20 -vcmpss, 0xF3C2, 0x, CpuAVX512F, Modrm|EVexLIG|Mask= ing=3D2|Space0F|VexVVVV|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_= sSuf|No_qSuf|No_ldSuf|SAE|ImmExt, { RegXMM|Dword|Unspecified|BaseIndex, Reg= XMM, RegMask } -vcmpss, 0xF3C2, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D2|Space0F|VexVVV= V|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|= SAE, { Imm8, RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegMask } +vcmps, 0xC2, 0x, CpuAVX512F, Modrm|EV= exLIG|Masking=3D2|Space0F|VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|N= o_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE|ImmExt, { RegXMM||Unspecified|= BaseIndex, RegXMM, RegMask } +vcmps, 0xC2, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D2|Spac= e0F|VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf= |No_ldSuf|SAE, { Imm8, RegXMM||Unspecified|BaseIndex, RegXMM, RegM= ask } =20 -vcomisd, 0x662F, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexW1|Disp8MemShi= ft=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM|Qword= |Unspecified|BaseIndex, RegXMM } -vucomisd, 0x662E, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexW1|Disp8MemSh= ift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM|Qwor= d|Unspecified|BaseIndex, RegXMM } - -vcomiss, 0x2F, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexW0|Disp8MemShift= =3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM|Dword|U= nspecified|BaseIndex, RegXMM } -vucomiss, 0x2E, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexW0|Disp8MemShif= t=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM|Dword|= Unspecified|BaseIndex, RegXMM } +vcomis, 0x2f, None, , Modrm|EVexLIG|||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE,= { RegXMM||Unspecified|BaseIndex, RegXMM } +vucomis, 0x2e, None, , Modrm|EVexLIG|||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE= , { RegXMM||Unspecified|BaseIndex, RegXMM } =20 vcompresspd, 0x668A, None, CpuAVX512F, Modrm|MaskingMorZ|Space0F38|VexW=3D= 2|Disp8MemShift=3D3|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No= _ldSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } vcompressps, 0x668A, None, CpuAVX512F, Modrm|MaskingMorZ|Space0F38|VexW=3D= 1|Disp8MemShift=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No= _ldSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } @@ -2293,7 +2196,6 @@ vcvtudq2pd, 0xF37A, None, CpuAVX512F, Modrm|EVex=3D1|= Masking=3D3|Space0F|VexW=3D1|Broa =20 vcvtdq2ps, 0x5B, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexW0|Broadca= st|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS= uf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, = RegXMM|RegYMM|RegZMM } vcvtps2udq, 0x79, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexW0|Broadc= ast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld= Suf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex,= RegXMM|RegYMM|RegZMM } -vsqrtps, 0x51, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexW0|Broadcast= |Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf= |StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, Re= gXMM|RegYMM|RegZMM } =20 vcvtpd2dq, 0xF2E6, None, CpuAVX512F, Modrm|EVex512|Masking=3D3|Space0F|Vex= W1|Broadcast|Disp8MemShift=3D6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_l= dSuf|StaticRounding|SAE, { RegZMM|Qword|Unspecified|BaseIndex, RegYMM } =20 @@ -2362,42 +2264,28 @@ vextracti64x4, 0x663B, None, CpuAVX512F, Modrm|EVex= =3D1|MaskingMorZ|Space0F3A|VexW vextractps, 0x6617, None, CpuAVX512F, Modrm|EVex128|Space0F3A|VexWIG|Disp8= MemShift=3D2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {= Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex } vextractps, 0x6617, None, CpuAVX512F|Cpu64, RegMem|EVex128|Space0F3A|VexWI= G|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg64 } =20 -vfixupimmpd, 0x6654, None, CpuAVX512F, Modrm|Masking=3D3|Space0F3A|VexVVVV= |VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|= No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIn= dex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfixupimmps, 0x6654, None, CpuAVX512F, Modrm|Masking=3D3|Space0F3A|VexVVVV= |VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|= No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIn= dex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } - -vfixupimmsd, 0x6655, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F3A= |VexVVVV|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No= _ldSuf|SAE, { Imm8, RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM } -vgetmantsd, 0x6627, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F3A|= VexVVVV|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_= ldSuf|SAE, { Imm8, RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM } -vrndscalesd, 0x660B, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F3A= |VexVVVV|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No= _ldSuf|SAE, { Imm8, RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM } - -vfixupimmss, 0x6655, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F3A= |VexVVVV|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No= _ldSuf|SAE, { Imm8, RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } -vgetmantss, 0x6627, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F3A|= VexVVVV|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_= ldSuf|SAE, { Imm8, RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } -vrndscaless, 0x660A, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F3A= |VexVVVV|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No= _ldSuf|SAE, { Imm8, RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } - -vfmaddpd, 0x6688 | 0x, None, CpuAVX512F, Modrm|Masking=3D3|S= pace0F38|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM= |Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfmaddps, 0x6688 | 0x, None, CpuAVX512F, Modrm|Masking=3D3|S= pace0F38|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM= |Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfmaddsd, 0x6689 | 0x, None, CpuAVX512F, Modrm|EVexLIG|Maski= ng=3D3|Space0F38|VexVVVV|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No= _sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|Qword|Unspecified|BaseI= ndex, RegXMM, RegXMM } -vfmaddss, 0x6689 | 0x, None, CpuAVX512F, Modrm|EVexLIG|Maski= ng=3D3|Space0F38|VexVVVV|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No= _sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseI= ndex, RegXMM, RegXMM } -vfmaddsubpd, 0x6686 | 0x, None, CpuAVX512F, Modrm|Masking=3D= 3|Space0F38|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wS= uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|Reg= ZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM= } -vfmaddsubps, 0x6686 | 0x, None, CpuAVX512F, Modrm|Masking=3D= 3|Space0F38|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wS= uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|Reg= ZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM= } -vfmsubpd, 0x668A | 0x, None, CpuAVX512F, Modrm|Masking=3D3|S= pace0F38|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM= |Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfmsubps, 0x668A | 0x, None, CpuAVX512F, Modrm|Masking=3D3|S= pace0F38|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM= |Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfmsubsd, 0x668B | 0x, None, CpuAVX512F, Modrm|EVexLIG|Maski= ng=3D3|Space0F38|VexVVVV|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No= _sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|Qword|Unspecified|BaseI= ndex, RegXMM, RegXMM } -vfmsubss, 0x668B | 0x, None, CpuAVX512F, Modrm|EVexLIG|Maski= ng=3D3|Space0F38|VexVVVV|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No= _sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseI= ndex, RegXMM, RegXMM } -vfmsubaddpd, 0x6687 | 0x, None, CpuAVX512F, Modrm|Masking=3D= 3|Space0F38|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wS= uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|Reg= ZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM= } -vfmsubaddps, 0x6687 | 0x, None, CpuAVX512F, Modrm|Masking=3D= 3|Space0F38|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wS= uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|Reg= ZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM= } -vfnmaddpd, 0x668C | 0x, None, CpuAVX512F, Modrm|Masking=3D3|= Space0F38|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf= |No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZM= M|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfnmaddps, 0x668C | 0x, None, CpuAVX512F, Modrm|Masking=3D3|= Space0F38|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf= |No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZM= M|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfnmaddsd, 0x668D | 0x, None, CpuAVX512F, Modrm|EVexLIG|Mask= ing=3D3|Space0F38|VexVVVV|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|Qword|Unspecified|Base= Index, RegXMM, RegXMM } -vfnmaddss, 0x668D | 0x, None, CpuAVX512F, Modrm|EVexLIG|Mask= ing=3D3|Space0F38|VexVVVV|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|Base= Index, RegXMM, RegXMM } -vfnmsubpd, 0x668E | 0x, None, CpuAVX512F, Modrm|Masking=3D3|= Space0F38|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf= |No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZM= M|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfnmsubps, 0x668E | 0x, None, CpuAVX512F, Modrm|Masking=3D3|= Space0F38|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf= |No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZM= M|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfnmsubsd, 0x668F | 0x, None, CpuAVX512F, Modrm|EVexLIG|Mask= ing=3D3|Space0F38|VexVVVV|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|Qword|Unspecified|Base= Index, RegXMM, RegXMM } -vfnmsubss, 0x668F | 0x, None, CpuAVX512F, Modrm|EVexLIG|Mask= ing=3D3|Space0F38|VexVVVV|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|Base= Index, RegXMM, RegXMM } - -vscalefpd, 0x662C, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV|V= exW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified= |BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vscalefps, 0x662C, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV|V= exW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified= |BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vscalefsd, 0x662D, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F38|V= exVVVV|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_l= dSuf|StaticRounding|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegX= MM } -vscalefss, 0x662D, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F38|V= exVVVV|VexW0|Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_l= dSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegX= MM } +vfixupimmp, 0x6654, None, CpuAVX512F, Modrm|Masking=3D3|Space0F3A|VexV= VVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM||Unspeci= fied|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vfixupimms, 0x6655, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0= F3A|VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf= |No_ldSuf|SAE, { Imm8, RegXMM||Unspecified|BaseIndex, RegXMM, RegX= MM } + +vgetmantp, 0x26, None, , Modrm|Masking=3D3|Space0F3= A||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No= _sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM||Unspeci= fied|BaseIndex, RegXMM|RegYMM|RegZMM } +vgetmants, 0x27, None, , Modrm|EVexLIG|Masking=3D3|= Space0F3A|VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|= No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM||Unspecified|BaseIndex, RegX= MM, RegXMM } + +vrndscalep, 0x08 | , None, , Modrm|Masking= =3D3|Space0F3A||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wS= uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vrndscales, 0x0a | , None, , Modrm|EVexLIG= |Masking=3D3|Space0F3A|VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_= lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM||Unspecified|Ba= seIndex, RegXMM, RegXMM } + +vfmaddp, 0x6688 | 0x, None, , Modrm|Masking=3D= 3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegY= MM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|Re= gYMM|RegZMM } +vfmadds, 0x6689 | 0x, None, , Modrm|EVexLIG|Ma= sking=3D3||VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lS= uf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM||Unspeci= fied|BaseIndex, RegXMM, RegXMM } +vfmaddsubp, 0x6686 | 0x, None, , Modrm|Masking= =3D3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_b= Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|R= egYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM= |RegYMM|RegZMM } +vfmsubp, 0x668a | 0x, None, , Modrm|Masking=3D= 3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegY= MM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|Re= gYMM|RegZMM } +vfmsubs, 0x668b | 0x, None, , Modrm|EVexLIG|Ma= sking=3D3||VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lS= uf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM||Unspeci= fied|BaseIndex, RegXMM, RegXMM } +vfmsubaddp, 0x6687 | 0x, None, , Modrm|Masking= =3D3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_b= Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|R= egYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM= |RegYMM|RegZMM } +vfnmaddp, 0x668c | 0x, None, , Modrm|Masking= =3D3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_b= Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|R= egYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM= |RegYMM|RegZMM } +vfnmadds, 0x668d | 0x, None, , Modrm|EVexLIG|M= asking=3D3||VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_l= Suf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM||Unspec= ified|BaseIndex, RegXMM, RegXMM } +vfnmsubp, 0x668e | 0x, None, , Modrm|Masking= =3D3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_b= Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|R= egYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM= |RegYMM|RegZMM } +vfnmsubs, 0x668f | 0x, None, , Modrm|EVexLIG|M= asking=3D3||VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_l= Suf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM||Unspec= ified|BaseIndex, RegXMM, RegXMM } + +vscalefp, 0x662c, None, , Modrm|Masking=3D3||VexVV= VV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vscalefs, 0x662d, None, , Modrm|EVexLIG|Masking=3D3||VexVVVV|