From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1386) id 6D6A93858425; Tue, 16 Aug 2022 07:13:36 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 6D6A93858425 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Jan Beulich To: bfd-cvs@sourceware.org Subject: [binutils-gdb] x86: template-ize vector packed dword/qword integer insns X-Act-Checkin: binutils-gdb X-Git-Author: Jan Beulich X-Git-Refname: refs/heads/master X-Git-Oldrev: 73d214b268a95d06a0eff0f2347049820d1ae320 X-Git-Newrev: 6473a592b46edb7523fff0facba216f169056945 Message-Id: <20220816071336.6D6A93858425@sourceware.org> Date: Tue, 16 Aug 2022 07:13:36 +0000 (GMT) X-BeenThere: binutils-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 16 Aug 2022 07:13:36 -0000 https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D6473a592b46e= db7523fff0facba216f169056945 commit 6473a592b46edb7523fff0facba216f169056945 Author: Jan Beulich Date: Tue Aug 16 09:12:30 2022 +0200 x86: template-ize vector packed dword/qword integer insns =20 Many of the vector integer insns come in dword/qword element pairs. Most of these pairs follow certain encoding patterns. Introduce a "dq" template to reduce redundancy. =20 Note that in the course of the conversion - a few otherwise untouched templates are moved, so they end up next to their siblings), - drop an unhelpful Cpu64 from the GPR form of VPBROADCASTQ, matching what we already have for KMOVQ - the diagnostic is better this way for insns with multiple forms (i.e. the same Cpu64 attributes on {,V}MOVQ, {,V}PEXTRQ, and {,V}PINSRQ are useful to keep), - this adds benign/meaningless IgnoreSize attributes to the GPR forms of KMOVD and VPBROADCASTD; it didn't seem worth avoiding this. Diff: --- opcodes/i386-opc.tbl | 295 ++++++------------ opcodes/i386-tbl.h | 838 +++++++++++++++++++++++++----------------------= ---- 2 files changed, 518 insertions(+), 615 deletions(-) diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index d894056ebbd..454e6dccf98 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -976,6 +976,10 @@ pause, 0xf390, None, Cpu186, No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { $avx:CpuAVX:Vex128|VexW0|SSE2AVX:VexLIG|VexW0|SSE2AVX:VexVVVV:Vex128|V= exVVVV=3D2|VexW0|SSE2AVX, + $sse:CpuSSE2::NoRex64::> =20 + + emms, 0xf77, None, CpuMMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSu= f, {} // These really shouldn't allow for Reg64 (movq is the right mnemonic for // copying between Reg64/Mem64 and RegXMM/RegMMX, as is mandated by Intel's @@ -1021,20 +1025,16 @@ pmullw, 0x0fd5, None, , Modr= m||C|No_bSuf|No_wSu por, 0x0feb, None, , Modrm||C|No_bSuf|No_= wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecified|Ba= seIndex, } psllw, 0x0ff1, None, , Modrm||No_bSuf|No_= wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecified|Ba= seIndex, } psllw, 0x0f71, 6, , Modrm||No_bSuf|No_wS= uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, } -pslld, 0x0ff2, None, , Modrm||No_bSuf|No_= wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecified|Ba= seIndex, } -pslld, 0x0f72, 6, , Modrm||No_bSuf|No_wS= uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, } -psllq, 0x0ff3, None, , Modrm||No_bSuf|No_= wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecified|Ba= seIndex, } -psllq, 0x0f73, 6, , Modrm||No_bSuf|No_wS= uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, } +psll, 0x0ff2 | , None, , Modrm||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||= Unspecified|BaseIndex, } +psll, 0x0f72 | , 6, , Modrm|= |No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, } psraw, 0x0fe1, None, , Modrm||No_bSuf|No_= wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecified|Ba= seIndex, } psraw, 0x0f71, 4, , Modrm||No_bSuf|No_wS= uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, } psrad, 0x0fe2, None, , Modrm||No_bSuf|No_= wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecified|Ba= seIndex, } psrad, 0x0f72, 4, , Modrm||No_bSuf|No_wS= uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, } psrlw, 0x0fd1, None, , Modrm||No_bSuf|No_= wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecified|Ba= seIndex, } psrlw, 0x0f71, 2, , Modrm||No_bSuf|No_wS= uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, } -psrld, 0x0fd2, None, , Modrm||No_bSuf|No_= wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecified|Ba= seIndex, } -psrld, 0x0f72, 2, , Modrm||No_bSuf|No_wS= uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, } -psrlq, 0x0fd3, None, , Modrm||No_bSuf|No_= wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecified|Ba= seIndex, } -psrlq, 0x0f73, 2, , Modrm||No_bSuf|No_wS= uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, } +psrl, 0x0fd2 | , None, , Modrm||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||= Unspecified|BaseIndex, } +psrl, 0x0f72 | , 2, , Modrm|= |No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, } psubb, 0x0ff8, None, , Modrm||No_bSuf|No_= wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecified|Ba= seIndex, } psubw, 0x0ff9, None, , Modrm||No_bSuf|No_= wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecified|Ba= seIndex, } psubd, 0x0ffa, None, , Modrm||No_bSuf|No_= wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ||Unspecified|Ba= seIndex, } @@ -1617,8 +1617,7 @@ vpermilp, 0x660c | , None, CpuAVX, Modrm|= Vex|Space0F38|VexVVVV|VexW0 vpermilp, 0x6604 | , None, CpuAVX, Modrm|Vex|Space0F3A|VexW0|C= heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspe= cified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } vpextrb, 0x6614, None, CpuAVX, RegMem|Vex|Space0F3A|VexWIG|No_bSuf|No_wSuf= |No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64 } vpextrb, 0x6614, None, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Byte|Unspecified|BaseInde= x } -vpextrd, 0x6616, None, CpuAVX, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_w= Suf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspecifi= ed|BaseIndex } -vpextrq, 0x6616, None, CpuAVX|Cpu64, Modrm|Vex|Space0F3A|VexW1|No_bSuf|No_= wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg64|Unspecified|Ba= seIndex } +vpextr, 0x6616, None, CpuAVX|, Modrm|Vex|Space0F3A||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, |Unspecified|BaseIndex } vpextrw, 0x66c5, None, CpuAVX, Load|Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wS= uf|No_sSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64 } vpextrw, 0x6615, None, CpuAVX, RegMem|Vex|Space0F3A|VexWIG|No_bSuf|No_wSuf= |No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64 } vpextrw, 0x6615, None, CpuAVX, Modrm|Vex|Space0F3A|VexWIG|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Word|Unspecified|BaseInde= x } @@ -1631,8 +1630,7 @@ vphsubsw, 0x6607, None, CpuAVX|CpuAVX2, Modrm|Vex|Spa= ce0F38|VexVVVV|VexWIG|Check vphsubw, 0x6605, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|= CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifie= d|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vpinsrb, 0x6620, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=3D1|VexWIG|No_b= Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Reg64, RegXMM, = RegXMM } vpinsrb, 0x6620, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|No_bSuf|= No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Byte|Unspecified|BaseInde= x, RegXMM, RegXMM } -vpinsrd, 0x6622, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=3D1|IgnoreSize|= No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Dword|Unspe= cified|BaseIndex, RegXMM, RegXMM } -vpinsrq, 0x6622, None, CpuAVX|Cpu64, Modrm|Vex|Space0F3A|VexVVVV=3D1|VexW1= |No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg64|Unspecifie= d|BaseIndex, RegXMM, RegXMM } +vpinsr, 0x6622, None, CpuAVX|, Modrm|Vex|Space0F3A|VexVVVV|<= dq:vexw64>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, |Unspecified|BaseIndex, RegXMM, RegXMM } vpinsrw, 0x66c4, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV=3D1|VexWIG|No_bSu= f|No_wSuf|No_sSuf|No_ldSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM } vpinsrw, 0x66c4, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|No_bSuf|No= _wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Word|Unspecified|BaseIndex,= RegXMM, RegXMM } vpmaddubsw, 0x6604, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW= IG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspeci= fied|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } @@ -1678,27 +1676,22 @@ vpshuflw, 0xf270, None, CpuAVX|CpuAVX2, Modrm|Vex|S= pace0F|VexWIG|CheckRegSize|No vpsignb, 0x6608, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|= CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifie= d|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vpsignd, 0x660a, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|= CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifie= d|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vpsignw, 0x6609, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|= CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecifie= d|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpslld, 0x6672, 6, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=3D2|VexWIG|Ch= eckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM= |RegYMM, RegXMM|RegYMM } -vpslld, 0x66f2, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|Che= ckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|B= aseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpsll, 0x6672 | , 6, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV= =3D2|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, = { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } +vpsll, 0x66f2 | , None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexV= VVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {= Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } vpslldq, 0x6673, 7, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=3D2|VexWIG|C= heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXM= M|RegYMM, RegXMM|RegYMM } -vpsllq, 0x6673, 6, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=3D2|VexWIG|Ch= eckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM= |RegYMM, RegXMM|RegYMM } -vpsllq, 0x66f3, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|Che= ckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|B= aseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } vpsllw, 0x6671, 6, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=3D2|VexWIG|Ch= eckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM= |RegYMM, RegXMM|RegYMM } vpsllw, 0x66f1, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|Che= ckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|B= aseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } vpsrad, 0x6672, 4, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=3D2|VexWIG|Ch= eckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM= |RegYMM, RegXMM|RegYMM } vpsrad, 0x66e2, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|Che= ckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|B= aseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } vpsraw, 0x6671, 4, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=3D2|VexWIG|Ch= eckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM= |RegYMM, RegXMM|RegYMM } vpsraw, 0x66e1, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|Che= ckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|B= aseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpsrld, 0x6672, 2, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=3D2|VexWIG|Ch= eckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM= |RegYMM, RegXMM|RegYMM } -vpsrld, 0x66d2, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|Che= ckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|B= aseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpsrl, 0x6672 | , 2, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV= =3D2|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, = { Imm8, RegXMM|RegYMM, RegXMM|RegYMM } +vpsrl, 0x66d2 | , None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexV= VVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {= Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } vpsrldq, 0x6673, 3, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=3D2|VexWIG|C= heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXM= M|RegYMM, RegXMM|RegYMM } -vpsrlq, 0x6673, 2, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=3D2|VexWIG|Ch= eckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM= |RegYMM, RegXMM|RegYMM } -vpsrlq, 0x66d3, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|Che= ckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|B= aseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } vpsrlw, 0x6671, 2, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV=3D2|VexWIG|Ch= eckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM= |RegYMM, RegXMM|RegYMM } vpsrlw, 0x66d1, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|Che= ckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|B= aseIndex|RegXMM, RegXMM|RegYMM, RegXMM|RegYMM } vpsubb, 0x66f8, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|Che= ckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Unsp= ecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpsubd, 0x66fa, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|Che= ckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Unsp= ecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpsubq, 0x66fb, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|Che= ckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Unsp= ecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpsub, 0x66fa | , None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexV= VVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Op= timize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM= } vpsubsb, 0x66e8, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|Ch= eckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|= BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vpsubsw, 0x66e9, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|Ch= eckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|= BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vpsubusb, 0x66d8, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|C= heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified= |BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } @@ -1756,8 +1749,7 @@ vbroadcastsd, 0x6619, None, CpuAVX2, Modrm|Vex=3D2|Sp= ace0F38|VexW=3D1|No_bSuf|No_wSu vbroadcastss, 0x6618, None, CpuAVX2, Modrm|Vex|Space0F38|VexW=3D1|No_bSuf|= No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|RegYMM } vpblendd, 0x6602, None, CpuAVX2, Modrm|Vex|Space0F3A|VexVVVV=3D1|VexW=3D1|= CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unsp= ecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vpbroadcastb, 0x6678, None, CpuAVX2, Modrm|Vex=3D1|Space0F38|VexW0|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Byte|Unspecified|BaseIndex|Reg= XMM, RegXMM|RegYMM } -vpbroadcastd, 0x6658, None, CpuAVX2, Modrm|Vex=3D1|Space0F38|VexW0|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Re= gXMM, RegXMM|RegYMM } -vpbroadcastq, 0x6659, None, CpuAVX2, Modrm|Vex=3D1|Space0F38|VexW0|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Re= gXMM, RegXMM|RegYMM } +vpbroadcast, 0x6658 | , None, CpuAVX2, Modrm|Vex|Space0F38|Vex= W0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { |Unspecifie= d|BaseIndex|RegXMM, RegXMM|RegYMM } vpbroadcastw, 0x6679, None, CpuAVX2, Modrm|Vex=3D1|Space0F38|VexW0|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex|Reg= XMM, RegXMM|RegYMM } vperm2i128, 0x6646, None, CpuAVX2, Modrm|Vex=3D2|Space0F3A|VexVVVV=3D1|Vex= W=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified= |BaseIndex|RegYMM, RegYMM, RegYMM } vpermd, 0x6636, None, CpuAVX2, Modrm|Vex=3D2|Space0F38|VexVVVV=3D1|VexW=3D= 1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex= |RegYMM, RegYMM, RegYMM } @@ -1766,15 +1758,11 @@ vpermps, 0x6616, None, CpuAVX2, Modrm|Vex=3D2|Space= 0F38|VexVVVV=3D1|VexW=3D1|No_bSuf|N vpermq, 0x6600, None, CpuAVX2, Modrm|Vex=3D2|Space0F3A|VexW=3D2|No_bSuf|No= _wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegYM= M, RegYMM } vextracti128, 0x6639, None, CpuAVX2, Modrm|Vex=3D2|Space0F3A|VexW=3D1|No_b= Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, Unspecified|B= aseIndex|RegXMM } vinserti128, 0x6638, None, CpuAVX2, Modrm|Vex=3D2|Space0F3A|VexVVVV=3D1|Ve= xW=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecifie= d|BaseIndex|RegXMM, RegYMM, RegYMM } -vpmaskmovd, 0x668e, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV=3D1|VexW=3D= 1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|R= egYMM, RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex } -vpmaskmovd, 0x668c, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV=3D1|VexW=3D= 1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|= Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } -vpmaskmovq, 0x668e, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV=3D1|VexW=3D= 2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|R= egYMM, RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex } -vpmaskmovq, 0x668c, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV=3D1|VexW=3D= 2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|= Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } -vpsllvd, 0x6647, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV=3D1|VexW=3D1|C= heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified= |BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpsllvq, 0x6647, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV=3D1|VexW=3D2|C= heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified= |BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpmaskmov, 0x668e, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV||CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|R= egYMM, RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex } +vpmaskmov, 0x668c, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV||CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|= Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } +vpsllv, 0x6647, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV||C= heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified= |BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vpsravd, 0x6646, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV=3D1|VexW=3D1|C= heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified= |BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpsrlvd, 0x6645, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV=3D1|VexW=3D1|C= heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified= |BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpsrlvq, 0x6645, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV=3D1|VexW=3D2|C= heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified= |BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpsrlv, 0x6645, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV||C= heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified= |BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } =20 // AVX gather instructions vgatherdpd, 0x6692, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW1|Check= RegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXM= M|RegYMM, Qword|Unspecified|BaseIndex, RegXMM|RegYMM } @@ -1786,9 +1774,8 @@ vgatherqps, 0x6693, None, CpuAVX2, Modrm|Vex=3D2|Spac= e0F38|VexVVVV|VexW0|No_bSuf|N vpgatherdd, 0x6690, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW0|No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM, Dword|Unsp= ecified|BaseIndex, RegXMM } vpgatherdd, 0x6690, None, CpuAVX2, Modrm|Vex=3D2|Space0F38|VexVVVV|VexW0|N= o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB256, { RegYMM, Dword|= Unspecified|BaseIndex, RegYMM } vpgatherdq, 0x6690, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW1|Check= RegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXM= M|RegYMM, Qword|Unspecified|BaseIndex, RegXMM|RegYMM } -vpgatherqd, 0x6691, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW0|No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM, Dword|Unsp= ecified|BaseIndex, RegXMM } +vpgatherq, 0x6691, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM, |Unspecified|BaseIndex, RegXMM } vpgatherqd, 0x6691, None, CpuAVX2, Modrm|Vex=3D2|Space0F38|VexVVVV|VexW0|N= o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB256, { RegXMM, Dword|= Unspecified|BaseIndex, RegXMM } -vpgatherqq, 0x6691, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW1|No_bS= uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM, Qword|Unsp= ecified|BaseIndex, RegXMM } vpgatherqq, 0x6691, None, CpuAVX2, Modrm|Vex=3D2|Space0F38|VexVVVV|VexW1|N= o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB256, { RegYMM, Qword|= Unspecified|BaseIndex, RegYMM } =20 // AES + AVX @@ -1888,18 +1875,14 @@ vpcom, 0xcc | 0x = | , None, CpuXO vpcom, 0xcc | 0x | , , CpuXOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|No_bSuf|= No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Unspecified|BaseI= ndex, RegXMM, RegXMM } vpermil2p, 0x6648 | , None, CpuXOP, Modrm|Space0F3A|VexVVVV|Ve= xW0|Vex|VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf= |No_ldSuf, { Imm8, RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegX= MM|RegYMM, RegXMM|RegYMM } vpermil2p, 0x6648 | , None, CpuXOP, Modrm|Space0F3A|VexVVVV|Ve= xW1|Vex|VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf= |No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegX= MM|RegYMM, RegXMM|RegYMM } -vphaddbd, 0xc2, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_lS= uf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } -vphaddbq, 0xc3, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_lS= uf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } +vphaddb, 0xc2 | , None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseInd= ex, RegXMM } vphaddbw, 0xc1, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_lS= uf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } vphadddq, 0xcb, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_lS= uf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } -vphaddubd, 0xd2, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_l= Suf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } -vphaddubq, 0xd3, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_l= Suf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } +vphaddub, 0xd2 | , None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSu= f|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIn= dex, RegXMM } vphaddubw, 0xd1, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_l= Suf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } vphaddudq, 0xdb, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_l= Suf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } -vphadduwd, 0xd6, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_l= Suf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } -vphadduwq, 0xd7, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_l= Suf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } -vphaddwd, 0xc6, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_lS= uf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } -vphaddwq, 0xc7, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_lS= uf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } +vphadduw, 0xd6 | , None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSu= f|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIn= dex, RegXMM } +vphaddw, 0xc6 | , None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseInd= ex, RegXMM } vphsubbw, 0xe1, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_lS= uf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } vphsubdq, 0xe3, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_lS= uf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } vphsubwd, 0xe2, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_lS= uf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } @@ -2120,42 +2103,25 @@ vmuls, 0x59, None, , Modrm|= EVexLIG|Masking=3D3|| vsqrts, 0x51, None, , Modrm|EVexLIG|Masking=3D3||VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N= o_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseInd= ex, RegXMM, RegXMM } vsubs, 0x5C, None, , Modrm|EVexLIG|Masking=3D3||VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseInde= x, RegXMM, RegXMM } =20 -valignd, 0x6603, None, CpuAVX512F, Modrm|Masking=3D3|Space0F3A|VexVVVV=3D1= |VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseInd= ex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpternlogd, 0x6625, None, CpuAVX512F, Modrm|Masking=3D3|Space0F3A|VexVVVV= =3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|Bas= eIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } - -valignq, 0x6603, None, CpuAVX512F, Modrm|Masking=3D3|Space0F3A|VexVVVV=3D1= |VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseInd= ex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpternlogq, 0x6625, None, CpuAVX512F, Modrm|Masking=3D3|Space0F3A|VexVVVV= =3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|Bas= eIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } - +valign, 0x6603, None, CpuAVX512F, Modrm|Masking=3D3|Space0F3A|VexVVVV= =3D1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|= No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecifie= d|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vblendmp, 0x6665, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVV= V||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_= sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseInd= ex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpblendmq, 0x6664, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpblendm, 0x6664, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVV= V=3D1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf= |No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|Bas= eIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpermi2, 0x6676, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|= No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|Base= Index, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vpermi2p, 0x6677, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVV= V||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_= sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseInd= ex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpermi2q, 0x6676, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=3D= 1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_s= Suf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, R= egXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpermt2, 0x667E, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|= No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|Base= Index, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vpermt2p, 0x667F, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVV= V||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_= sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseInd= ex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpermt2q, 0x667E, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=3D= 1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_s= Suf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, R= egXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmaxsq, 0x663D, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=3D1= |VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, Re= gXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmaxuq, 0x663F, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=3D1= |VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, Re= gXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpminsq, 0x6639, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=3D1= |VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, Re= gXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpminuq, 0x663B, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=3D1= |VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, Re= gXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmaxs, 0x663D, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|= No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|Base= Index, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmaxu, 0x663F, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|= No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|Base= Index, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmins, 0x6639, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|= No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|Base= Index, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpminu, 0x663B, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|= No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|Base= Index, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vpmuldq, 0x6628, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=3D1= |VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, Re= gXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vprolvq, 0x6615, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=3D1= |VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, Re= gXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vprorvq, 0x6614, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=3D1= |VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, Re= gXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsllvq, 0x6647, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=3D1= |VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, Re= gXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsravq, 0x6646, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=3D1= |VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, Re= gXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsrlvq, 0x6645, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=3D1= |VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, Re= gXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } - -vpblendmd, 0x6664, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpermi2d, 0x6676, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=3D= 1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_s= Suf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, R= egXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpermt2d, 0x667E, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=3D= 1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_s= Suf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, R= egXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmaxsd, 0x663D, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=3D1= |VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, Re= gXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmaxud, 0x663F, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=3D1= |VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, Re= gXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpminsd, 0x6639, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=3D1= |VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, Re= gXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpminud, 0x663B, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=3D1= |VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, Re= gXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vpmulld, 0x6640, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=3D1= |VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, Re= gXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vprolvd, 0x6615, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=3D1= |VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, Re= gXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vprorvd, 0x6614, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=3D1= |VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, Re= gXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsllvd, 0x6647, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=3D1= |VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, Re= gXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsravd, 0x6646, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=3D1= |VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, Re= gXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsrlvd, 0x6645, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=3D1= |VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, Re= gXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vprolv, 0x6615, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|= No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|Base= Index, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vprorv, 0x6614, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|= No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|Base= Index, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsllv, 0x6647, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|= No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|Base= Index, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsrav, 0x6646, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|= No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|Base= Index, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsrlv, 0x6645, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV= =3D1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|= No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|Base= Index, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpternlog, 0x6625, None, CpuAVX512F, Modrm|Masking=3D3|Space0F3A|VexVV= VV=3D1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSu= f|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecif= ied|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } =20 vbroadcastf32x4, 0x661A, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|Vex= W=3D1|Disp8MemShift=3D4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {= XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } vbroadcasti32x4, 0x665A, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|Vex= W=3D1|Disp8MemShift=3D4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {= XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } @@ -2166,8 +2132,8 @@ vbroadcasti64x4, 0x665B, None, CpuAVX512F, Modrm|EVex= =3D1|Masking=3D3|Space0F38|VexW vbroadcastss, 0x6618, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexW0|= Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXM= M|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } vbroadcastsd, 0x6619, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexW1|= Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXM= M|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } =20 -vpbroadcastd, 0x6658, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexW0|= Disp8MemShift=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXM= M|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpbroadcastd, 0x667C, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|No_bSu= f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, RegXMM|RegYMM|RegZMM } +vpbroadcast, 0x6658 | , None, CpuAVX512F, Modrm|Masking=3D3|Sp= ace0F38||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_= ldSuf, { RegXMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpbroadcast, 0x667c, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { , RegX= MM|RegYMM|RegZMM } =20 vcmpp, 0xC2, 0x, CpuAVX512F, Modrm|Ma= sking=3D2|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_= bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, { RegXMM|RegYMM|R= egZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } vcmpp, 0xC2, None, CpuAVX512F, Modrm|Masking=3D2|Space0F|VexV= VVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM||Unspeci= fied|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } @@ -2348,52 +2314,33 @@ vmovs, 0x10, None, , D|Modr= m|EVexLIG|Masking=3D3|, 0x661e | , None, CpuAVX512F, Modrm|Masking=3D3|Space0F3= 8||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_= sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseInd= ex, RegXMM|RegYMM|RegZMM } vpaddd, 0x66FE, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|Ve= xW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|= No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXM= M|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpandd, 0x66DB, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|Ve= xW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|= No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseInd= ex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpandnd, 0x66DF, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|V= exW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf= |No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIn= dex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpord, 0x66EB, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|Vex= W=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N= o_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseInde= x, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsubd, 0x66FA, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|Ve= xW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|= No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseInd= ex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpaddq, 0x66d4, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|VexW1|= Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf= |No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYM= M|RegZMM, RegXMM|RegYMM|RegZMM } +vpand, 0x66db, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|= No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM||Unspecified|Bas= eIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpandn, 0x66df, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf= |No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM||Unspecified|Ba= seIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmuludq, 0x66f4, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|VexW= 1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS= uf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|Reg= YMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpor, 0x66eb, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N= o_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM||Unspecified|Base= Index, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsub, 0x66fa | , None, CpuAVX512F, Modrm|Masking=3D3|Space0F|= VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lS= uf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM||Unsp= ecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vpunpckhdq, 0x666A, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D= 1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_s= Suf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, R= egXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpunpckhqdq, 0x666d, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|V= exW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|= RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vpunpckldq, 0x6662, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D= 1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_s= Suf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, R= egXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpxord, 0x66EF, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|Ve= xW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|= No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseInd= ex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } - -vpaddq, 0x66D4, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|Ve= xW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|= No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXM= M|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpandnq, 0x66DF, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|V= exW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf= |No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIn= dex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpandq, 0x66DB, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|Ve= xW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|= No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseInd= ex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmuludq, 0x66F4, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|= VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSu= f|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, Reg= XMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vporq, 0x66EB, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|Vex= W=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N= o_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseInde= x, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsubq, 0x66FB, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|Ve= xW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|= No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseInd= ex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpunpckhqdq, 0x666D, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV= =3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpunpcklqdq, 0x666C, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV= =3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpxorq, 0x66EF, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|Ve= xW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|= No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseInd= ex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } - -vpbroadcastq, 0x6659, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexW1|= Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXM= M|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpbroadcastq, 0x667C, None, CpuAVX512F|Cpu64, Modrm|Masking=3D3|Space0F38|= VexW=3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg64, RegXMM|= RegYMM|RegZMM } +vpunpcklqdq, 0x666c, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|V= exW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|= RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpxor, 0x66ef, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|= No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM||Unspecified|Bas= eIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } =20 =20 vpcmpeqd, 0x6676, None, CpuAVX512F, Modrm|Masking=3D2|Space0F|VexVVVV=3D1|= VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSu= f|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, Reg= XMM|RegYMM|RegZMM, RegMask } +vpcmpeqq, 0x6629, None, CpuAVX512F, Modrm|Masking=3D2|Space0F38|VexVVVV|Ve= xW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_= qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|R= egYMM|RegZMM, RegMask } vpcmpgtd, 0x6666, None, CpuAVX512F, Modrm|Masking=3D2|Space0F|VexVVVV=3D1|= VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSu= f|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, Reg= XMM|RegYMM|RegZMM, RegMask } -vpcmpd, 0x661F, None, CpuAVX512F, Modrm|Masking=3D2|Space0F3A|VexVVVV=3D1|= VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSu= f|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseInde= x, RegXMM|RegYMM|RegZMM, RegMask } -vpcmpd, 0x661F, , CpuAVX512F, Modrm|Masking=3D2|Sp= ace0F3A|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|N= o_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Dword|Unspec= ified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmpud, 0x661E, None, CpuAVX512F, Modrm|Masking=3D2|Space0F3A|VexVVVV=3D1= |VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseInd= ex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmpud, 0x661E, , CpuAVX512F, Modrm|Masking=3D2|S= pace0F3A|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Dword|Unspe= cified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } - -vpcmpeqq, 0x6629, None, CpuAVX512F, Modrm|Masking=3D2|Space0F38|VexVVVV=3D= 1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_s= Suf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, R= egXMM|RegYMM|RegZMM, RegMask } -vpcmpgtq, 0x6637, None, CpuAVX512F, Modrm|Masking=3D2|Space0F38|VexVVVV=3D= 1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_s= Suf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, R= egXMM|RegYMM|RegZMM, RegMask } -vpcmpq, 0x661F, None, CpuAVX512F, Modrm|Masking=3D2|Space0F3A|VexVVVV=3D1|= VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSu= f|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseInde= x, RegXMM|RegYMM|RegZMM, RegMask } -vpcmpq, 0x661F, , CpuAVX512F, Modrm|Masking=3D2|Sp= ace0F3A|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|N= o_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Qword|Unspec= ified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmpuq, 0x661E, None, CpuAVX512F, Modrm|Masking=3D2|Space0F3A|VexVVVV=3D1= |VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseInd= ex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmpuq, 0x661E, , CpuAVX512F, Modrm|Masking=3D2|S= pace0F3A|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Qword|Unspe= cified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } - -vptestmd, 0x6627, None, CpuAVX512F, Modrm|Masking=3D2|Space0F38|VexVVVV=3D= 1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_s= Suf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, R= egXMM|RegYMM|RegZMM, RegMask } -vptestnmd, 0xF327, None, CpuAVX512F, Modrm|Masking=3D2|Space0F38|VexVVVV= =3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegMask } +vpcmpgtq, 0x6637, None, CpuAVX512F, Modrm|Masking=3D2|Space0F38|VexVVVV|Ve= xW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_= qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|R= egYMM|RegZMM, RegMask } +vpcmp, 0x661f, None, CpuAVX512F, Modrm|Masking=3D2|Space0F3A|VexVVVV|<= dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSu= f|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|Base= Index, RegXMM|RegYMM|RegZMM, RegMask } +vpcmpu, 0x661e, None, CpuAVX512F, Modrm|Masking=3D2|Space0F3A|VexVVVV|= |Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|Bas= eIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmp, 0x661f, , CpuAVX512F, Modrm|Masking=3D2= |Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No= _wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmpu, 0x661e, , CpuAVX512F, Modrm|Masking=3D= 2|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|N= o_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } =20 -vptestmq, 0x6627, None, CpuAVX512F, Modrm|Masking=3D2|Space0F38|VexVVVV=3D= 1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_s= Suf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, R= egXMM|RegYMM|RegZMM, RegMask } -vptestnmq, 0xF327, None, CpuAVX512F, Modrm|Masking=3D2|Space0F38|VexVVVV= =3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N= o_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegMask } +vptestm, 0x6627, None, CpuAVX512F, Modrm|Masking=3D2|Space0F38|VexVVVV= ||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_s= Suf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseInde= x, RegXMM|RegYMM|RegZMM, RegMask } +vptestnm, 0xf327, None, CpuAVX512F, Modrm|Masking=3D2|Space0F38|VexVVV= V||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_= sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseInd= ex, RegXMM|RegYMM|RegZMM, RegMask } =20 vpermd, 0x6636, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=3D1|= VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSu= f|No_qSuf|No_ldSuf, { RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|Reg= ZMM, RegYMM|RegZMM } vpermps, 0x6616, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV=3D1= |VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|Re= gZMM, RegYMM|RegZMM } @@ -2441,30 +2388,20 @@ vpmovzxwd, 0x6633, None, CpuAVX512F, Modrm|EVex=3D1= |Masking=3D3|Space0F38|VexWIG|Dis vpmovsxwq, 0x6624, None, CpuAVX512F, Modrm|EVex=3D1|Masking=3D3|Space0F38|= VexWIG|Disp8MemShift=3D4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, = { RegXMM|Unspecified|BaseIndex, RegZMM } vpmovzxwq, 0x6634, None, CpuAVX512F, Modrm|EVex=3D1|Masking=3D3|Space0F38|= VexWIG|Disp8MemShift=3D4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, = { RegXMM|Unspecified|BaseIndex, RegZMM } =20 -vprold, 0x6672, 1, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D2|VexW= =3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, R= egXMM|RegYMM|RegZMM } -vprord, 0x6672, 0, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D2|VexW= =3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, R= egXMM|RegYMM|RegZMM } - -vprolq, 0x6672, 1, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D2|VexW= =3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, R= egXMM|RegYMM|RegZMM } -vprorq, 0x6672, 0, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D2|VexW= =3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, R= egXMM|RegYMM|RegZMM } +vprol, 0x6672, 1, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D2||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf= |No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseI= ndex, RegXMM|RegYMM|RegZMM } +vpror, 0x6672, 0, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D2||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf= |No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseI= ndex, RegXMM|RegYMM|RegZMM } =20 vpscatterqd, 0x66A1, None, CpuAVX512F, Modrm|EVex=3D1|Masking=3D2|NoDefMas= k|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { RegYMM, Dword|Unspecified|BaseIndex } vscatterqps, 0x66A3, None, CpuAVX512F, Modrm|EVex=3D1|Masking=3D2|NoDefMas= k|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sS= uf|No_qSuf|No_ldSuf, { RegYMM, Dword|Unspecified|BaseIndex } =20 vpshufd, 0x6670, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexW=3D1|Broa= dcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_= ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|Reg= YMM|RegZMM } =20 -vpslld, 0x66F2, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|VexW0|= Disp8MemShift=3D4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_l= dSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|R= egZMM } -vpslld, 0x6672, 6, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D2|VexW= =3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, R= egXMM|RegYMM|RegZMM } -vpsrad, 0x66E2, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|Ve= xW=3D1|Disp8MemShift=3D4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS= uf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|R= egYMM|RegZMM } -vpsrad, 0x6672, 4, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D2|VexW= =3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, R= egXMM|RegYMM|RegZMM } -vpsrld, 0x66D2, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|Ve= xW=3D1|Disp8MemShift=3D4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS= uf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|R= egYMM|RegZMM } -vpsrld, 0x6672, 2, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D2|VexW= =3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, R= egXMM|RegYMM|RegZMM } - -vpsllq, 0x66F3, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|Ve= xW=3D2|Disp8MemShift=3D4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS= uf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|R= egYMM|RegZMM } -vpsllq, 0x6673, 6, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D2|VexW= =3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, R= egXMM|RegYMM|RegZMM } -vpsraq, 0x66E2, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|Ve= xW=3D2|Disp8MemShift=3D4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS= uf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|R= egYMM|RegZMM } -vpsraq, 0x6672, 4, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D2|VexW= =3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, R= egXMM|RegYMM|RegZMM } -vpsrlq, 0x66D3, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D1|Ve= xW=3D2|Disp8MemShift=3D4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS= uf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|R= egYMM|RegZMM } -vpsrlq, 0x6673, 2, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D2|VexW= =3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, R= egXMM|RegYMM|RegZMM } +vpsll, 0x66f2 | , None, CpuAVX512F, Modrm|Masking=3D3|Space0F|= VexVVVV||Disp8MemShift=3D4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No= _sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZM= M, RegXMM|RegYMM|RegZMM } +vpsll, 0x6672 | , 6, CpuAVX512F, Modrm|Masking=3D3|Space0F|Vex= VVVV=3D2||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_l= Suf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspec= ified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpsra, 0x66e2, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV||Disp8MemShift=3D4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS= uf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|R= egYMM|RegZMM } +vpsra, 0x6672, 4, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV=3D2||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf= |No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseI= ndex, RegXMM|RegYMM|RegZMM } +vpsrl, 0x66d2 | , None, CpuAVX512F, Modrm|Masking=3D3|Space0F|= VexVVVV||Disp8MemShift=3D4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No= _sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZM= M, RegXMM|RegYMM|RegZMM } +vpsrl, 0x6672 | , 2, CpuAVX512F, Modrm|Masking=3D3|Space0F|Vex= VVVV=3D2||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_l= Suf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspec= ified|BaseIndex, RegXMM|RegYMM|RegZMM } =20 vrcp14p, 0x664C, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q= Suf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXM= M|RegYMM|RegZMM } vrcp14s, 0x664D, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D3|Space0F38= |VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No= _ldSuf, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } @@ -2490,11 +2427,9 @@ vunpcklp, 0x14, None, CpuAVX512F, Modrm= |Masking=3D3|Space0F|VexVVVV|< vpbroadcastmb2q, 0xF32A, None, CpuAVX512CD, Modrm|Space0F38|EVex=3D5|VexW= =3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegXMM|Re= gYMM|RegZMM } vpbroadcastmw2d, 0xF33A, None, CpuAVX512CD, Modrm|Space0F38|EVex=3D5|VexW= =3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegXMM|Re= gYMM|RegZMM } =20 -vpconflictd, 0x66C4, None, CpuAVX512CD, Modrm|Masking=3D3|Space0F38|VexW= =3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|= RegYMM|RegZMM } -vpconflictq, 0x66C4, None, CpuAVX512CD, Modrm|Masking=3D3|Space0F38|VexW= =3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|= RegYMM|RegZMM } +vpconflict, 0x66c4, None, CpuAVX512CD, Modrm|Masking=3D3|Space0F38||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|= No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, R= egXMM|RegYMM|RegZMM } =20 -vplzcntd, 0x6644, None, CpuAVX512CD, Modrm|Masking=3D3|Space0F38|VexW=3D1|= Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf= |No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYM= M|RegZMM } -vplzcntq, 0x6644, None, CpuAVX512CD, Modrm|Masking=3D3|Space0F38|VexW=3D2|= Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf= |No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYM= M|RegZMM } +vplzcnt, 0x6644, None, CpuAVX512CD, Modrm|Masking=3D3|Space0F38||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_= qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegX= MM|RegYMM|RegZMM } =20 // AVX512CD instructions end. =20 @@ -2570,10 +2505,10 @@ vgatherdpd, 0x6692, None, CpuAVX512F|CpuAVX512VL, M= odrm|Masking=3D2|NoDefMask|Spac vgatherqp, 0x6693, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking= =3D2|NoDefMask|Space0F38||Disp8MemShift|VecSIB128|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { |Unspecified|BaseIndex, RegXMM= } vgatherqpd, 0x6693, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D3|Masking= =3D2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3D3|VecSIB256|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegYMM } vpgatherdq, 0x6690, None, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3D2|NoDefM= ask|Space0F38|VexW1|Disp8MemShift=3D3|VecSIB128|No_bSuf|No_wSuf|No_lSuf|No_= sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM|RegYMM } -vpgatherqq, 0x6691, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D2|Masking= =3D2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3D3|VecSIB128|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM } +vpgatherq, 0x6691, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking= =3D2|NoDefMask|Space0F38||Disp8MemShift|VecSIB128|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { |Unspecified|BaseIndex, RegXMM= } vpgatherqq, 0x6691, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D3|Masking= =3D2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3D3|VecSIB256|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegYMM } vpscatterdq, 0x66A0, None, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3D2|NoDef= Mask|Space0F38|VexW1|Disp8MemShift=3D3|VecSIB128|No_bSuf|No_wSuf|No_lSuf|No= _sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex } -vpscatterqq, 0x66A1, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D2|Masking= =3D2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3D3|VecSIB128|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex } +vpscatterq, 0x66A1, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Maskin= g=3D2|NoDefMask|Space0F38||Disp8MemShift|VecSIB128|No_bSuf|No_wSuf= |No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, |Unspecified|BaseInde= x } vpscatterqq, 0x66A1, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D3|Masking= =3D2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3D3|VecSIB256|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Qword|Unspecified|BaseIndex } vscatterdpd, 0x66A2, None, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3D2|NoDef= Mask|Space0F38|VexW1|Disp8MemShift=3D3|VecSIB128|No_bSuf|No_wSuf|No_lSuf|No= _sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex } vscatterqp, 0x66A3, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Maskin= g=3D2|NoDefMask|Space0F38||Disp8MemShift|VecSIB128|No_bSuf|No_wSuf= |No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, |Unspecified|BaseInde= x } @@ -2584,11 +2519,9 @@ vgatherdps, 0x6692, None, CpuAVX512F|CpuAVX512VL, Mo= drm|EVex=3D3|Masking=3D2|NoDefMa vgatherqps, 0x6693, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D3|Masking= =3D2|NoDefMask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB256|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM } vpgatherdd, 0x6690, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D2|Masking= =3D2|NoDefMask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB128|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM } vpgatherdd, 0x6690, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D3|Masking= =3D2|NoDefMask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB256|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegYMM } -vpgatherqd, 0x6691, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D2|Masking= =3D2|NoDefMask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB128|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM } vpgatherqd, 0x6691, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D3|Masking= =3D2|NoDefMask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB256|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM } vpscatterdd, 0x66A0, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D2|Masking= =3D2|NoDefMask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB128|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex } vpscatterdd, 0x66A0, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D3|Masking= =3D2|NoDefMask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB256|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Dword|Unspecified|BaseIndex } -vpscatterqd, 0x66A1, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D2|Masking= =3D2|NoDefMask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB128|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex } vpscatterqd, 0x66A1, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D3|Masking= =3D2|NoDefMask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB256|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex } vscatterdps, 0x66A2, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D2|Masking= =3D2|NoDefMask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB128|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex } vscatterdps, 0x66A2, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3D3|Masking= =3D2|NoDefMask|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB256|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Dword|Unspecified|BaseIndex } @@ -2699,38 +2632,22 @@ vpmovzxwq, 0x6634, None, CpuAVX512F|CpuAVX512VL, Mo= drm|EVex=3D3|Masking=3D3|Space0F3 =20 // AVX512BW instructions. =20 -kaddd, 0x664A, None, CpuAVX512BW, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW= =3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, = RegMask } -kandd, 0x6641, None, CpuAVX512BW, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW= =3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, = RegMask } -kandnd, 0x6642, None, CpuAVX512BW, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW= =3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegMask, = RegMask, RegMask } -kmovd, 0x6690, None, CpuAVX512BW, Modrm|Vex=3D1|Space0F|VexW1|No_bSuf|No_w= Suf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask|Dword|Unspecified|BaseIndex= , RegMask } -kmovd, 0x6691, None, CpuAVX512BW, Modrm|Vex=3D1|Space0F|VexW=3D2|IgnoreSiz= e|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, Dword|Unspec= ified|BaseIndex } -kmovd, 0xF292, None, CpuAVX512BW, D|Modrm|Vex=3D1|Space0F|No_bSuf|No_wSuf|= No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, RegMask } -knotd, 0x6644, None, CpuAVX512BW, Modrm|Vex=3D1|Space0F|VexW=3D2|No_bSuf|N= o_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask } -kord, 0x6645, None, CpuAVX512BW, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW=3D= 2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, Reg= Mask } -kortestd, 0x6698, None, CpuAVX512BW, Modrm|Vex=3D1|Space0F|VexW=3D2|No_bSu= f|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask } -ktestd, 0x6699, None, CpuAVX512BW, Modrm|Vex=3D1|Space0F|VexW=3D2|No_bSuf|= No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask } -kxnord, 0x6646, None, CpuAVX512BW, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW= =3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, = RegMask } -kxord, 0x6647, None, CpuAVX512BW, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW= =3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegMask, = RegMask, RegMask } - -kaddq, 0x4A, None, CpuAVX512BW, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW=3D2= |No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegM= ask } -kandnq, 0x42, None, CpuAVX512BW, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW=3D= 2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegMask, Reg= Mask, RegMask } -kandq, 0x41, None, CpuAVX512BW, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW=3D2= |No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegM= ask } -kmovq, 0x90, None, CpuAVX512BW, Modrm|Vex=3D1|Space0F|VexW1|No_bSuf|No_wSu= f|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask|Qword|Unspecified|BaseIndex, = RegMask } -kmovq, 0x91, None, CpuAVX512BW, Modrm|Vex=3D1|Space0F|VexW=3D2|IgnoreSize|= No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, Qword|Unspecif= ied|BaseIndex } -kmovq, 0xF292, None, CpuAVX512BW, D|Modrm|Vex=3D1|Space0F|VexW=3D2|No_bSuf= |No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg64, RegMask } -knotq, 0x44, None, CpuAVX512BW, Modrm|Vex=3D1|Space0F|VexW=3D2|No_bSuf|No_= wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask } -korq, 0x45, None, CpuAVX512BW, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW=3D2|= No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMa= sk } -kortestq, 0x98, None, CpuAVX512BW, Modrm|Vex=3D1|Space0F|VexW=3D2|No_bSuf|= No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask } -ktestq, 0x99, None, CpuAVX512BW, Modrm|Vex=3D1|Space0F|VexW=3D2|No_bSuf|No= _wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask } +kadd, 0x4a, None, CpuAVX512BW, Modrm|Vex256|Space0F|VexVVVV|V= exW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, = RegMask } +kand, 0x41, None, CpuAVX512BW, Modrm|Vex256|Space0F|VexVVVV|V= exW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, = RegMask } +kandn, 0x42, None, CpuAVX512BW, Modrm|Vex256|Space0F|VexVVVV|= VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegMask,= RegMask, RegMask } +kmov, 0x90, None, CpuAVX512BW, Modrm|Vex128|Space0F|VexW1|No_= bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask||Unspecif= ied|BaseIndex, RegMask } +kmov, 0x91, None, CpuAVX512BW, Modrm|Vex128|Space0F|VexW1|Ign= oreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, |Unspecified|BaseIndex } +kmov, 0xf292, None, CpuAVX512BW, D|Modrm|Vex128|Space0F||No= _bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { , RegMask } +knot, 0x44, None, CpuAVX512BW, Modrm|Vex128|Space0F|VexW1|No_= bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask } +kor, 0x45, None, CpuAVX512BW, Modrm|Vex256|Space0F|VexVVVV|Ve= xW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, R= egMask } +kortest, 0x98, None, CpuAVX512BW, Modrm|Vex128|Space0F|VexW1|= No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask } +ktest, 0x99, None, CpuAVX512BW, Modrm|Vex128|Space0F|VexW1|No= _bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask } +kxnor, 0x46, None, CpuAVX512BW, Modrm|Vex256|Space0F|VexVVVV|= VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask,= RegMask } +kxor, 0x47, None, CpuAVX512BW, Modrm|Vex256|Space0F|VexVVVV|V= exW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegMask, = RegMask, RegMask } kunpckdq, 0x4B, None, CpuAVX512BW, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW= =3D2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, = RegMask } kunpckwd, 0x4B, None, CpuAVX512BW, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW= =3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, = RegMask } -kxnorq, 0x46, None, CpuAVX512BW, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW=3D= 2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, Reg= Mask } -kxorq, 0x47, None, CpuAVX512BW, Modrm|Vex=3D2|Space0F|VexVVVV=3D1|VexW=3D2= |No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegMask, RegM= ask, RegMask } - -kshiftld, 0x6633, None, CpuAVX512BW, Modrm|Vex=3D1|Space0F3A|VexW=3D1|No_b= Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMask, RegMask } -kshiftlq, 0x6633, None, CpuAVX512BW, Modrm|Vex=3D1|Space0F3A|VexW=3D2|No_b= Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMask, RegMask } -kshiftrd, 0x6631, None, CpuAVX512BW, Modrm|Vex=3D1|Space0F3A|VexW=3D1|No_b= Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMask, RegMask } -kshiftrq, 0x6631, None, CpuAVX512BW, Modrm|Vex=3D1|Space0F3A|VexW=3D2|No_b= Suf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMask, RegMask } +kshiftl, 0x6633, None, CpuAVX512BW, Modrm|Vex128|Space0F3A||N= o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMask, RegMask } +kshiftr, 0x6631, None, CpuAVX512BW, Modrm|Vex128|Space0F3A||N= o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMask, RegMask } =20 vdbpsadbw, 0x6642, None, CpuAVX512BW, Modrm|Masking=3D3|Space0F3A|VexVVVV= =3D1|VexW=3D1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_= qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|R= egYMM|RegZMM, RegXMM|RegYMM|RegZMM } =20 @@ -2945,11 +2862,8 @@ vextracti32x8, 0x663B, None, CpuAVX512DQ, Modrm|EVex= =3D1|MaskingMorZ|Space0F3A|Vex vinsertf32x8, 0x661A, None, CpuAVX512DQ, Modrm|EVex=3D1|Masking=3D3|Space0= F3A|VexVVVV=3D1|VexW=3D1|Disp8MemShift=3D5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|= No_qSuf|No_ldSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM } vinserti32x8, 0x663A, None, CpuAVX512DQ, Modrm|EVex=3D1|Masking=3D3|Space0= F3A|VexVVVV=3D1|VexW=3D1|Disp8MemShift=3D5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|= No_qSuf|No_ldSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM } =20 -vpextrd, 0x6616, None, CpuAVX512DQ, Modrm|EVex128|Space0F3A|Disp8MemShift= =3D2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, R= egXMM, Reg32|Dword|Unspecified|BaseIndex } -vpinsrd, 0x6622, None, CpuAVX512DQ, Modrm|EVex128|Space0F3A|VexVVVV=3D1|Di= sp8MemShift=3D2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf= , { Imm8, Reg32|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } - -vpextrq, 0x6616, None, CpuAVX512DQ|Cpu64, Modrm|EVex128|Space0F3A|VexW1|Di= sp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, R= egXMM, Reg64|Unspecified|BaseIndex } -vpinsrq, 0x6622, None, CpuAVX512DQ|Cpu64, Modrm|EVex128|Space0F3A|VexVVVV= =3D1|VexW1|Disp8MemShift=3D3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS= uf, { Imm8, Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } +vpextr, 0x6616, None, CpuAVX512DQ|, Modrm|EVex128|Space0F3A|= |Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,= { Imm8, RegXMM, |Unspecified|BaseIndex } +vpinsr, 0x6622, None, CpuAVX512DQ|, Modrm|EVex128|Space0F3A|= VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N= o_ldSuf, { Imm8, |Unspecified|BaseIndex, RegXMM, RegXMM } =20 vextractf64x2, 0x6619, None, CpuAVX512DQ, Modrm|MaskingMorZ|Space0F3A|VexW= =3D2|Disp8MemShift=3D4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { = Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } vextracti64x2, 0x6639, None, CpuAVX512DQ, Modrm|MaskingMorZ|Space0F3A|VexW= =3D2|Disp8MemShift=3D4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { = Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } @@ -2963,11 +2877,8 @@ vfpclasspx, 0x6666, None, CpuAVX512DQ|CpuAVX512V= L, Modrm|EVex128|Masking=3D2|S vfpclasspy, 0x6666, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex256|Maski= ng=3D2|Space0F3A||Broadcast|Disp8MemShift=3D5|No_bSuf|No_wSuf|No_l= Suf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM||Unspecified|BaseInde= x, RegMask } vfpclasss, 0x67, None, , Modrm|EVexLIG|Masking=3D= 2|Space0F3A||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu= f|No_ldSuf, { Imm8, RegXMM||Unspecified|BaseIndex, RegMask } =20 -vpmovd2m, 0xF339, None, CpuAVX512DQ, Modrm|EVex=3D5|Space0F38|VexW=3D1|No_= bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegM= ask } -vpmovq2m, 0xF339, None, CpuAVX512DQ, Modrm|EVex=3D5|Space0F38|VexW=3D2|No_= bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegM= ask } - -vpmovm2d, 0xF338, None, CpuAVX512DQ, Modrm|EVex=3D5|Space0F38|VexW=3D1|No_= bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegXMM|RegYMM|Reg= ZMM } -vpmovm2q, 0xF338, None, CpuAVX512DQ, Modrm|EVex=3D5|Space0F38|VexW=3D2|No_= bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegXMM|RegYMM|Reg= ZMM } +vpmov2m, 0xf339, None, CpuAVX512DQ, Modrm|EVexDYN|Space0F38||= No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, R= egMask } +vpmovm2, 0xf338, None, CpuAVX512DQ, Modrm|EVexDYN|Space0F38||= No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegXMM|RegYMM|= RegZMM } =20 vpmullq, 0x6640, None, CpuAVX512DQ, Modrm|Masking=3D3|Space0F38|VexVVVV=3D= 1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_s= Suf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, R= egXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } =20 @@ -3019,8 +2930,7 @@ vp4dpwssds, 0xf253, None, CpuAVX512_4VNNIW, Modrm|EVe= x=3D1|Masking=3D3|Space0F38|Vex =20 // AVX512_VPOPCNTDQ instructions =20 -vpopcntd, 0x6655, None, CpuAVX512_VPOPCNTDQ, Modrm|Masking=3D3|Space0F38|V= exW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf= |No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegX= MM|RegYMM|RegZMM } -vpopcntq, 0x6655, None, CpuAVX512_VPOPCNTDQ, Modrm|Masking=3D3|Space0F38|V= exW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf= |No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegX= MM|RegYMM|RegZMM } +vpopcnt, 0x6655, None, CpuAVX512_VPOPCNTDQ, Modrm|Masking=3D3|Space0F3= 8||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_= sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseInd= ex, RegXMM|RegYMM|RegZMM } =20 // AVX512_VPOPCNTDQ instructions end =20 @@ -3032,23 +2942,17 @@ vpcompressw, 0x6663, None, CpuAVX512_VBMI2, Modrm|M= askingMorZ|Space0F38|VexW=3D2|D vpexpandb, 0x6662, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F38|VexW= =3D1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXM= M|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } vpexpandw, 0x6662, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F38|VexW= =3D2|Disp8MemShift=3D1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf= |No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZ= MM } =20 -vpshldvd, 0x6671, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F38|VexVV= VV=3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf= |No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseInd= ex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpshrdvd, 0x6673, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F38|VexVV= VV=3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf= |No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseInd= ex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } - -vpshldvq, 0x6671, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F38|VexVV= VV=3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf= |No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseInd= ex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpshrdvq, 0x6673, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F38|VexVV= VV=3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf= |No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseInd= ex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } - -vpshldvw, 0x6670, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F38|VexVV= VV=3D1|VexW=3D2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N= o_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYM= M|RegZMM, RegXMM|RegYMM|RegZMM } -vpshrdvw, 0x6672, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F38|VexVV= VV=3D1|VexW=3D2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N= o_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYM= M|RegZMM, RegXMM|RegYMM|RegZMM } +vpshldv, 0x6671, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F38|Ve= xVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf= |No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|Bas= eIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpshldvw, 0x6670, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F38|VexVV= VV|VexW1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|= No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZM= M, RegXMM|RegYMM|RegZMM } =20 -vpshldd, 0x6671, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F3A|VexVVV= V=3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|= No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|Ba= seIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpshrdd, 0x6673, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F3A|VexVVV= V=3D1|VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|= No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|Ba= seIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpshrdv, 0x6673, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F38|Ve= xVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf= |No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|Bas= eIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpshrdvw, 0x6672, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F38|VexVV= VV|VexW1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|= No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZM= M, RegXMM|RegYMM|RegZMM } =20 -vpshldq, 0x6671, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F3A|VexVVV= V=3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|= No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|Ba= seIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpshrdq, 0x6673, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F3A|VexVVV= V=3D1|VexW=3D2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|= No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|Ba= seIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpshld, 0x6671, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F3A|Vex= VVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|= No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecifie= d|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpshldw, 0x6670, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F3A|VexVVV= V|VexW1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N= o_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|= RegZMM, RegXMM|RegYMM|RegZMM } =20 -vpshldw, 0x6670, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F3A|VexVVV= V=3D1|VexW=3D2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|= RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpshrdw, 0x6672, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F3A|VexVVV= V=3D1|VexW=3D2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No= _qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|= RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpshrd, 0x6673, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F3A|Vex= VVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|= No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecifie= d|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpshrdw, 0x6672, None, CpuAVX512_VBMI2, Modrm|Masking=3D3|Space0F3A|VexVVV= V|VexW1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N= o_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|= RegZMM, RegXMM|RegYMM|RegZMM } =20 // AVX512_VBMI2 instructions end =20 @@ -3242,8 +3146,7 @@ enqcmds, 0xf30f38f8, None, CpuENQCMD, Modrm|AddrPrefi= xOpReg, { Unspecified|BaseI =20 // VP2INTERSECT instructions. =20 -vp2intersectd, 0xf268, None, CpuAVX512_VP2INTERSECT, Modrm|Space0F38|VexVV= VV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSu= f|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, Reg= XMM|RegYMM|RegZMM, RegMask } -vp2intersectq, 0xf268, None, CpuAVX512_VP2INTERSECT, Modrm|Space0F38|VexVV= VV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSu= f|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, Reg= XMM|RegYMM|RegZMM, RegMask } +vp2intersect, 0xf268, None, CpuAVX512_VP2INTERSECT, Modrm|Space0F38|Ve= xVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf= |No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|Bas= eIndex, RegXMM|RegYMM|RegZMM, RegMask } =20 // VP2INTERSECT instructions end. =20 diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index d32312eca88..325dba6089b 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -11206,7 +11206,7 @@ const insn_template i386_optab[] =3D 0, 0, 0, 0, 0, 0 } }, { { 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "pslld", 0xf2, 2, None, + { "pslld", 0xf2 | 0, 2, None, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, @@ -11221,7 +11221,7 @@ const insn_template i386_optab[] =3D 1, 0, 0, 0, 1, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } } } }, - { "pslld", 0xf2, 2, None, + { "pslld", 0xf2 | 0, 2, None, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, @@ -11236,7 +11236,7 @@ const insn_template i386_optab[] =3D 1, 0, 0, 0, 1, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } } } }, - { "pslld", 0xf2, 2, None, + { "pslld", 0xf2 | 0, 2, None, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, @@ -11251,7 +11251,7 @@ const insn_template i386_optab[] =3D 0, 0, 0, 0, 1, 0 } }, { { 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "pslld", 0x72, 2, 6, + { "pslld", 0x72 | 0, 2, 6, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, @@ -11266,7 +11266,7 @@ const insn_template i386_optab[] =3D 0, 0, 0, 0, 0, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } } } }, - { "pslld", 0x72, 2, 6, + { "pslld", 0x72 | 0, 2, 6, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, @@ -11281,7 +11281,7 @@ const insn_template i386_optab[] =3D 0, 0, 0, 0, 0, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } } } }, - { "pslld", 0x72, 2, 6, + { "pslld", 0x72 | 0, 2, 6, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, @@ -11296,7 +11296,7 @@ const insn_template i386_optab[] =3D 0, 0, 0, 0, 0, 0 } }, { { 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "psllq", 0xf3, 2, None, + { "psllq", 0xf2 | 1, 2, None, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, @@ -11311,7 +11311,7 @@ const insn_template i386_optab[] =3D 1, 0, 0, 0, 1, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } } } }, - { "psllq", 0xf3, 2, None, + { "psllq", 0xf2 | 1, 2, None, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, @@ -11326,7 +11326,7 @@ const insn_template i386_optab[] =3D 1, 0, 0, 0, 1, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } } } }, - { "psllq", 0xf3, 2, None, + { "psllq", 0xf2 | 1, 2, None, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, @@ -11341,7 +11341,7 @@ const insn_template i386_optab[] =3D 0, 0, 0, 0, 1, 0 } }, { { 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "psllq", 0x73, 2, 6, + { "psllq", 0x72 | 1, 2, 6, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, @@ -11356,7 +11356,7 @@ const insn_template i386_optab[] =3D 0, 0, 0, 0, 0, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } } } }, - { "psllq", 0x73, 2, 6, + { "psllq", 0x72 | 1, 2, 6, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, @@ -11371,7 +11371,7 @@ const insn_template i386_optab[] =3D 0, 0, 0, 0, 0, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } } } }, - { "psllq", 0x73, 2, 6, + { "psllq", 0x72 | 1, 2, 6, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, @@ -11656,7 +11656,7 @@ const insn_template i386_optab[] =3D 0, 0, 0, 0, 0, 0 } }, { { 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "psrld", 0xd2, 2, None, + { "psrld", 0xd2 | 0, 2, None, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, @@ -11671,7 +11671,7 @@ const insn_template i386_optab[] =3D 1, 0, 0, 0, 1, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } } } }, - { "psrld", 0xd2, 2, None, + { "psrld", 0xd2 | 0, 2, None, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, @@ -11686,7 +11686,7 @@ const insn_template i386_optab[] =3D 1, 0, 0, 0, 1, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } } } }, - { "psrld", 0xd2, 2, None, + { "psrld", 0xd2 | 0, 2, None, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, @@ -11701,7 +11701,7 @@ const insn_template i386_optab[] =3D 0, 0, 0, 0, 1, 0 } }, { { 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "psrld", 0x72, 2, 2, + { "psrld", 0x72 | 0, 2, 2, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, @@ -11716,7 +11716,7 @@ const insn_template i386_optab[] =3D 0, 0, 0, 0, 0, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } } } }, - { "psrld", 0x72, 2, 2, + { "psrld", 0x72 | 0, 2, 2, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, @@ -11731,7 +11731,7 @@ const insn_template i386_optab[] =3D 0, 0, 0, 0, 0, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } } } }, - { "psrld", 0x72, 2, 2, + { "psrld", 0x72 | 0, 2, 2, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, @@ -11746,7 +11746,7 @@ const insn_template i386_optab[] =3D 0, 0, 0, 0, 0, 0 } }, { { 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "psrlq", 0xd3, 2, None, + { "psrlq", 0xd2 | 1, 2, None, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, @@ -11761,7 +11761,7 @@ const insn_template i386_optab[] =3D 1, 0, 0, 0, 1, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } } } }, - { "psrlq", 0xd3, 2, None, + { "psrlq", 0xd2 | 1, 2, None, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, @@ -11776,7 +11776,7 @@ const insn_template i386_optab[] =3D 1, 0, 0, 0, 1, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } } } }, - { "psrlq", 0xd3, 2, None, + { "psrlq", 0xd2 | 1, 2, None, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, @@ -11791,7 +11791,7 @@ const insn_template i386_optab[] =3D 0, 0, 0, 0, 1, 0 } }, { { 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "psrlq", 0x73, 2, 2, + { "psrlq", 0x72 | 1, 2, 2, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, @@ -11806,7 +11806,7 @@ const insn_template i386_optab[] =3D 0, 0, 0, 0, 0, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } } } }, - { "psrlq", 0x73, 2, 2, + { "psrlq", 0x72 | 1, 2, 2, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, @@ -11821,7 +11821,7 @@ const insn_template i386_optab[] =3D 0, 0, 0, 0, 0, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } } } }, - { "psrlq", 0x73, 2, 2, + { "psrlq", 0x72 | 1, 2, 2, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, @@ -31690,7 +31690,7 @@ const insn_template i386_optab[] =3D 1, 1, 0, 0, 1, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0 } } } }, - { "vpabsd", 0x1e, 2, None, + { "vpabsd", 0x1e | 0, 2, None, { 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 1, 0, 0, 0, 0, 3, 3, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0 }, @@ -35368,7 +35368,7 @@ const insn_template i386_optab[] =3D 1, 1, 0, 0, 0, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0 } } } }, - { "vpslld", 0x72, 3, 6, + { "vpslld", 0x72 | 0, 3, 6, { 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, [...] [diff truncated at 100000 bytes]