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From: Jan Beulich <jbeulich@sourceware.org>
To: bfd-cvs@sourceware.org
Subject: [binutils-gdb] x86: shorten certain template names
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https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D390ddd6f6812=
474f1d0cfd5447bc12b8dcba2071

commit 390ddd6f6812474f1d0cfd5447bc12b8dcba2071
Author: Jan Beulich <jbeulich@suse.com>
Date:   Tue Aug 16 09:15:15 2022 +0200

    x86: shorten certain template names
   =20
    Now that we can purge templates, let's use this to improve readability a
    little by shortening a few of their names, making functionally similar
    ones also have identical names in their multiple incarnations.

Diff:
---
 opcodes/i386-opc.tbl | 58 +++++++++++++++++++++++++++++-------------------=
----
 1 file changed, 32 insertions(+), 26 deletions(-)

diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index f151ba6c683..eace12c8832 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -1056,14 +1056,14 @@ pxor<mmx>, 0x<mmx:pfx>0fef, None, <mmx:cpu>, Modrm|=
<mmx:attr>|C|No_bSuf|No_wSuf|
 <sse:cpu:attr:scal:vvvv, +
     $avx:CpuAVX:Vex128|VexW0|SSE2AVX:VexLIG|VexW0|SSE2AVX:VexVVVV, +
     $sse:CpuSSE::IgnoreSize:>
-<sse_frel:imm:comm, eq:0:C, lt:1:, le:2:, unord:3:C, neq:4:C, nlt:5:, nle:=
6:, ord:7:C>
+<frel:imm:comm, eq:0:C, lt:1:, le:2:, unord:3:C, neq:4:C, nlt:5:, nle:6:, =
ord:7:C>
=20
 addps<sse>, 0x0f58, None, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|No_bSuf|N=
o_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, Re=
gXMM }
 addss<sse>, 0xf30f58, None, <sse:cpu>, Modrm|<sse:scal>|<sse:vvvv>|No_bSuf=
|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Re=
gXMM, RegXMM }
 andnps<sse>, 0x0f55, None, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|No_bSuf|=
No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, R=
egXMM }
 andps<sse>, 0x0f54, None, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|C|No_bSuf=
|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, =
RegXMM }
-cmp<sse_frel>ps<sse>, 0x0fc2, <sse_frel:imm>, <sse:cpu>, Modrm|<sse:attr>|=
<sse:vvvv>|<sse_frel:comm>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf=
|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
-cmp<sse_frel>ss<sse>, 0xf30fc2, <sse_frel:imm>, <sse:cpu>, Modrm|<sse:scal=
>|<sse:vvvv>|<sse_frel:comm>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS=
uf|ImmExt, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM }
+cmp<frel>ps<sse>, 0x0fc2, <frel:imm>, <sse:cpu>, Modrm|<sse:attr>|<sse:vvv=
v>|<frel:comm>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { R=
egXMM|Unspecified|BaseIndex, RegXMM }
+cmp<frel>ss<sse>, 0xf30fc2, <frel:imm>, <sse:cpu>, Modrm|<sse:scal>|<sse:v=
vvv>|<frel:comm>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, {=
 RegXMM|Dword|Unspecified|BaseIndex, RegXMM }
 cmpps<sse>, 0x0fc2, None, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|No_bSuf|N=
o_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseInd=
ex, RegXMM }
 cmpss<sse>, 0xf30fc2, None, <sse:cpu>, Modrm|<sse:scal>|<sse:vvvv>|No_bSuf=
|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|Unspecified|BaseIn=
dex|RegXMM, RegXMM }
 comiss<sse>, 0x0f2f, None, <sse:cpu>, Modrm|<sse:scal>|No_bSuf|No_wSuf|No_=
lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM=
 }
@@ -1156,8 +1156,8 @@ addpd<sse2>, 0x660f58, None, <sse2:cpu>, Modrm|<sse2:=
attr>|<sse2:vvvv>|No_bSuf|N
 addsd<sse2>, 0xf20f58, None, <sse2:cpu>, Modrm|<sse2:scal>|<sse2:vvvv>|No_=
bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseInde=
x|RegXMM, RegXMM }
 andnpd<sse2>, 0x660f55, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|No=
_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIn=
dex, RegXMM }
 andpd<sse2>, 0x660f54, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|C|N=
o_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseI=
ndex, RegXMM }
-cmp<sse_frel>pd<sse2>, 0x660fc2, <sse_frel:imm>, <sse2:cpu>, Modrm|<sse2:a=
ttr>|<sse2:vvvv>|<sse_frel:comm>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No=
_ldSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM }
-cmp<sse_frel>sd<sse2>, 0xf20fc2, <sse_frel:imm>, <sse2:cpu>, Modrm|<sse2:s=
cal>|<sse2:vvvv>|<sse_frel:comm>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No=
_ldSuf|ImmExt, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
+cmp<frel>pd<sse2>, 0x660fc2, <frel:imm>, <sse2:cpu>, Modrm|<sse2:attr>|<ss=
e2:vvvv>|<frel:comm>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmEx=
t, { RegXMM|Unspecified|BaseIndex, RegXMM }
+cmp<frel>sd<sse2>, 0xf20fc2, <frel:imm>, <sse2:cpu>, Modrm|<sse2:scal>|<ss=
e2:vvvv>|<frel:comm>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmEx=
t, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
 cmppd<sse2>, 0x660fc2, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|No_=
bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|B=
aseIndex, RegXMM }
 cmpsd<sse2>, 0xf20fc2, None, <sse2:cpu>, Modrm|<sse2:scal>|<sse2:vvvv>|No_=
bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Qword|Unspecified|Ba=
seIndex|RegXMM, RegXMM }
 comisd<sse2>, 0x660f2f, None, <sse2:cpu>, Modrm|<sse2:scal>|No_bSuf|No_wSu=
f|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, R=
egXMM }
@@ -1232,6 +1232,8 @@ psrldq<sse2>, 0x660f73, 3, <sse2:cpu>, Modrm|<sse2:sh=
imm>|No_bSuf|No_wSuf|No_lSu
 punpckhqdq<sse2>, 0x660f6d, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv=
>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|Ba=
seIndex, RegXMM }
 punpcklqdq<sse2>, 0x660f6c, None, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv=
>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|Ba=
seIndex, RegXMM }
=20
+<frel>
+
 // SSE3 instructions.
=20
 <sse3:cpu:attr:vvvv, $avx:CpuAVX:Vex128|VexW0|SSE2AVX:VexVVVV, $sse:CpuSSE=
3::>
@@ -1457,7 +1459,7 @@ gf2p8mulb<gfni>, 0x660f38cf, None, <gfni:cpu>CpuGFNI,=
 Modrm|<gfni:w0>|No_bSuf|No
=20
 // AVX instructions.
=20
-<avx_frel:imm:comm, eq:00:C, eq_oq:00:C, lt:01:, lt_os:01:, le:02:, le_os:=
02:, +
+<frel:imm:comm, eq:00:C, eq_oq:00:C, lt:01:, lt_os:01:, le:02:, le_os:02:,=
 +
     unord:03:C, unord_q:03:C, neq:04:C, neq_uq:04:C, nlt:05:, nlt_us:05:, +
     nle:06:, nle_us:06:, ord:07:C, ord_q:07:C, eq_uq:08:C, +
     nge:09:, nge_us:09:, ngt:0a:, ngt_us:0a:, false:0b:C, false_oq:0b:C, +
@@ -1484,8 +1486,8 @@ vblendvp<sd>, 0x664a | <sd:opc>, None, CpuAVX, Modrm|=
Vex|Space0F3A|VexVVVV|VexW0
 vbroadcastf128, 0x661a, None, CpuAVX, Modrm|Vex=3D2|Space0F38|VexW=3D1|No_=
bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIn=
dex, RegYMM }
 vbroadcastsd, 0x6619, None, CpuAVX, Modrm|Vex=3D2|Space0F38|VexW=3D1|Ignor=
eSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified=
|BaseIndex, RegYMM }
 vbroadcastss, 0x6618, None, CpuAVX, Modrm|Vex|Space0F38|VexW=3D1|IgnoreSiz=
e|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|Bas=
eIndex, RegXMM|RegYMM }
-vcmp<avx_frel>p<sd>, 0x<sd:ppfx>c2, 0x<avx_frel:imm>, CpuAVX, Modrm|<avx_f=
rel:comm>|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|Unspecified|BaseIndex, RegX=
MM|RegYMM, RegXMM|RegYMM }
-vcmp<avx_frel>s<sd>, 0x<sd:spfx>c2, 0x<avx_frel:imm>, CpuAVX, Modrm|<avx_f=
rel:comm>|VexLIG|Space0F|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_=
qSuf|No_ldSuf|ImmExt, { RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, Reg=
XMM }
+vcmp<frel>p<sd>, 0x<sd:ppfx>c2, 0x<frel:imm>, CpuAVX, Modrm|<frel:comm>|Ve=
x|Space0F|VexVVVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qS=
uf|No_ldSuf|ImmExt, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, R=
egXMM|RegYMM }
+vcmp<frel>s<sd>, 0x<sd:spfx>c2, 0x<frel:imm>, CpuAVX, Modrm|<frel:comm>|Ve=
xLIG|Space0F|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSu=
f|ImmExt, { RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM }
 vcmpp<sd>, 0x<sd:ppfx>c2, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|C=
heckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspe=
cified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
 vcmps<sd>, 0x<sd:spfx>c2, None, CpuAVX, Modrm|VexLIG|Space0F|VexVVVV|VexWI=
G|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, <sd:elem>|Unspe=
cified|BaseIndex|RegXMM, RegXMM, RegXMM }
 vcomis<sd>, 0x<sd:ppfx>2f, None, CpuAVX, Modrm|VexLIG|Space0F|VexWIG|No_bS=
uf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <sd:elem>|Unspecified|BaseIn=
dex|RegXMM, RegXMM }
@@ -1839,15 +1841,15 @@ vfnmsubs<sd>, 0x667e | <sd:opc>, None, CpuFMA4, D|M=
odrm|VexLIG|Space0F3A|VexVVVV
=20
 // XOP instructions
=20
-<xop_elem:opc, b:0, w:1, d:2, q:3>
-<xop_irel:imm, lt:0, le:1, gt:2, ge:3, eq:4, neq:5, false:6, true:7>
-<xop_sign:opc, :00, u:20>
+<xop:opc, b:0, w:1, d:2, q:3>
+<irel:imm, lt:0, le:1, gt:2, ge:3, eq:4, neq:5, false:6, true:7>
+<sign:opc, :00, u:20>
=20
 vfrczp<sd>, 0x80 | <sd:opc>, None, CpuXOP, Modrm|SpaceXOP09|VexW0|CheckReg=
Size|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Unspecified|Ba=
seIndex|RegXMM|RegYMM, RegXMM|RegYMM }
 vfrczs<sd>, 0x82 | <sd:opc>, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|=
No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { <sd:elem>|RegXMM|Unspecifie=
d|BaseIndex, RegXMM }
 vpcmov, 0xa2, None, CpuXOP, D|Modrm|SpaceXOP08|VexSources=3D2|VexVVVV|VexW=
0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegX=
MM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYM=
M }
-vpcom<xop_sign><xop_elem>, 0xcc | 0x<xop_sign:opc> | <xop_elem:opc>, None,=
 CpuXOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_s=
Suf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
-vpcom<xop_irel><xop_sign><xop_elem>, 0xcc | 0x<xop_sign:opc> | <xop_elem:o=
pc>, <xop_irel:imm>, CpuXOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|No_bSuf|=
No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Unspecified|BaseI=
ndex, RegXMM, RegXMM }
+vpcom<sign><xop>, 0xcc | 0x<sign:opc> | <xop:opc>, None, CpuXOP, Modrm|Vex=
128|SpaceXOP08|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS=
uf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
+vpcom<irel><sign><xop>, 0xcc | 0x<sign:opc> | <xop:opc>, <irel:imm>, CpuXO=
P, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No=
_qSuf|No_ldSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
 vpermil2p<sd>, 0x6648 | <sd:opc>, None, CpuXOP, Modrm|Space0F3A|VexVVVV|Ve=
xW0|Vex|VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf=
|No_ldSuf, { Imm8, RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegX=
MM|RegYMM, RegXMM|RegYMM }
 vpermil2p<sd>, 0x6648 | <sd:opc>, None, CpuXOP, Modrm|Space0F3A|VexVVVV|Ve=
xW1|Vex|VexSources=3D2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf=
|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegX=
MM|RegYMM, RegXMM|RegYMM }
 vphaddb<dq>, 0xc2 | <dq:opc>, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf=
|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseInd=
ex, RegXMM }
@@ -1874,10 +1876,14 @@ vpmacsww, 0x95, None, CpuXOP, Modrm|SpaceXOP08|VexS=
ources=3D2|VexVVVV=3D1|VexW=3D1|No_
 vpmadcsswd, 0xa6, None, CpuXOP, Modrm|SpaceXOP08|VexSources=3D2|VexVVVV=3D=
1|VexW=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, =
RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
 vpmadcswd, 0xb6, None, CpuXOP, Modrm|SpaceXOP08|VexSources=3D2|VexVVVV=3D1=
|VexW=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, R=
egXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
 vpperm, 0xa3, None, CpuXOP, D|Modrm|SpaceXOP08|VexSources=3D2|VexVVVV|VexW=
0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, RegXMM|Un=
specified|BaseIndex, RegXMM, RegXMM }
-vprot<xop_elem>, 0x90 | <xop_elem:opc>, None, CpuXOP, D|Modrm|Vex128|Space=
XOP09|VexW0|VexSources=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf=
, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM }
-vprot<xop_elem>, 0xc0 | <xop_elem:opc>, None, CpuXOP, Modrm|Vex128|SpaceXO=
P08|VexW0|VexSources=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, =
{ Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
-vpsha<xop_elem>, 0x98 | <xop_elem:opc>, None, CpuXOP, D|Modrm|Vex128|Space=
XOP09|VexW0|VexSources=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf=
, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM }
-vpshl<xop_elem>, 0x94 | <xop_elem:opc>, None, CpuXOP, D|Modrm|Vex128|Space=
XOP09|VexW0|VexSources=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf=
, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM }
+vprot<xop>, 0x90 | <xop:opc>, None, CpuXOP, D|Modrm|Vex128|SpaceXOP09|VexW=
0|VexSources=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { RegXMM=
, RegXMM|Unspecified|BaseIndex, RegXMM }
+vprot<xop>, 0xc0 | <xop:opc>, None, CpuXOP, Modrm|Vex128|SpaceXOP08|VexW0|=
VexSources=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { Imm8, Re=
gXMM|Unspecified|BaseIndex, RegXMM }
+vpsha<xop>, 0x98 | <xop:opc>, None, CpuXOP, D|Modrm|Vex128|SpaceXOP09|VexW=
0|VexSources=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { RegXMM=
, RegXMM|Unspecified|BaseIndex, RegXMM }
+vpshl<xop>, 0x94 | <xop:opc>, None, CpuXOP, D|Modrm|Vex128|SpaceXOP09|VexW=
0|VexSources=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { RegXMM=
, RegXMM|Unspecified|BaseIndex, RegXMM }
+
+<xop>
+<irel>
+<sign>
=20
 // LWP instructions
=20
@@ -2117,10 +2123,10 @@ vbroadcastsd, 0x6619, None, CpuAVX512F, Modrm|Maski=
ng=3D3|Space0F38|VexW1|Disp8Mem
 vpbroadcast<dq>, 0x6658 | <dq:opc>, None, CpuAVX512F, Modrm|Masking=3D3|Sp=
ace0F38|<dq:vexw>|Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_=
ldSuf, { RegXMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
 vpbroadcast<dq>, 0x667c, None, CpuAVX512F, Modrm|Masking=3D3|Space0F38|<dq=
:vexw64>|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { <dq:gpr>, RegX=
MM|RegYMM|RegZMM }
=20
-vcmp<avx_frel>p<sd>, 0x<sd:ppfx>C2, 0x<avx_frel:imm>, CpuAVX512F, Modrm|Ma=
sking=3D2|Space0F|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_=
bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, { RegXMM|RegYMM|R=
egZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
+vcmp<frel>p<sd>, 0x<sd:ppfx>C2, 0x<frel:imm>, CpuAVX512F, Modrm|Masking=3D=
2|Space0F|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_=
wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, { RegXMM|RegYMM|RegZMM|<s=
d:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
 vcmpp<sd>, 0x<sd:ppfx>C2, None, CpuAVX512F, Modrm|Masking=3D2|Space0F|VexV=
VVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspeci=
fied|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
=20
-vcmp<avx_frel>s<sd>, 0x<sd:spfx>C2, 0x<avx_frel:imm>, CpuAVX512F, Modrm|EV=
exLIG|Masking=3D2|Space0F|VexVVVV|<sd:vexw>|Disp8MemShift|No_bSuf|No_wSuf|N=
o_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE|ImmExt, { RegXMM|<sd:elem>|Unspecified|=
BaseIndex, RegXMM, RegMask }
+vcmp<frel>s<sd>, 0x<sd:spfx>C2, 0x<frel:imm>, CpuAVX512F, Modrm|EVexLIG|Ma=
sking=3D2|Space0F|VexVVVV|<sd:vexw>|Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|N=
o_sSuf|No_qSuf|No_ldSuf|SAE|ImmExt, { RegXMM|<sd:elem>|Unspecified|BaseInde=
x, RegXMM, RegMask }
 vcmps<sd>, 0x<sd:spfx>C2, None, CpuAVX512F, Modrm|EVexLIG|Masking=3D2|Spac=
e0F|VexVVVV|<sd:vexw>|Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf=
|No_ldSuf|SAE, { Imm8, RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegM=
ask }
=20
 vcomis<sdh>, 0x<sdh:ppfx>2f, None, <sdh:cpu>, Modrm|EVexLIG|<sdh:spc1>|<sd=
h:vexw>|Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE,=
 { RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegXMM }
@@ -2310,7 +2316,7 @@ vpunpckldq, 0x6662, None, CpuAVX512F, Modrm|Masking=
=3D3|Space0F|VexVVVV=3D1|VexW=3D1|B
 vpunpcklqdq, 0x666c, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|V=
exW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No=
_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|=
RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
 vpxor<dq>, 0x66ef, None, CpuAVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|<dq=
:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|=
No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|Bas=
eIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
=20
-<avx_irel:imm, eq:0, lt:1, le:2, neq:4, nlt:5, nle:6>
+<irel:imm, eq:0, lt:1, le:2, neq:4, nlt:5, nle:6>
=20
 vpcmpeqd, 0x6676, None, CpuAVX512F, Modrm|Masking=3D2|Space0F|VexVVVV=3D1|=
VexW=3D1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSu=
f|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, Reg=
XMM|RegYMM|RegZMM, RegMask }
 vpcmpeqq, 0x6629, None, CpuAVX512F, Modrm|Masking=3D2|Space0F38|VexVVVV|Ve=
xW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_=
qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|R=
egYMM|RegZMM, RegMask }
@@ -2318,8 +2324,8 @@ vpcmpgtd, 0x6666, None, CpuAVX512F, Modrm|Masking=3D2=
|Space0F|VexVVVV=3D1|VexW=3D1|Bro
 vpcmpgtq, 0x6637, None, CpuAVX512F, Modrm|Masking=3D2|Space0F38|VexVVVV|Ve=
xW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_=
qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|R=
egYMM|RegZMM, RegMask }
 vpcmp<dq>, 0x661f, None, CpuAVX512F, Modrm|Masking=3D2|Space0F3A|VexVVVV|<=
dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSu=
f|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|Base=
Index, RegXMM|RegYMM|RegZMM, RegMask }
 vpcmpu<dq>, 0x661e, None, CpuAVX512F, Modrm|Masking=3D2|Space0F3A|VexVVVV|=
<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sS=
uf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|Bas=
eIndex, RegXMM|RegYMM|RegZMM, RegMask }
-vpcmp<avx_irel><dq>, 0x661f, <avx_irel:imm>, CpuAVX512F, Modrm|Masking=3D2=
|Space0F3A|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No=
_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|<dq:e=
lem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
-vpcmp<avx_irel>u<dq>, 0x661e, <avx_irel:imm>, CpuAVX512F, Modrm|Masking=3D=
2|Space0F3A|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|N=
o_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|<dq:=
elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
+vpcmp<irel><dq>, 0x661f, <irel:imm>, CpuAVX512F, Modrm|Masking=3D2|Space0F=
3A|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No=
_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|<dq:elem>|Uns=
pecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
+vpcmp<irel>u<dq>, 0x661e, <irel:imm>, CpuAVX512F, Modrm|Masking=3D2|Space0=
F3A|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|N=
o_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|<dq:elem>|Un=
specified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
=20
 vptestm<dq>, 0x6627, None, CpuAVX512F, Modrm|Masking=3D2|Space0F38|VexVVVV=
|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_s=
Suf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseInde=
x, RegXMM|RegYMM|RegZMM, RegMask }
 vptestnm<dq>, 0xf327, None, CpuAVX512F, Modrm|Masking=3D2|Space0F38|VexVVV=
V|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_=
sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseInd=
ex, RegXMM|RegYMM|RegZMM, RegMask }
@@ -2666,8 +2672,8 @@ vpcmpeq<bw>, 0x6674 | <bw:opc>, None, CpuAVX512BW, Mo=
drm|Masking=3D2|Space0F|VexWI
 vpcmpgt<bw>, 0x6664 | <bw:opc>, None, CpuAVX512BW, Modrm|Masking=3D2|Space=
0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf=
|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|Reg=
YMM|RegZMM, RegMask }
 vpcmp<bw>, 0x663f, None, CpuAVX512BW, Modrm|Masking=3D2|Space0F3A|VexVVVV|=
<bw:vexw>|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf=
|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYM=
M|RegZMM, RegMask }
 vpcmpu<bw>, 0x663e, None, CpuAVX512BW, Modrm|Masking=3D2|Space0F3A|VexVVVV=
|<bw:vexw>|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu=
f|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegY=
MM|RegZMM, RegMask }
-vpcmp<avx_irel><bw>, 0x663f, <avx_irel:imm>, CpuAVX512BW, Modrm|Masking=3D=
2|Space0F3A|VexVVVV|<bw:vexw>|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_=
lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|Ba=
seIndex, RegXMM|RegYMM|RegZMM, RegMask }
-vpcmp<avx_irel>u<bw>, 0x663e, <avx_irel:imm>, CpuAVX512BW, Modrm|Masking=
=3D2|Space0F3A|VexVVVV|<bw:vexw>|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|=
No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified=
|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
+vpcmp<irel><bw>, 0x663f, <irel:imm>, CpuAVX512BW, Modrm|Masking=3D2|Space0=
F3A|VexVVVV|<bw:vexw>|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_=
sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex,=
 RegXMM|RegYMM|RegZMM, RegMask }
+vpcmp<irel>u<bw>, 0x663e, <irel:imm>, CpuAVX512BW, Modrm|Masking=3D2|Space=
0F3A|VexVVVV|<bw:vexw>|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No=
_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex=
, RegXMM|RegYMM|RegZMM, RegMask }
=20
 vpslldq, 0x6673, 7, CpuAVX512BW, Modrm|Space0F|VexWIG|VexVVVV=3D2|Disp8Shi=
ftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8,=
 RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
 vpsrldq, 0x6673, 3, CpuAVX512BW, Modrm|Space0F|VexWIG|VexVVVV=3D2|Disp8Shi=
ftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8,=
 RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
@@ -3170,10 +3176,10 @@ vfcmulcsh, 0xf2d7, None, CpuAVX512_FP16, Modrm|EVex=
LIG|Masking=3D3|EVexMap6|VexVVV
 vfmulcph, 0xf3d6, None, CpuAVX512_FP16, Modrm|VexVVVV|Masking=3D3|EVexMap6=
|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|DistinctDest|No_bSuf|No_wSuf|No_=
lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dw=
ord|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
 vfmulcsh, 0xf3d7, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3D3|EVexMap6=
|VexVVVV|VexW0|Disp8MemShift=3D2|DistinctDest|No_bSuf|No_wSuf|No_lSuf|No_sS=
uf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseInde=
x, RegXMM, RegXMM }
=20
-vcmp<avx_frel>ph, 0xc2, 0x<avx_frel:imm>, CpuAVX512_FP16, Modrm|Masking=3D=
2|Space0F3A|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wS=
uf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, { RegXMM|RegYMM|RegZMM|Word=
|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
+vcmp<frel>ph, 0xc2, 0x<frel:imm>, CpuAVX512_FP16, Modrm|Masking=3D2|Space0=
F3A|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lS=
uf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspeci=
fied|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
 vcmpph, 0xc2, None, CpuAVX512_FP16, Modrm|Masking=3D2|Space0F3A|VexVVVV|Ve=
xW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_=
qSuf|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex,=
 RegXMM|RegYMM|RegZMM, RegMask }
=20
-vcmp<avx_frel>sh, 0xf3c2, 0x<avx_frel:imm>, CpuAVX512_FP16, Modrm|EVexLIG|=
Masking=3D2|Space0F3A|VexVVVV|VexW0|Disp8MemShift=3D1|No_bSuf|No_wSuf|No_lS=
uf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, { RegXMM|Word|Unspecified|BaseIndex=
, RegXMM, RegMask }
+vcmp<frel>sh, 0xf3c2, 0x<frel:imm>, CpuAVX512_FP16, Modrm|EVexLIG|Masking=
=3D2|Space0F3A|VexVVVV|VexW0|Disp8MemShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_s=
Suf|No_qSuf|No_ldSuf|ImmExt|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXM=
M, RegMask }
 vcmpsh, 0xf3c2, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3D2|Space0F3A|=
VexVVVV|VexW0|Disp8MemShift=3D1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_=
ldSuf|SAE, { Imm8, RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegMask }
=20
 vcvtdq2ph<xy>, 0x5b, None, CpuAVX512_FP16|<xy:vl>, Modrm|<xy:attr>|Masking=
=3D3|EVexMap5|VexW0|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld=
Suf|<xy:sr>, { <xy:src>|Dword, <xy:dst> }