From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1386) id 060E73858D28; Thu, 18 Aug 2022 07:20:35 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 060E73858D28 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Jan Beulich To: bfd-cvs@sourceware.org Subject: [binutils-gdb] x86: move / quiesce pre-386 non-16-bit warning X-Act-Checkin: binutils-gdb X-Git-Author: Jan Beulich X-Git-Refname: refs/heads/master X-Git-Oldrev: b4d65f2d0b445fee54a2eefcec25336b4238ab82 X-Git-Newrev: d59a54c2c350ba65c65dde5e2a8976918ac59046 Message-Id: <20220818072035.060E73858D28@sourceware.org> Date: Thu, 18 Aug 2022 07:20:35 +0000 (GMT) X-BeenThere: binutils-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 18 Aug 2022 07:20:35 -0000 https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3Dd59a54c2c350= ba65c65dde5e2a8976918ac59046 commit d59a54c2c350ba65c65dde5e2a8976918ac59046 Author: Jan Beulich Date: Thu Aug 18 09:20:05 2022 +0200 x86: move / quiesce pre-386 non-16-bit warning =20 Emitting this warning for every insn, including ones having actual errors, is annoying. Introduce a boolean variable to emit the warning just once on the first insn after .arch may have changed the things, and move the warning to output_insn(). (I didn't want to go as far as checking whether the .arch actually turned off the i386 bit, but doing so would be an option.) Diff: --- gas/config/tc-i386.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 3c0b73f26a6..6598b0e52f1 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -765,6 +765,9 @@ int optimize_align_code =3D 1; /* Non-zero to quieten some warnings. */ static int quiet_warnings =3D 0; =20 +/* Guard to avoid repeated warnings about non-16-bit code on 16-bit CPUs. = */ +static bool pre_386_16bit_warned; + /* CPU name. */ static const char *cpu_arch_name =3D NULL; static char *cpu_sub_arch_name =3D NULL; @@ -2809,6 +2812,7 @@ set_cpu_arch (int dummy ATTRIBUTE_UNUSED) cpu_arch_tune =3D cpu_arch_isa; cpu_arch_tune_flags =3D cpu_arch_isa_flags; } + pre_386_16bit_warned =3D false; break; } =20 @@ -5486,12 +5490,7 @@ parse_insn (char *line, char *mnemonic) { supported |=3D cpu_flags_match (t); if (supported =3D=3D CPU_FLAGS_PERFECT_MATCH) - { - if (!cpu_arch_flags.bitfield.cpui386 && (flag_code !=3D CODE_16BIT)) - as_warn (_("use .code16 to ensure correct addressing mode")); - - return l; - } + return l; } =20 if (!(supported & CPU_FLAGS_64BIT_MATCH)) @@ -9541,6 +9540,13 @@ output_insn (void) fragP->tc_frag_data.max_bytes =3D max_branch_padding_size; } =20 + if (!cpu_arch_flags.bitfield.cpui386 && (flag_code !=3D CODE_16BIT) + && !pre_386_16bit_warned) + { + as_warn (_("use .code16 to ensure correct addressing mode")); + pre_386_16bit_warned =3D true; + } + /* Output jumps. */ if (i.tm.opcode_modifier.jump =3D=3D JUMP) output_branch ();