From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7803) id 2C0493858D1E; Fri, 2 Sep 2022 06:06:30 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 2C0493858D1E Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Nelson Chu To: bfd-cvs@sourceware.org Subject: [binutils-gdb] RISC-V: Add address printer tests with ADDIW X-Act-Checkin: binutils-gdb X-Git-Author: Tsukasa OI X-Git-Refname: refs/heads/master X-Git-Oldrev: 5edf42b635a375f7bf79e2079529eeb869129cbe X-Git-Newrev: e9f7ba21f08a264f813140eb6221e9d9670dc12f Message-Id: <20220902060630.2C0493858D1E@sourceware.org> Date: Fri, 2 Sep 2022 06:06:30 +0000 (GMT) X-BeenThere: binutils-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 02 Sep 2022 06:06:30 -0000 https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3De9f7ba21f08a= 264f813140eb6221e9d9670dc12f commit e9f7ba21f08a264f813140eb6221e9d9670dc12f Author: Tsukasa OI Date: Sat Aug 27 00:10:58 2022 +0000 RISC-V: Add address printer tests with ADDIW =20 Address sequences involving ADDIW/C.ADDIW instructions require special handling to sign-extend lower 32-bits of the original result. =20 This commit tests whether this sign-extension works. =20 gas/ChangeLog: =20 * testsuite/gas/riscv/dis-addr-addiw.s: New to test the address computation with sign extension as used in ADDIW/C.ADDIW. * testsuite/gas/riscv/dis-addr-addiw-a.d: Test PC sign bit 0. * testsuite/gas/riscv/dis-addr-addiw-b.d: Test PC sign bit 1. =20 gas/ChangeLog: =20 * testsuite/gas/riscv/dis-addr-addiw-a.d: New test. * testsuite/gas/riscv/dis-addr-addiw-b.d: New test. * testsuite/gas/riscv/dis-addr-addiw.s: New test. Diff: --- gas/testsuite/gas/riscv/dis-addr-addiw-a.d | 18 ++++++++++++++++++ gas/testsuite/gas/riscv/dis-addr-addiw-b.d | 18 ++++++++++++++++++ gas/testsuite/gas/riscv/dis-addr-addiw.s | 28 ++++++++++++++++++++++++++= ++ 3 files changed, 64 insertions(+) diff --git a/gas/testsuite/gas/riscv/dis-addr-addiw-a.d b/gas/testsuite/gas= /riscv/dis-addr-addiw-a.d new file mode 100644 index 00000000000..3cd9d4e3805 --- /dev/null +++ b/gas/testsuite/gas/riscv/dis-addr-addiw-a.d @@ -0,0 +1,18 @@ +#as: -march=3Drv64ic +#source: dis-addr-addiw.s +#objdump: -d --adjust-vma=3D0xffffffe0 + +.*: file format elf64-(little|big)riscv + + +Disassembly of section .text: + +0+ffffffe0 <_start>: +[ ]+ffffffe0:[ ]+00000297[ ]+auipc[ ]+t0,0x0 +[ ]+ffffffe4:[ ]+0182831b[ ]+addiw[ ]+t1,t0,24 # fffffffffffffff8 +[ ]+ffffffe8:[ ]+00000397[ ]+auipc[ ]+t2,0x0 +[ ]+ffffffec:[ ]+01c38e1b[ ]+addiw[ ]+t3,t2,28 # 4 +[ ]+fffffff0:[ ]+00000e97[ ]+auipc[ ]+t4,0x0 +[ ]+fffffff4:[ ]+2eb1[ ]+addiw[ ]+t4,t4,12 # fffffffffffffffc +[ ]+fffffff6:[ ]+00000f17[ ]+auipc[ ]+t5,0x0 +[ ]+fffffffa:[ ]+2f49[ ]+addiw[ ]+t5,t5,18 # 8 diff --git a/gas/testsuite/gas/riscv/dis-addr-addiw-b.d b/gas/testsuite/gas= /riscv/dis-addr-addiw-b.d new file mode 100644 index 00000000000..2c68d6b6e5f --- /dev/null +++ b/gas/testsuite/gas/riscv/dis-addr-addiw-b.d @@ -0,0 +1,18 @@ +#as: -march=3Drv64ic +#source: dis-addr-addiw.s +#objdump: -d --adjust-vma=3D0x7fffffe0 + +.*: file format elf64-(little|big)riscv + + +Disassembly of section .text: + +0+7fffffe0 <_start>: +[ ]+7fffffe0:[ ]+00000297[ ]+auipc[ ]+t0,0x0 +[ ]+7fffffe4:[ ]+0182831b[ ]+addiw[ ]+t1,t0,24 # 7ffffff8 +[ ]+7fffffe8:[ ]+00000397[ ]+auipc[ ]+t2,0x0 +[ ]+7fffffec:[ ]+01c38e1b[ ]+addiw[ ]+t3,t2,28 # ffffffff80000004 +[ ]+7ffffff0:[ ]+00000e97[ ]+auipc[ ]+t4,0x0 +[ ]+7ffffff4:[ ]+2eb1[ ]+addiw[ ]+t4,t4,12 # 7ffffffc +[ ]+7ffffff6:[ ]+00000f17[ ]+auipc[ ]+t5,0x0 +[ ]+7ffffffa:[ ]+2f49[ ]+addiw[ ]+t5,t5,18 # ffffffff80000008 diff --git a/gas/testsuite/gas/riscv/dis-addr-addiw.s b/gas/testsuite/gas/r= iscv/dis-addr-addiw.s new file mode 100644 index 00000000000..7c878f86dd6 --- /dev/null +++ b/gas/testsuite/gas/riscv/dis-addr-addiw.s @@ -0,0 +1,28 @@ +.set addr_rv64_addiw_0a, 0xfffffffffffffff8 # 0xffffffe0 + 0x18 (sext:3= 2->64) +.set addr_rv64_c_addiw_0a, 0xfffffffffffffffc # 0xfffffff0 + 0x0c (sext:3= 2->64) +.set addr_rv64_addiw_0b, 0x00000004 # 0xffffffe8 + 0x1c +.set addr_rv64_c_addiw_0b, 0x00000008 # 0xfffffff6 + 0x12 +.set addr_rv64_addiw_1a, 0x7ffffff8 # 0x7fffffe0 + 0x18 +.set addr_rv64_c_addiw_1a, 0x7ffffffc # 0x7ffffff0 + 0x0c +.set addr_rv64_addiw_1b, 0xffffffff80000004 # 0x7fffffe8 + 0x1c (sext:3= 2->64) +.set addr_rv64_c_addiw_1b, 0xffffffff80000008 # 0x7ffffff6 + 0x12 (sext:3= 2->64) + + .text + .global _start +_start: + .option push + .option arch, -c + # _start + 0x00 + auipc t0, 0 + addiw t1, t0, 0x18 + # _start + 0x08 + auipc t2, 0 + addiw t3, t2, 0x1c + + .option pop + # _start + 0x10 + auipc t4, 0 + c.addiw t4, 0x0c + # _start + 0x16 + auipc t5, 0 + c.addiw t5, 0x12