From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1464) id 14C843858403; Mon, 12 Sep 2022 19:57:43 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 14C843858403 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Peter Bergner To: bfd-cvs@sourceware.org Subject: [binutils-gdb] ppc: Document the -mfuture and -Mfuture options and make them usable X-Act-Checkin: binutils-gdb X-Git-Author: Peter Bergner X-Git-Refname: refs/heads/master X-Git-Oldrev: fbdc50d2c7ce12458aa925ea3dd8512f652929bd X-Git-Newrev: 29a6701e530a4119d3c0d261da2b7b24034c9233 Message-Id: <20220912195743.14C843858403@sourceware.org> Date: Mon, 12 Sep 2022 19:57:43 +0000 (GMT) X-BeenThere: binutils-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 12 Sep 2022 19:57:43 -0000 https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D29a6701e530a= 4119d3c0d261da2b7b24034c9233 commit 29a6701e530a4119d3c0d261da2b7b24034c9233 Author: Peter Bergner Date: Mon Sep 12 14:56:20 2022 -0500 ppc: Document the -mfuture and -Mfuture options and make them usable =20 The -mfuture and -Mfuture options which are used for adding potential new ISA instructions were not documented. They also lacked a bitmask so new instructions could not be enabled by those options. Fixed. =20 binutils/ * doc/binutils.texi: Document -Mfuture. =20 gas/ * config/tc-ppc.c: Document -mfuture * doc/c-ppc.texi: Likewise. =20 include/ * opcode/ppc.h (PPC_OPCODE_FUTURE): Define. =20 opcodes/ * ppc-dis.c (ppc_opts) : Use it. * ppc-opc.c (FUTURE): Define. Diff: --- binutils/doc/binutils.texi | 2 +- gas/config/tc-ppc.c | 2 ++ gas/doc/c-ppc.texi | 3 +++ include/opcode/ppc.h | 3 +++ opcodes/ppc-dis.c | 3 ++- opcodes/ppc-opc.c | 1 + 6 files changed, 12 insertions(+), 2 deletions(-) diff --git a/binutils/doc/binutils.texi b/binutils/doc/binutils.texi index f61a619ec78..1499db5728c 100644 --- a/binutils/doc/binutils.texi +++ b/binutils/doc/binutils.texi @@ -2638,7 +2638,7 @@ rather than @code{li}. All of the @option{-m} argume= nts for @option{ppc32}, @option{ppc64}, @option{ppc64bridge}, @option{ppcps}, @option{pwr}, @option{pwr2}, @option{pwr4}, @option{pwr5}, @option{pwr5x}, @option{pwr6}, @option{pwr7}, @option{pwr8}, @option{pwr9}, @option{pwr10}, -@option{pwrx}, @option{titan}, and @option{vle}. +@option{pwrx}, @option{titan}, @option{vle}, and @option{future}. @option{32} and @option{64} modify the default or a prior CPU selection, disabling and enabling 64-bit insns respectively. In addition, @option{altivec}, @option{any}, @option{htm}, @option{vsx}, diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c index b5aad4b6e3e..37a8b54a28f 100644 --- a/gas/config/tc-ppc.c +++ b/gas/config/tc-ppc.c @@ -1384,6 +1384,8 @@ PowerPC options:\n")); fprintf (stream, _("\ -mlibresoc generate code for Libre-SOC architecture\n")); fprintf (stream, _("\ +-mfuture generate code for 'future' architecture\n")); + fprintf (stream, _("\ -mcell generate code for Cell Broadband Engine architectu= re\n")); fprintf (stream, _("\ -mcom generate code for Power/PowerPC common instruction= s\n")); diff --git a/gas/doc/c-ppc.texi b/gas/doc/c-ppc.texi index 81254935239..2986d3de7f8 100644 --- a/gas/doc/c-ppc.texi +++ b/gas/doc/c-ppc.texi @@ -150,6 +150,9 @@ Generate code for Power9 architecture. @item -mpower10, -mpwr10 Generate code for Power10 architecture. =20 +@item -mfuture +Generate code for 'future' architecture. + @item -mcell @item -mcell Generate code for Cell Broadband Engine architecture. diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h index 3578f0d218d..c5d96a265a8 100644 --- a/include/opcode/ppc.h +++ b/include/opcode/ppc.h @@ -240,6 +240,9 @@ extern const unsigned int spe2_num_opcodes; /* Opcode is only supported by SVP64 extensions (LibreSOC architecture). = */ #define PPC_OPCODE_SVP64 0x800000000000ull =20 +/* Opcode is only supported by 'future' architecture. */ +#define PPC_OPCODE_FUTURE 0x1000000000000ull + /* A macro to extract the major opcode from an instruction. */ #define PPC_OP(i) (((i) >> 26) & 0x3f) =20 diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c index 97f2e201e9a..3ba06274b21 100644 --- a/opcodes/ppc-dis.c +++ b/opcodes/ppc-dis.c @@ -208,7 +208,8 @@ struct ppc_mopt ppc_opts[] =3D { { "future", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9 - | PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX), + | PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX + | PPC_OPCODE_FUTURE), 0 }, { "ppc", PPC_OPCODE_PPC, 0 }, diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 934b1bf4e85..25c96ba87b7 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -4847,6 +4847,7 @@ const unsigned int num_powerpc_operands =3D (sizeof (= powerpc_operands) #define POWER8 PPC_OPCODE_POWER8 #define POWER9 PPC_OPCODE_POWER9 #define POWER10 PPC_OPCODE_POWER10 +#define FUTURE PPC_OPCODE_FUTURE #define CELL PPC_OPCODE_CELL #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE #define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \