From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1923) id 69AB13858D38; Thu, 22 Sep 2022 16:42:50 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 69AB13858D38 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Philipp Tomsich To: bfd-cvs@sourceware.org Subject: [binutils-gdb] RISC-V: Add generic support for vendor extensions X-Act-Checkin: binutils-gdb X-Git-Author: =?utf-8?q?Christoph_M=C3=BCllner?= X-Git-Refname: refs/heads/master X-Git-Oldrev: aaf3f3f3bb38a59125ea34afa0ef7e0e14c2e916 X-Git-Newrev: fb1737381d886c7c0a4e870af078c473ac463fce Message-Id: <20220922164250.69AB13858D38@sourceware.org> Date: Thu, 22 Sep 2022 16:42:50 +0000 (GMT) X-BeenThere: binutils-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 22 Sep 2022 16:42:50 -0000 https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3Dfb1737381d88= 6c7c0a4e870af078c473ac463fce commit fb1737381d886c7c0a4e870af078c473ac463fce Author: Christoph M=C3=BCllner Date: Tue Jun 28 17:42:58 2022 +0200 RISC-V: Add generic support for vendor extensions =20 This patch introduces changes that allow the integration of vendor ISA extensions: * Define a list of vendor extensions (riscv_supported_vendor_x_ext) where vendor extensions can be added * Introduce a section with a table in the documentation where vendor extensions can be added =20 To add a vendor extension that consists of instructions only, the following things need to be done: * Add the extension to the riscv_supported_vendor_x_ext list * Add lookup entry in riscv_multi_subset_supports * Documenting the extension in c-riscv.texti * Add test cases for all instructions * Add MATCH*/MASK* constants and DECLARE_INSN() for all instructions * Add new instruction class to enum riscv_insn_class * Define the instructions in riscv_opcodes * Additional changes if necessary (depending on the instructions) =20 Co-developed-by: Lifang Xia Signed-off-by: Christoph M=C3=BCllner Diff: --- bfd/elfxx-riscv.c | 9 +++++++-- gas/doc/c-riscv.texi | 14 ++++++++++++++ 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 7eda177bd6e..cb3a980936d 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1222,12 +1222,18 @@ static struct riscv_supported_ext riscv_supported_s= td_zxm_ext[] =3D {NULL, 0, 0, 0, 0} }; =20 +static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =3D +{ + {NULL, 0, 0, 0, 0} +}; + const struct riscv_supported_ext *riscv_all_supported_ext[] =3D { riscv_supported_std_ext, riscv_supported_std_z_ext, riscv_supported_std_s_ext, riscv_supported_std_zxm_ext, + riscv_supported_vendor_x_ext, NULL }; =20 @@ -1483,8 +1489,7 @@ riscv_get_default_ext_version (enum riscv_spec_class = *default_isa_spec, case RV_ISA_CLASS_ZXM: table =3D riscv_supported_std_zxm_ext; break; case RV_ISA_CLASS_Z: table =3D riscv_supported_std_z_ext; break; case RV_ISA_CLASS_S: table =3D riscv_supported_std_s_ext; break; - case RV_ISA_CLASS_X: - break; + case RV_ISA_CLASS_X: table =3D riscv_supported_vendor_x_ext; break; default: table =3D riscv_supported_std_ext; } diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index 21d867e9cf0..30afd200b7d 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -20,6 +20,7 @@ * RISC-V-Modifiers:: RISC-V Assembler Modifiers * RISC-V-Formats:: RISC-V Instruction Formats * RISC-V-ATTRIBUTE:: RISC-V Object Attribute +* RISC-V-CustomExts:: RISC-V Custom (Vendor-Defined) Extensions @end menu =20 @node RISC-V-Options @@ -692,3 +693,16 @@ the privileged specification. It will report errors i= f object files of different privileged specification versions are merged. =20 @end table + +@node RISC-V-CustomExts +@section RISC-V Custom (Vendor-Defined) Extensions +@cindex custom (vendor-defined) extensions, RISC-V +@cindex RISC-V custom (vendor-defined) extensions + +The following table lists the custom (vendor-defined) RISC-V +extensions supported and provides the location of their +publicly-released documentation: + +@table @r + +@end table