* [binutils-gdb/upstream/users/aburgess/arm-disasm-styling] opcodes/arm: add disassembler styling for arm
@ 2022-10-19 10:06 Andrew Burgess
0 siblings, 0 replies; only message in thread
From: Andrew Burgess @ 2022-10-19 10:06 UTC (permalink / raw)
To: bfd-cvs
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=11843af456b9c5c2418e4e8eac35649c713c1425
commit 11843af456b9c5c2418e4e8eac35649c713c1425
Author: Andrew Burgess <aburgess@redhat.com>
Date: Thu Jul 7 13:43:45 2022 +0100
opcodes/arm: add disassembler styling for arm
This commit adds disassembler styling for the ARM architecture.
The ARM disassembler is driven by several instruction tables,
e.g. cde_opcodes, coprocessor_opcodes, neon_opcodes, etc
The type for elements in each table can vary, but they all have one
thing in common, a 'const char * assembler' field. This field
contains a string that describes the assembler syntax of the
instruction.
Embedded within that assembler syntax are various escape characters,
prefixed with a '%'. Here's an example of a very simple instruction
from the arm_opcodes table:
"pld\t%a"
The '%a' indicates a particular type of operand, the function
print_insn_arm processes the arm_opcodes table, and includes a switch
statement that handles the '%a' operand, and takes care of printing
the correct value for that instruction operand.
It is worth noting that there are many print_* functions, each
function handles a single *_opcodes table, and includes its own switch
statement for operand handling. As a result, every *_opcodes table
uses a different mapping for the operand escape sequences. This means
that '%a' might print an address for one *_opcodes table, but in a
different *_opcodes table '%a' might print a register operand.
Notice as well that in our example above, the instruction mnemonic
'pld' is embedded within the assembler string. Some instructions also
include comments within the assembler string, for example, also from
the arm_opcodes table:
"nop\t\t\t@ (mov r0, r0)"
here, everything after the '@' is a comment that is displayed at the
end of the instruction disassembly.
The next complexity is that the meaning of some escape sequences is
not necessarily fixed. Consider these two examples from arm_opcodes:
"ldrex%c\tr%12-15d, [%16-19R]"
"setpan\t#%9-9d"
Here, the '%d' escape is used with a bitfield modifier, '%12-15d' in
the first instruction, and '%9-9d' in the second instruction, but,
both of these are the '%d' escape.
However, in the first instruction, the '%d' is used to print a
register number, notice the 'r' immediately before the '%d'. In the
second instruction the '%d' is used to print an immediate, notice the
'#' just before the '%d'.
We have two problems here, first, the '%d' needs to know if it should
use register style or immediate style, and secondly, the 'r' and '#'
characters also need to be styled appropriately.
The final thing we must consider is that some escape codes result in
more than just a single operand being printed, for example, the '%q'
operand as used in arm_opcodes ends up calling arm_decode_shift, which
can print a register name, a shift type, and a shift amount, this
could end up using register, sub-mnemonic, and immediate styles, as
well as the text style for things like ',' between the different
parts.
I propose a three layer approach to adding styling:
(1) Basic state machine:
When we start printing an instruction we should maintain the idea
of a 'base_style'. Every character from the assembler string will
be printed using the base_style.
The base_style will start as mnemonic, as each instruction starts
with an instruction mnemonic. When we encounter the first '\t'
character, the base_style will change to text. When we encounter
the first '@' the base_style will change to comment_start.
This simple state machine ensures that for simple instructions the
basic parts, except for the operands themselves, will be printed in
the correct style.
(2) Simple operand styling:
For operands that only have a single meaning, or which expand to
multiple parts, all of which have a consistent meaning, then I
will simply update the operand printing code to print the operand
with the correct style. This will cover a large number of the
operands, and is the most consistent with how styling has been
added to previous architectures.
(3) New styling syntax in assembler strings:
For cases like the '%s' that I describe above, I propose adding a
new extension to the assembler syntax. This extension will allow
me to temporarily change the base_style. Some operands, like
'%d', will then print using the base_style rather than using a
fixed style.
Here are the two examples from above that use '%d', updated with
the new syntax extension:
"ldrex%c\t%{R:r%12-15d%}, [%16-19R]"
"setpan\t%{I:#%9-9d%}"
The syntax has the general form '%{X:....%}' where the 'X'
character changes to indicate a different style. In the first
instruction I use '%{R:...%}' to change base_style to the register
style, and in the second '%{I:...%}' changes base_style to
immediate style.
Notice that the 'r' and '#' characters are included within the new
style group, this ensures that these characters are printed with
the correct style rather than as text.
The function decode_base_style maps from character to style. I've
included a character for each style for completeness, though only
a small number of styles are currently used.
I have updated arm-dis.c to the above scheme, and checked all of the
tests in gas/testsuite/gas/arm/, and the styling looks reasonable.
There are no regressions on the ARM gas/binutils/ld tests that I can
see, so I don't believe I've changed the output layout at all. There
were two binutils tests for which I needed to force the disassembler
styling off.
I can't guarantee that I've not missed some untested corners of the
disassembler, or that I might have just missed some incorrectly styled
output when reviewing the test results, but I don't believe I've
introduced any changes that could break the disassembler - the worst
should be some aspect is not styled correctly.
Diff:
---
binutils/testsuite/binutils-all/arm/objdump.exp | 4 +-
opcodes/arm-dis.c | 2632 ++++++++++++++---------
opcodes/disassemble.c | 1 +
3 files changed, 1633 insertions(+), 1004 deletions(-)
diff --git a/binutils/testsuite/binutils-all/arm/objdump.exp b/binutils/testsuite/binutils-all/arm/objdump.exp
index 9cd057e60f1..c667577f19e 100644
--- a/binutils/testsuite/binutils-all/arm/objdump.exp
+++ b/binutils/testsuite/binutils-all/arm/objdump.exp
@@ -51,7 +51,7 @@ if {![binutils_assemble $srcdir/$subdir/thumb2-cond.s tmpdir/thumb2-cond.o]} the
fail "thumb2-cond test1"
}
- set got [binutils_run $OBJDUMP "$OBJDUMPFLAGS --disassemble --start-address=10 $objfile"]
+ set got [binutils_run $OBJDUMP "$OBJDUMPFLAGS --disassemble --disassembler-color=off --start-address=10 $objfile"]
set want "bx\[ \t\]*lr"
@@ -78,7 +78,7 @@ if {![binutils_assemble $srcdir/$subdir/simple.s tmpdir/simple.o]} then {
# Make sure multiple disassemblies come out the same
- set got [binutils_run $OBJDUMP "-dr $objfile $objfile"]
+ set got [binutils_run $OBJDUMP "-dr --disassembler-color=off $objfile $objfile"]
set want "$objfile:\[ \]*file format.*$objfile:\[ \]*file format.*push.*add.*sub.*str.*add.*ldmfd"
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index c73a7447b28..6d302ec50ba 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -490,45 +490,45 @@ static const struct cdeopcode32 cde_opcodes[] =
/* Custom Datapath Extension instructions. */
CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
0xee000000, 0xefc00840,
- "cx1%a\t%p, %12-15n, #%0-5,7,16-21d"),
+ "cx1%a\t%p, %12-15n, %{I:#%0-5,7,16-21d%}"),
CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
0xee000040, 0xefc00840,
- "cx1d%a\t%p, %12-15S, %12-15T, #%0-5,7,16-21d"),
+ "cx1d%a\t%p, %12-15S, %12-15T, %{I:#%0-5,7,16-21d%}"),
CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
0xee400000, 0xefc00840,
- "cx2%a\t%p, %12-15n, %16-19n, #%0-5,7,20-21d"),
+ "cx2%a\t%p, %12-15n, %16-19n, %{I:#%0-5,7,20-21d%}"),
CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
0xee400040, 0xefc00840,
- "cx2d%a\t%p, %12-15S, %12-15T, %16-19n, #%0-5,7,20-21d"),
+ "cx2d%a\t%p, %12-15S, %12-15T, %16-19n, %{I:#%0-5,7,20-21d%}"),
CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
0xee800000, 0xef800840,
- "cx3%a\t%p, %0-3n, %16-19n, %12-15n, #%4-5,7,20-22d"),
+ "cx3%a\t%p, %0-3n, %16-19n, %12-15n, %{I:#%4-5,7,20-22d%}"),
CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
0xee800040, 0xef800840,
- "cx3d%a\t%p, %0-3S, %0-3T, %16-19n, %12-15n, #%4-5,7,20-22d"),
+ "cx3d%a\t%p, %0-3S, %0-3T, %16-19n, %12-15n, %{I:#%4-5,7,20-22d%}"),
CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
0xec200000, 0xeeb00840,
- "vcx1%a\t%p, %12-15,22V, #%0-5,7,16-19d"),
+ "vcx1%a\t%p, %12-15,22V, %{I:#%0-5,7,16-19d%}"),
CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
0xec200040, 0xeeb00840,
- "vcx1%a\t%p, %12-15,22V, #%0-5,7,16-19,24d"),
+ "vcx1%a\t%p, %12-15,22V, %{I:#%0-5,7,16-19,24d%}"),
CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
0xec300000, 0xeeb00840,
- "vcx2%a\t%p, %12-15,22V, %0-3,5V, #%4,7,16-19d"),
+ "vcx2%a\t%p, %12-15,22V, %0-3,5V, %{I:#%4,7,16-19d%}"),
CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
0xec300040, 0xeeb00840,
- "vcx2%a\t%p, %12-15,22V, %0-3,5V, #%4,7,16-19,24d"),
+ "vcx2%a\t%p, %12-15,22V, %0-3,5V, %{I:#%4,7,16-19,24d%}"),
CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
0xec800000, 0xee800840,
- "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, #%4,20-21d"),
+ "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, %{I:#%4,20-21d%}"),
CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE),
0xec800040, 0xee800840,
- "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, #%4,20-21,24d"),
+ "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, %{I:#%4,20-21,24d%}"),
CDE_OPCODE (ARM_FEATURE_CORE_LOW (0), 0, 0, 0)
@@ -539,16 +539,16 @@ static const struct sopcode32 coprocessor_opcodes[] =
/* XScale instructions. */
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e200010, 0x0fff0ff0,
- "mia%c\tacc0, %0-3r, %12-15r"},
+ "mia%c\t%{R:acc0%}, %0-3r, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e280010, 0x0fff0ff0,
- "miaph%c\tacc0, %0-3r, %12-15r"},
+ "miaph%c\t%{R:acc0%}, %0-3r, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
- 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
+ 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\t%{R:acc0%}, %0-3r, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
- 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
+ 0x0c400000, 0x0ff00fff, "mar%c\t%{R:acc0%}, %12-15r, %16-19r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
- 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
+ 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, %{R:acc0%}"},
/* Intel Wireless MMX technology instructions. */
{ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
@@ -557,11 +557,11 @@ static const struct sopcode32 coprocessor_opcodes[] =
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
- 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
+ 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, %{I:#%0-2d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
- 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
+ 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, %{I:#%0-2d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
- 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
+ 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, %{I:#%0-2d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
@@ -593,7 +593,7 @@ static const struct sopcode32 coprocessor_opcodes[] =
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
- 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
+ 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, %{I:#%20-22d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
@@ -621,7 +621,7 @@ static const struct sopcode32 coprocessor_opcodes[] =
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
- 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
+ 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, %{I:#%21-23d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
@@ -651,7 +651,7 @@ static const struct sopcode32 coprocessor_opcodes[] =
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
- 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
+ 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
@@ -659,21 +659,21 @@ static const struct sopcode32 coprocessor_opcodes[] =
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
- 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
+ 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, %{I:#%Z%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
- 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
+ 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
- 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
+ 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
- 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
+ 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, %{I:#%i%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
@@ -860,17 +860,17 @@ static const struct sopcode32 coprocessor_opcodes[] =
{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
+ 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%{R:%16-19,7D[%21d]%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
+ 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %{R:%16-19,7D[%21d]%}"},
{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
+ 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%{R:%16-19,7D[%6,21d]%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
+ 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %{R:%16-19,7D[%6,21d]%}"},
{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
+ 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%{R:%16-19,7D[%5,6,21d]%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
+ 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %{R:%16-19,7D[%5,6,21d]%}"},
/* Half-precision conversion instructions. */
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
@@ -883,63 +883,63 @@ static const struct sopcode32 coprocessor_opcodes[] =
/* Floating point coprocessor (VFP) instructions. */
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
+ 0x0ee00a10, 0x0fff0fff, "vmsr%c\t%{R:fpsid%}, %12-15r"},
{ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD),
- 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
+ 0x0ee10a10, 0x0fff0fff, "vmsr%c\t%{R:fpscr%}, %12-15r"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
- 0x0ee20a10, 0x0fff0fff, "vmsr%c\tfpscr_nzcvqc, %12-15r"},
+ 0x0ee20a10, 0x0fff0fff, "vmsr%c\t%{R:fpscr_nzcvqc%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
+ 0x0ee60a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr1%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
+ 0x0ee70a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr0%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
- 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
+ 0x0ee50a10, 0x0fff0fff, "vmsr%c\t%{R:mvfr2%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
+ 0x0ee80a10, 0x0fff0fff, "vmsr%c\t%{R:fpexc%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
+ 0x0ee90a10, 0x0fff0fff, "vmsr%c\t%{R:fpinst%}, %12-15r\t@ Impl def"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
+ 0x0eea0a10, 0x0fff0fff, "vmsr%c\t%{R:fpinst2%}, %12-15r\t@ Impl def"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
- 0x0eec0a10, 0x0fff0fff, "vmsr%c\tvpr, %12-15r"},
+ 0x0eec0a10, 0x0fff0fff, "vmsr%c\t%{R:vpr%}, %12-15r"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
- 0x0eed0a10, 0x0fff0fff, "vmsr%c\tp0, %12-15r"},
+ 0x0eed0a10, 0x0fff0fff, "vmsr%c\t%{R:p0%}, %12-15r"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
- 0x0eee0a10, 0x0fff0fff, "vmsr%c\tfpcxt_ns, %12-15r"},
+ 0x0eee0a10, 0x0fff0fff, "vmsr%c\t%{R:fpcxt_ns%}, %12-15r"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
- 0x0eef0a10, 0x0fff0fff, "vmsr%c\tfpcxt_s, %12-15r"},
+ 0x0eef0a10, 0x0fff0fff, "vmsr%c\t%{R:fpcxt_s%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
+ 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpsid%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
+ 0x0ef1fa10, 0x0fffffff, "vmrs%c\t%{R:APSR_nzcv%}, %{R:fpscr%}"},
{ANY, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN, FPU_VFP_EXT_V1xD),
- 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
+ 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpscr%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
- 0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr_nzcvqc"},
+ 0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpscr_nzcvqc%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
- 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
+ 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr2%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
+ 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr1%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
+ 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:mvfr0%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
+ 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpexc%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
+ 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpinst%}\t@ Impl def"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
+ 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpinst2%}\t@ Impl def"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
- 0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, vpr"},
+ 0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:vpr%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
- 0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, p0"},
+ 0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:p0%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
- 0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_ns"},
+ 0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpcxt_ns%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
- 0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_s"},
+ 0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, %{R:fpcxt_s%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
- 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
+ 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%{I:%21d%}], %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
- 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
+ 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%{I:%21d%}]"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
@@ -949,9 +949,9 @@ static const struct sopcode32 coprocessor_opcodes[] =
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
- 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
+ 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, %{I:#0.0%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
- 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
+ 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, %{I:#0.0%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
@@ -981,23 +981,23 @@ static const struct sopcode32 coprocessor_opcodes[] =
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
- 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
+ 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, %{I:#%5,0-3k%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
- 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
+ 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, %{I:#%5,0-3k%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
- 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
+ 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, %{I:#%5,0-3k%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
- 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
+ 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, %{I:#%5,0-3k%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
- 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
+ 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, %{I:#%0-3,16-19E%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
- 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
+ 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, %{I:#%0-3,16-19E%}"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
@@ -1043,177 +1043,177 @@ static const struct sopcode32 coprocessor_opcodes[] =
/* Cirrus coprocessor instructions. */
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
+ 0x0d100400, 0x0f500f00, "cfldrs%c\t%{R:mvf%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
+ 0x0c100400, 0x0f500f00, "cfldrs%c\t%{R:mvf%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
+ 0x0d500400, 0x0f500f00, "cfldrd%c\t%{R:mvd%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
+ 0x0c500400, 0x0f500f00, "cfldrd%c\t%{R:mvd%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
+ 0x0d100500, 0x0f500f00, "cfldr32%c\t%{R:mvfx%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
+ 0x0c100500, 0x0f500f00, "cfldr32%c\t%{R:mvfx%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
+ 0x0d500500, 0x0f500f00, "cfldr64%c\t%{R:mvdx%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
+ 0x0c500500, 0x0f500f00, "cfldr64%c\t%{R:mvdx%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
+ 0x0d000400, 0x0f500f00, "cfstrs%c\t%{R:mvf%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
+ 0x0c000400, 0x0f500f00, "cfstrs%c\t%{R:mvf%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
+ 0x0d400400, 0x0f500f00, "cfstrd%c\t%{R:mvd%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
+ 0x0c400400, 0x0f500f00, "cfstrd%c\t%{R:mvd%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
+ 0x0d000500, 0x0f500f00, "cfstr32%c\t%{R:mvfx%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
+ 0x0c000500, 0x0f500f00, "cfstr32%c\t%{R:mvfx%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
+ 0x0d400500, 0x0f500f00, "cfstr64%c\t%{R:mvdx%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
+ 0x0c400500, 0x0f500f00, "cfstr64%c\t%{R:mvdx%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
+ 0x0e000450, 0x0ff00ff0, "cfmvsr%c\t%{R:mvf%16-19d%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
+ 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, %{R:mvf%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
+ 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\t%{R:mvd%16-19d%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
+ 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, %{R:mvd%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
+ 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\t%{R:mvd%16-19d%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
+ 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, %{R:mvd%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
+ 0x0e000510, 0x0ff00fff, "cfmv64lr%c\t%{R:mvdx%16-19d%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
+ 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, %{R:mvdx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
+ 0x0e000530, 0x0ff00fff, "cfmv64hr%c\t%{R:mvdx%16-19d%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
+ 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, %{R:mvdx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
+ 0x0e200440, 0x0ff00fff, "cfmval32%c\t%{R:mvax%12-15d%}, %{R:mvfx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
+ 0x0e100440, 0x0ff00fff, "cfmv32al%c\t%{R:mvfx%12-15d%}, %{R:mvax%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
+ 0x0e200460, 0x0ff00fff, "cfmvam32%c\t%{R:mvax%12-15d%}, %{R:mvfx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
+ 0x0e100460, 0x0ff00fff, "cfmv32am%c\t%{R:mvfx%12-15d%}, %{R:mvax%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
+ 0x0e200480, 0x0ff00fff, "cfmvah32%c\t%{R:mvax%12-15d%}, %{R:mvfx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
+ 0x0e100480, 0x0ff00fff, "cfmv32ah%c\t%{R:mvfx%12-15d%}, %{R:mvax%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
+ 0x0e2004a0, 0x0ff00fff, "cfmva32%c\t%{R:mvax%12-15d%}, %{R:mvfx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
+ 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\t%{R:mvfx%12-15d%}, %{R:mvax%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
+ 0x0e2004c0, 0x0ff00fff, "cfmva64%c\t%{R:mvax%12-15d%}, %{R:mvdx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
+ 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\t%{R:mvdx%12-15d%}, %{R:mvax%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
+ 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\t%{R:dspsc%}, %{R:mvdx%12-15d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
+ 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\t%{R:mvdx%12-15d%}, %{R:dspsc%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
+ 0x0e000400, 0x0ff00fff, "cfcpys%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
+ 0x0e000420, 0x0ff00fff, "cfcpyd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
+ 0x0e000460, 0x0ff00fff, "cfcvtsd%c\t%{R:mvd%12-15d%}, %{R:mvf%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
+ 0x0e000440, 0x0ff00fff, "cfcvtds%c\t%{R:mvf%12-15d%}, %{R:mvd%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
+ 0x0e000480, 0x0ff00fff, "cfcvt32s%c\t%{R:mvf%12-15d%}, %{R:mvfx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
+ 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\t%{R:mvd%12-15d%}, %{R:mvfx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
+ 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\t%{R:mvf%12-15d%}, %{R:mvdx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
+ 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\t%{R:mvd%12-15d%}, %{R:mvdx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
+ 0x0e100580, 0x0ff00fff, "cfcvts32%c\t%{R:mvfx%12-15d%}, %{R:mvf%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
+ 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\t%{R:mvfx%12-15d%}, %{R:mvd%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
+ 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\t%{R:mvfx%12-15d%}, %{R:mvf%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
+ 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\t%{R:mvfx%12-15d%}, %{R:mvd%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
+ 0x0e000550, 0x0ff00ff0, "cfrshl32%c\t%{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
+ 0x0e000570, 0x0ff00ff0, "cfrshl64%c\t%{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
+ 0x0e000500, 0x0ff00f10, "cfsh32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{I:#%I%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
+ 0x0e200500, 0x0ff00f10, "cfsh64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}, %{I:#%I%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
+ 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, %{R:mvf%16-19d%}, %{R:mvf%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
+ 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, %{R:mvd%16-19d%}, %{R:mvd%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
+ 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
+ 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, %{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
+ 0x0e300400, 0x0ff00fff, "cfabss%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
+ 0x0e300420, 0x0ff00fff, "cfabsd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
+ 0x0e300440, 0x0ff00fff, "cfnegs%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
+ 0x0e300460, 0x0ff00fff, "cfnegd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
+ 0x0e300480, 0x0ff00ff0, "cfadds%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}, %{R:mvf%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
+ 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}, %{R:mvd%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
+ 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}, %{R:mvf%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
+ 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}, %{R:mvd%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
+ 0x0e100400, 0x0ff00ff0, "cfmuls%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}, %{R:mvf%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
+ 0x0e100420, 0x0ff00ff0, "cfmuld%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}, %{R:mvd%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
+ 0x0e300500, 0x0ff00fff, "cfabs32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
+ 0x0e300520, 0x0ff00fff, "cfabs64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
+ 0x0e300540, 0x0ff00fff, "cfneg32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
+ 0x0e300560, 0x0ff00fff, "cfneg64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
+ 0x0e300580, 0x0ff00ff0, "cfadd32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
+ 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
+ 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
+ 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
+ 0x0e100500, 0x0ff00ff0, "cfmul32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
+ 0x0e100520, 0x0ff00ff0, "cfmul64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
+ 0x0e100540, 0x0ff00ff0, "cfmac32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
- 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
+ 0x0e100560, 0x0ff00ff0, "cfmsc32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000600, 0x0ff00f10,
- "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
+ "cfmadd32%c\t%{R:mvax%5-7d%}, %{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100600, 0x0ff00f10,
- "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
+ "cfmsub32%c\t%{R:mvax%5-7d%}, %{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e200600, 0x0ff00f10,
- "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
+ "cfmadda32%c\t%{R:mvax%5-7d%}, %{R:mvax%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300600, 0x0ff00f10,
- "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
+ "cfmsuba32%c\t%{R:mvax%5-7d%}, %{R:mvax%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
/* VFP Fused multiply add instructions. */
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
@@ -1262,25 +1262,25 @@ static const struct sopcode32 coprocessor_opcodes[] =
{ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
/* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
- 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
+ 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%24?29%24'70%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
- 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
+ 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%24?29%24'70%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
- 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
+ 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23'90%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
- 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
+ 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23?21%23?780%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
- 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
+ 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23'90%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
- 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
+ 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, %{I:#%23?21%23?780%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
- 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
+ 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}, %{I:#%20'90%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
- 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
+ 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}, %{I:#%20?21%20?780%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
- 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
+ 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %{R:%0-3,5D[0]%}, %{I:#%20'90%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
- 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
+ 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %{R:%0-3,5D[0]%}, %{I:#%20?21%20?780%}"},
/* BFloat16 instructions. */
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
@@ -1290,25 +1290,25 @@ static const struct sopcode32 coprocessor_opcodes[] =
{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
{ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
- 0xfe200d00, 0xff200f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
+ 0xfe200d00, 0xff200f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %{R:%0-3D[%5?10]%}"},
/* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
- 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
+ 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-3d%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
- 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
+ 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-3d%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
- 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
+ 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-3,5d%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
- 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
+ 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-3,5d%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
- 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
+ 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-2d[%3d]%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
- 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
+ 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, %{R:s%7,16-19d%}, %{R:s%5,0-2d[%3d]%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
- 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
+ 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-2d[%3,5d]%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
- 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
+ 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, %{R:d%16-19,7d%}, %{R:d%0-2d[%3,5d]%}"},
/* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
cp_num: bit <11:8> == 0b1001.
@@ -1320,11 +1320,11 @@ static const struct sopcode32 coprocessor_opcodes[] =
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
- 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
+ 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, %{I:#0.0%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
- 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
+ 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, %{I:#%5,0-3k%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
- 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
+ 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, %{I:#%5,0-3k%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
@@ -1362,7 +1362,7 @@ static const struct sopcode32 coprocessor_opcodes[] =
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
- 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
+ 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, %{I:#%0-3,16-19E%}"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
{ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
@@ -1398,49 +1398,49 @@ static const struct sopcode32 generic_coprocessor_opcodes[] =
{
/* Generic coprocessor instructions. */
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
- 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
+ 0x0c400000, 0x0ff00000, "mcrr%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15R, %16-19r, %{R:cr%0-3d%}"},
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
0x0c500000, 0x0ff00000,
- "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
+ "mrrc%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15Ru, %16-19Ru, %{R:cr%0-3d%}"},
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
0x0e000000, 0x0f000010,
- "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
+ "cdp%c\t%{I:%8-11d%}, %{I:%20-23d%}, %{R:cr%12-15d%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
0x0e10f010, 0x0f10f010,
- "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
+ "mrc%c\t%{I:%8-11d%}, %{I:%21-23d%}, %{R:APSR_nzcv%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
0x0e100010, 0x0f100010,
- "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
+ "mrc%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15r, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
0x0e000010, 0x0f100010,
- "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
+ "mcr%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15R, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
- 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
+ 0x0c000000, 0x0e100000, "stc%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
- 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
+ 0x0c100000, 0x0e100000, "ldc%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
/* V6 coprocessor instructions. */
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0xfc500000, 0xfff00000,
- "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
+ "mrrc2%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15Ru, %16-19Ru, %{R:cr%0-3d%}"},
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0xfc400000, 0xfff00000,
- "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
+ "mcrr2%c\t%{I:%8-11d%}, %{I:%4-7d%}, %12-15R, %16-19R, %{R:cr%0-3d%}"},
/* V5 coprocessor instructions. */
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
- 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
+ 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
- 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
+ 0xfc000000, 0xfe100000, "stc2%22'l%c\t%{I:%8-11d%}, %{R:cr%12-15d%}, %A"},
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
0xfe000000, 0xff000010,
- "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
+ "cdp2%c\t%{I:%8-11d%}, %{I:%20-23d%}, %{R:cr%12-15d%}, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
0xfe000010, 0xff100010,
- "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
+ "mcr2%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15R, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
{ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
0xfe100010, 0xff100010,
- "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
+ "mrc2%c\t%{I:%8-11d%}, %{I:%21-23d%}, %12-15r, %{R:cr%16-19d%}, %{R:cr%0-3d%}, {%{I:%5-7d%}}"},
{ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
};
@@ -1482,10 +1482,10 @@ static const struct opcode32 neon_opcodes[] =
/* Extract. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2b00840, 0xffb00850,
- "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
+ "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, %{I:#%8-11d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2b00000, 0xffb00810,
- "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
+ "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, %{I:#%8-11d%}"},
/* Data transfer between ARM and NEON registers. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
@@ -1503,11 +1503,11 @@ static const struct opcode32 neon_opcodes[] =
/* Move data element to all lanes. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
+ 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %{R:%0-3,5D[%19d]%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
+ 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %{R:%0-3,5D[%18-19d]%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
+ 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %{R:%0-3,5D[%17-19d]%}"},
/* Table lookup. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
@@ -1535,7 +1535,7 @@ static const struct opcode32 neon_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
0xfc000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
- 0xfe000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
+ 0xfe000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
0xfc000c40, 0xffb00f50, "vmmla.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
@@ -1543,7 +1543,7 @@ static const struct opcode32 neon_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
0xfc300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
- 0xfe300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-2D[%3,5d]"},
+ 0xfe300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %{R:%0-2D[%3,5d]%}"},
/* Matrix Multiply instructions. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
@@ -1555,9 +1555,9 @@ static const struct opcode32 neon_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
0xfca00d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
- 0xfe800d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
+ 0xfe800d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
- 0xfe800d10, 0xffb00f10, "vsudot.u8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
+ 0xfe800d10, 0xffb00f10, "vsudot.u8\t%12-15,22R, %16-19,7R, %{R:d%0-3d[%5d]%}"},
/* Two registers, miscellaneous. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
@@ -1604,7 +1604,7 @@ static const struct opcode32 neon_opcodes[] =
0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b20300, 0xffb30fd0,
- "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
+ "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, %{I:#%18-19S2%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
@@ -1634,15 +1634,15 @@ static const struct opcode32 neon_opcodes[] =
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
+ 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
+ 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
+ 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
+ 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
+ 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, %{I:#0%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
@@ -1881,128 +1881,128 @@ static const struct opcode32 neon_opcodes[] =
/* Two registers and a shift amount. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
+ 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
+ 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
+ 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
+ 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
+ 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2880950, 0xfeb80fd0,
- "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
+ "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, %{I:#%16-18e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
+ 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, %{I:#%16-18d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
+ 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
+ 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
+ 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
+ 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
+ 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
+ 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
+ 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
+ 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
+ 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2900950, 0xfeb00fd0,
- "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
+ "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, %{I:#%16-19e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
+ 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, %{I:#%16-19d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
+ 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
+ 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
+ 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
+ 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
+ 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, %{I:#%16-18d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
+ 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
+ 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
+ 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
+ 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
+ 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
+ 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
+ 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, %{I:#%16-20d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
+ 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
+ 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
+ 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
+ 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
+ 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, %{I:#%16-19d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
+ 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
+ 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
+ 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2a00950, 0xfea00fd0,
- "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
+ "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, %{I:#%16-20e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
+ 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
+ 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
+ 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
+ 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
+ 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
+ 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
+ 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
+ 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
+ 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, %{I:#%16-20d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
+ 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
+ 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
+ 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
+ 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
+ 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
+ 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
+ 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
+ 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21e%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
+ 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, %{I:#%16-21d%}"},
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf2a00e10, 0xfea00e90,
- "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
+ "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xf2a00c10, 0xfea00e90,
- "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
+ "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, %{I:#%16-20e%}"},
/* Three registers of different lengths. */
{ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
@@ -2372,13 +2372,13 @@ static const struct mopcode32 mve_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VCADD_FP,
0xfc800840, 0xfea11f51,
- "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"},
+ "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%24o%}"},
/* Vector VCADD. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VCADD_VEC,
0xfe000f00, 0xff810f51,
- "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
+ "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%12o%}"},
/* Vector VCLS. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
@@ -2396,7 +2396,7 @@ static const struct mopcode32 mve_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VCMLA_FP,
0xfc200840, 0xfe211f51,
- "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"},
+ "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%23-24o%}"},
/* Vector VCMP floating point T1. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
@@ -2505,7 +2505,7 @@ static const struct mopcode32 mve_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VCMUL_FP,
0xee300e00, 0xefb10f50,
- "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"},
+ "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%0,12o%}"},
/* Vector VCTP. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
@@ -2529,7 +2529,7 @@ static const struct mopcode32 mve_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VCVT_FP_FIX_VEC,
0xef800c50, 0xef801cd1,
- "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
+ "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, %{I:#%16-21k%}"},
/* Vector VCVT. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
@@ -2559,31 +2559,31 @@ static const struct mopcode32 mve_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VDDUP,
0xee011f6e, 0xff811f7e,
- "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
+ "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, %{I:#%0,7u%}"},
/* Vector VDWDUP. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VDWDUP,
0xee011f60, 0xff811f70,
- "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
+ "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, %{I:#%0,7u%}"},
/* Vector VHCADD. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VHCADD,
0xee000f00, 0xff810f51,
- "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
+ "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, %{I:#%12o%}"},
/* Vector VIWDUP. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VIWDUP,
0xee010f60, 0xff811f70,
- "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
+ "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, %{I:#%0,7u%}"},
/* Vector VIDUP. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VIDUP,
0xee010f6e, 0xff811f7e,
- "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
+ "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, %{I:#%0,7u%}"},
/* Vector VLD2. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
@@ -2625,13 +2625,13 @@ static const struct mopcode32 mve_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VLDRW_GATHER_T5,
0xfd101e00, 0xff111f00,
- "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
+ "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
/* Vector VLDRD gather load, variant T6. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VLDRD_GATHER_T6,
0xfd101f00, 0xff111f00,
- "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
+ "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
/* Vector VLDRB. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
@@ -2848,7 +2848,7 @@ static const struct mopcode32 mve_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VMOV_GP_TO_VEC_LANE,
0xee000b10, 0xff900f1f,
- "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
+ "vmov%c.%5-6,21-22s\t%{R:%17-19,7Q[%N]%}, %12-15r"},
/* Vector VORR immediate to vector.
NOTE: MVE_VORR_IMM must appear in the table
@@ -2864,7 +2864,7 @@ static const struct mopcode32 mve_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VQSHL_T2,
0xef800750, 0xef801fd1,
- "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
/* Vector VQSHLU T3 Variant
NOTE: MVE_VQSHL_T2 must appear in the table before
@@ -2873,7 +2873,7 @@ static const struct mopcode32 mve_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VQSHLU_T3,
0xff800650, 0xff801fd1,
- "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
/* Vector VRSHR
NOTE: MVE_VRSHR must appear in the table before
@@ -2881,7 +2881,7 @@ static const struct mopcode32 mve_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VRSHR,
0xef800250, 0xef801fd1,
- "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
/* Vector VSHL.
NOTE: MVE_VSHL must appear in the table before
@@ -2889,7 +2889,7 @@ static const struct mopcode32 mve_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSHL_T1,
0xef800550, 0xff801fd1,
- "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
/* Vector VSHR
NOTE: MVE_VSHR must appear in the table before
@@ -2897,7 +2897,7 @@ static const struct mopcode32 mve_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSHR,
0xef800050, 0xef801fd1,
- "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
/* Vector VSLI
NOTE: MVE_VSLI must appear in the table before
@@ -2905,7 +2905,7 @@ static const struct mopcode32 mve_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSLI,
0xff800550, 0xff801fd1,
- "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
/* Vector VSRI
NOTE: MVE_VSRI must appear in the table before
@@ -2913,7 +2913,7 @@ static const struct mopcode32 mve_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSRI,
0xff800450, 0xff801fd1,
- "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
/* Vector VMOV immediate to vector,
undefinded for cmode == 1111 */
@@ -2936,38 +2936,38 @@ static const struct mopcode32 mve_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VMOV2_VEC_LANE_TO_GP,
0xec000f00, 0xffb01ff0,
- "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
+ "vmov%c\t%0-3r, %16-19r, %{R:%13-15,22Q[2]%}, %{R:%13-15,22Q[0]%}"},
/* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VMOV2_VEC_LANE_TO_GP,
0xec000f10, 0xffb01ff0,
- "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
+ "vmov%c\t%0-3r, %16-19r, %{R:%13-15,22Q[3]%}, %{R:%13-15,22Q[1]%}"},
/* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VMOV2_GP_TO_VEC_LANE,
0xec100f00, 0xffb01ff0,
- "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
+ "vmov%c\t%{R:%13-15,22Q[2]%}, %{R:%13-15,22Q[0]%}, %0-3r, %16-19r"},
/* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VMOV2_GP_TO_VEC_LANE,
0xec100f10, 0xffb01ff0,
- "vmov%c\t%13-15,22Q[3], %13-15,22Q[1], %0-3r, %16-19r"},
+ "vmov%c\t%{R:%13-15,22Q[3]%}, %{R:%13-15,22Q[1]%}, %0-3r, %16-19r"},
/* Vector VMOV Vector lane to gpr. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP),
MVE_VMOV_VEC_LANE_TO_GP,
0xee100b10, 0xff100f1f,
- "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
+ "vmov%c.%u%5-6,21-22s\t%12-15r, %{R:%17-19,7Q[%N]%}"},
/* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due
to instruction opcode aliasing. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSHLL_T1,
0xeea00f40, 0xefa00fd1,
- "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
/* Vector VMOVL long. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
@@ -3229,13 +3229,13 @@ static const struct mopcode32 mve_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VQRSHRN,
0xee800f41, 0xefa00fd1,
- "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
/* Vector VQRSHRUN. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VQRSHRUN,
0xfe800fc0, 0xffa00fd1,
- "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
/* Vector VQSHL T1 Variant. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
@@ -3253,13 +3253,13 @@ static const struct mopcode32 mve_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VQSHRN,
0xee800f40, 0xefa00fd1,
- "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
/* Vector VQSHRUN. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VQSHRUN,
0xee800fc0, 0xffa00fd1,
- "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
/* Vector VQSUB T1 Variant. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
@@ -3325,7 +3325,7 @@ static const struct mopcode32 mve_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VRSHRN,
0xfe800fc1, 0xffa00fd1,
- "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
/* Vector VSBC. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
@@ -3349,19 +3349,19 @@ static const struct mopcode32 mve_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSHLC,
0xeea00fc0, 0xffa01ff0,
- "vshlc%v\t%13-15,22Q, %0-3r, #%16-20d"},
+ "vshlc%v\t%13-15,22Q, %0-3r, %{I:#%16-20d%}"},
/* Vector VSHLL T2 Variant. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSHLL_T2,
0xee310e01, 0xefb30fd1,
- "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, #%18-19d"},
+ "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, %{I:#%18-19d%}"},
/* Vector VSHRN. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSHRN,
0xee800fc1, 0xffa00fd1,
- "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
+ "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, %{I:#%16-18d%}"},
/* Vector VST2 no writeback. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
@@ -3415,13 +3415,13 @@ static const struct mopcode32 mve_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSTRW_SCATTER_T5,
0xfd001e00, 0xff111f00,
- "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
+ "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
/* Vector VSTRD scatter store, T6 variant. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
MVE_VSTRD_SCATTER_T6,
0xfd001f00, 0xff111f00,
- "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
+ "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, %{I:#%a%0-6i%}]%w"},
/* Vector VSTRB. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE),
@@ -3659,7 +3659,7 @@ static const struct opcode32 arm_opcodes[] =
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
0xe1a00000, 0xffffffff, "nop\t\t\t@ (mov r0, r0)"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
- 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
+ 0xe7f000f0, 0xfff000f0, "udf\t%{I:#%e%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
@@ -3689,7 +3689,7 @@ static const struct opcode32 arm_opcodes[] =
0x0320f005, 0x0fffffff, "sevl"},
/* Defined in V8 but is in NOP space so available to all arch. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
- 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
+ 0xe1000070, 0xfff000f0, "hlt\t%{I:0x%16-19X%12-15X%8-11X%0-3X%}"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
{ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
@@ -3734,7 +3734,7 @@ static const struct opcode32 arm_opcodes[] =
/* Privileged Access Never extension instructions. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
- 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
+ 0xf1100000, 0xfffffdff, "setpan\t%{I:#%9-9d%}"},
/* Virtualization Extension instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
@@ -3756,14 +3756,14 @@ static const struct opcode32 arm_opcodes[] =
/* V7 instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t%{I:#%0-3d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
- 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
+ 0x0320f000, 0x0fffffff, "nop%c\t{%{I:%0-7d%}}"},
/* ARM V6T2 instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
@@ -3787,7 +3787,7 @@ static const struct opcode32 arm_opcodes[] =
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
- 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
+ 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, %{I:#%7-11d%}, %{I:#%16-20W%}"},
/* ARM Security extension instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
@@ -3822,29 +3822,29 @@ static const struct opcode32 arm_opcodes[] =
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
0x0320f004, 0x0fffffff, "sev%c"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
- 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
+ 0x0320f000, 0x0fffff00, "nop%c\t{%{I:%0-7d%}}"},
/* ARM V6 instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
+ 0xf1080000, 0xfffffe3f, "cpsie\t%{B:%8'a%7'i%6'f%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
+ 0xf10a0000, 0xfffffe20, "cpsie\t%{B:%8'a%7'i%6'f%},%{I:#%0-4d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
+ 0xf10C0000, 0xfffffe3f, "cpsid\t%{B:%8'a%7'i%6'f%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
+ 0xf10e0000, 0xfffffe20, "cpsid\t%{B:%8'a%7'i%6'f%},%{I:#%0-4d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
+ 0xf1000000, 0xfff1fe20, "cps\t%{I:#%0-4d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
+ 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, %{B:lsl%} %{I:#%7-11d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
+ 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, %{B:asr%} %{I:#32%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
+ 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, %{B:asr%} %{I:#%7-11d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
+ 0x01900f9f, 0x0ff00fff, "ldrex%c\t%{R:r%12-15d%}, [%16-19R]"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
@@ -3928,103 +3928,103 @@ static const struct opcode32 arm_opcodes[] =
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
+ 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
+ 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
+ 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
+ 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
+ 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
+ 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
+ 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
+ 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
+ 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
+ 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
+ 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
+ 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
+ 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
+ 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
+ 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
+ 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#8%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
+ 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#16%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
+ 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, %{B:ror%} %{I:#24%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
+ 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
+ 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
+ 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
+ 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
+ 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
+ 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
+ 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
+ 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
+ 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
+ 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
+ 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
+ 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
+ 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
+ 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
+ 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR %{I:#24%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
+ 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#8%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
+ 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#16%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
+ 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, %{B:ror%} %{I:#24%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
+ 0xf1010000, 0xfffffc00, "setend\t%{B:%9?ble%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
@@ -4044,15 +4044,15 @@ static const struct opcode32 arm_opcodes[] =
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
+ 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, %{I:#%0-4d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
+ 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
+ 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R, %{B:lsl%} %{I:#%7-11d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
+ 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, %{I:#%16-20W%}, %0-3R, %{B:asr%} %{I:#%7-11d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
+ 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, %{I:#%16-19W%}, %0-3r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
@@ -4062,13 +4062,13 @@ static const struct opcode32 arm_opcodes[] =
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
+ 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
+ 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R, %{B:lsl%} %{I:#%7-11d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
+ 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, %{I:#%16-20d%}, %0-3R, %{B:asr%} %{I:#%7-11d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
+ 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, %{I:#%16-19d%}, %0-3R"},
/* V5J instruction. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
@@ -4077,7 +4077,7 @@ static const struct opcode32 arm_opcodes[] =
/* V5 Instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
0xe1200070, 0xfff000f0,
- "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
+ "bkpt\t%{I:0x%16-19X%12-15X%8-11X%0-3X%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
0xfa000000, 0xfe000000, "blx\t%B"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
@@ -4398,7 +4398,7 @@ static const struct opcode32 arm_opcodes[] =
/* The rest. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
- 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
+ 0x03200000, 0x0fff00ff, "nop%c\t{%{I:%0-7d%}}" UNPREDICTABLE_INSTRUCTION},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
{ARM_FEATURE_CORE_LOW (0),
@@ -4443,7 +4443,7 @@ static const struct opcode16 thumb_opcodes[] =
/* ARM V8 instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t#%3-3d"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN), 0xb610, 0xfff7, "setpan\t%{I:#%3-3d%}"},
/* ARM V6K no-argument instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
@@ -4461,13 +4461,13 @@ static const struct opcode16 thumb_opcodes[] =
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
/* ARM V6. */
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%{B:%2'a%1'i%0'f%}%X"},
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%{B:%2'a%1'i%0'f%}%X"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%{B:%3?ble%}%X"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
@@ -4500,8 +4500,8 @@ static const struct opcode16 thumb_opcodes[] =
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
/* format 13 */
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\t%{R:sp%}, %{I:#%0-6W%}"},
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\t%{R:sp%}, %{I:#%0-6W%}"},
/* format 5 */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
@@ -4516,9 +4516,9 @@ static const struct opcode16 thumb_opcodes[] =
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
+ 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, %{I:#%6-8d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
+ 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, %{I:#%6-8d%}"},
/* format 8 */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
@@ -4534,50 +4534,50 @@ static const struct opcode16 thumb_opcodes[] =
/* format 1 */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
+ 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, %{I:#%6-10d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
/* format 3 */
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, %{I:#%0-7d%}"},
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, %{I:#%0-7d%}"},
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, %{I:#%0-7d%}"},
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, %{I:#%0-7d%}"},
/* format 6 */
/* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
0x4800, 0xF800,
- "ldr%c\t%8-10r, [pc, #%0-7W]\t@ (%0-7a)"},
+ "ldr%c\t%8-10r, [%{R:pc%}, %{I:#%0-7W%}]\t@ (%0-7a)"},
/* format 9 */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
+ 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, %{I:#%6-10W%}]"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
+ 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, %{I:#%6-10W%}]"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
+ 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, %{I:#%6-10d%}]"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
+ 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, %{I:#%6-10d%}]"},
/* format 10 */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
+ 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, %{I:#%6-10H%}]"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
+ 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, %{I:#%6-10H%}]"},
/* format 11 */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
+ 0x9000, 0xF800, "str%c\t%8-10r, [%{R:sp%}, %{I:#%0-7W%}]"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
+ 0x9800, 0xF800, "ldr%c\t%8-10r, [%{R:sp%}, %{I:#%0-7W%}]"},
/* format 12 */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t@ (adr %8-10r, %0-7a)"},
+ 0xA000, 0xF800, "add%c\t%8-10r, %{R:pc%}, %{I:#%0-7W%}\t@ (adr %8-10r, %0-7a)"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
- 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
+ 0xA800, 0xF800, "add%c\t%8-10r, %{R:sp%}, %{I:#%0-7W%}"},
/* format 15 */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
/* format 17 */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
/* format 16 */
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t%{I:#%0-7d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
/* format 18 */
@@ -4655,7 +4655,7 @@ static const struct opcode32 thumb32_opcodes[] =
/* Arm v8.1-M Mainline Pointer Authentication and Branch Target
Identification Extension. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
- 0xf3af802d, 0xffffffff, "aut\tr12, lr, sp"},
+ 0xf3af802d, 0xffffffff, "aut\t%{R:r12%}, %{R:lr%}, %{R:sp%}"},
{ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
0xfb500f00, 0xfff00ff0, "autg%c\t%12-15r, %16-19r, %0-3r"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
@@ -4663,9 +4663,9 @@ static const struct opcode32 thumb32_opcodes[] =
{ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
0xfb500f10, 0xfff00ff0, "bxaut%c\t%12-15r, %16-19r, %0-3r"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
- 0xf3af801d, 0xffffffff, "pac\tr12, lr, sp"},
+ 0xf3af801d, 0xffffffff, "pac\t%{R:r12%}, %{R:lr%}, %{R:sp%}"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
- 0xf3af800d, 0xffffffff, "pacbti\tr12, lr, sp"},
+ 0xf3af800d, 0xffffffff, "pacbti\t%{R:r12%}, %{R:lr%}, %{R:sp%}"},
{ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
0xfb60f000, 0xfff0f0f0, "pacg%c\t%8-11r, %16-19r, %0-3r"},
@@ -4676,17 +4676,17 @@ static const struct opcode32 thumb32_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
0xf02fc001, 0xfffff001, "le\t%P"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
- 0xf00fc001, 0xfffff001, "le\tlr, %P"},
+ 0xf00fc001, 0xfffff001, "le\t%{R:lr%}, %P"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
- 0xf01fc001, 0xfffff001, "letp\tlr, %P"},
+ 0xf01fc001, 0xfffff001, "letp\t%{R:lr%}, %P"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
- 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
+ 0xf040c001, 0xfff0f001, "wls\t%{R:lr%}, %16-19S, %Q"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN[...]
[diff truncated at 100000 bytes]
^ permalink raw reply [flat|nested] only message in thread
only message in thread, other threads:[~2022-10-19 10:06 UTC | newest]
Thread overview: (only message) (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-10-19 10:06 [binutils-gdb/upstream/users/aburgess/arm-disasm-styling] opcodes/arm: add disassembler styling for arm Andrew Burgess
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).