From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1464) id F41723858402; Tue, 8 Nov 2022 18:18:16 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org F41723858402 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Peter Bergner To: bfd-cvs@sourceware.org Subject: [binutils-gdb] PowerPC: Add XSP operand define X-Act-Checkin: binutils-gdb X-Git-Author: Peter Bergner X-Git-Refname: refs/heads/master X-Git-Oldrev: be6a2dca1505a4597fa3de71a85e7957d8d470ff X-Git-Newrev: 7dacb40b89b19382bb2597c5e26f347985d4edb5 Message-Id: <20221108181816.F41723858402@sourceware.org> Date: Tue, 8 Nov 2022 18:18:16 +0000 (GMT) X-BeenThere: binutils-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 08 Nov 2022 18:18:17 -0000 https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D7dacb40b89b1= 9382bb2597c5e26f347985d4edb5 commit 7dacb40b89b19382bb2597c5e26f347985d4edb5 Author: Peter Bergner Date: Tue Nov 8 12:15:06 2022 -0600 PowerPC: Add XSP operand define =20 opcodes/ * ppc-opc.c (XSP): New define. (powerpc_opcodes) : Use it. Diff: --- opcodes/ppc-opc.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index cf729029dac..4d67d2581b1 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -2332,7 +2332,7 @@ extract_xc6 (uint64_t insn, return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f); } =20 -/* The split XTp field in a vector paired insn. */ +/* The split XTp and XSp field in a vector paired insn. */ =20 static uint64_t insert_xtp (uint64_t insn, @@ -3822,8 +3822,9 @@ const struct powerpc_operand powerpc_operands[] =3D #define XTQ6 XSQ6 { 0x3f, PPC_OPSHIFT_INV, insert_xtq6, extract_xtq6, PPC_OPERAND_VSR }, =20 - /* The split XTp field in a vector paired instruction. */ + /* The split XTp and XSp field in a vector paired instruction. */ #define XTP XSQ6 + 1 +#define XSP XTP { 0x3e, PPC_OPSHIFT_INV, insert_xtp, extract_xtp, PPC_OPERAND_VSR }, =20 #define XTS XTP + 1 @@ -6024,7 +6025,7 @@ const struct powerpc_opcode powerpc_opcodes[] =3D { {"dcbz_l", X (4,1014), XRT_MASK, PPCPS, 0, {RA, RB}}, =20 {"lxvp", DQXP(6,0), DQXP_MASK, POWER10, PPCVLE, {XTP, DQ, RA0}}, -{"stxvp", DQXP(6,1), DQXP_MASK, POWER10, PPCVLE, {XTP, DQ, RA0}}, +{"stxvp", DQXP(6,1), DQXP_MASK, POWER10, PPCVLE, {XSP, DQ, RA0}}, =20 {"mulli", OP(7), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, {"muli", OP(7), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, @@ -8080,7 +8081,7 @@ const struct powerpc_opcode powerpc_opcodes[] =3D { {"divwu", XO(31,459,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, {"divwu.", XO(31,459,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, =20 -{"stxvpx", X(31,461), XX1_MASK, POWER10, 0, {XTP, RA0, RB}}, +{"stxvpx", X(31,461), XX1_MASK, POWER10, 0, {XSP, RA0, RB}}, =20 {"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, 0, {PMR, RS}}, {"mttmr", X(31,494), X_MASK, PPCTMR, 0, {TMR, RS}}, @@ -9854,7 +9855,7 @@ const struct powerpc_opcode prefix_opcodes[] =3D { {"pmxvf64gernn", PMMIRR|XX3(59,250), P_GER64_MASK, POWER10, 0, {ACC, XA6= ap, XB6a, XMSK, YMSK2}}, {"pstq", P8LS|OP(60), P_D_MASK, POWER10, 0, {RSQ, D34, PRA0, PCRE= L}}, {"pstd", P8LS|OP(61), P_D_MASK, POWER10, 0, {RS, D34, PRA0, PCREL= }}, -{"pstxvp", P8LS|OP(62), P_D_MASK, POWER10, 0, {XTP, D34, PRA0, PC= REL}}, +{"pstxvp", P8LS|OP(62), P_D_MASK, POWER10, 0, {XSP, D34, PRA0, PC= REL}}, }; =20 const unsigned int prefix_num_opcodes =3D ARRAY_SIZE (prefix_opcodes);