From: Nelson Chu <nelsonc1225@sourceware.org>
To: bfd-cvs@sourceware.org
Subject: [binutils-gdb] RISC-V: Make R_RISCV_SUB6 conforms to riscv ABI standard
Date: Wed, 23 Nov 2022 02:46:57 +0000 (GMT) [thread overview]
Message-ID: <20221123024657.28ED03858298@sourceware.org> (raw)
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=06f0a892a5260d8fe93550ed96364cc76fef971d
commit 06f0a892a5260d8fe93550ed96364cc76fef971d
Author: Xiao Zeng <zengxiao@eswincomputing.com>
Date: Mon Nov 21 20:00:37 2022 +0800
RISC-V: Make R_RISCV_SUB6 conforms to riscv ABI standard
According to the riscv psabi, R_RISCV_SUB6 only allows 6 least significant
bits are valid, but since binutils implementation, we usually get 8 bits
field for it. That means, the high 2 bits could be other field and have
different purpose. Therefore, we should filter the 8 bits to 6 bits before
calculate, and then only encode the valid 6 bits back. By the way, we also
need the out-of-range check for R_RISCV_SUB6, and the overflow checks for
all R_RISCV_ADD/SUB/SET relocations, but we can add them in the future patches.
Passing riscv-gnu-toolchain regressions.
bfd/ChangeLog:
* elfnn-riscv.c (riscv_elf_relocate_section): Take the R_RISCV_SUB6
lower 6 bits as the significant bit.
* elfxx-riscv.c (riscv_elf_add_sub_reloc): Likewise.
Diff:
---
bfd/elfnn-riscv.c | 9 +++++++++
bfd/elfxx-riscv.c | 4 ++++
2 files changed, 13 insertions(+)
diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
index 0570a971b5a..a2d85dbe939 100644
--- a/bfd/elfnn-riscv.c
+++ b/bfd/elfnn-riscv.c
@@ -2427,6 +2427,15 @@ riscv_elf_relocate_section (bfd *output_bfd,
break;
case R_RISCV_SUB6:
+ {
+ bfd_vma old_value = bfd_get (howto->bitsize, input_bfd,
+ contents + rel->r_offset);
+ relocation = (old_value & ~howto->dst_mask)
+ | (((old_value & howto->dst_mask) - relocation)
+ & howto->dst_mask);
+ }
+ break;
+
case R_RISCV_SUB8:
case R_RISCV_SUB16:
case R_RISCV_SUB32:
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index afbde56b9e5..ff9607e7966 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -994,6 +994,10 @@ riscv_elf_add_sub_reloc (bfd *abfd,
relocation = old_value + relocation;
break;
case R_RISCV_SUB6:
+ relocation = (old_value & ~howto->dst_mask)
+ | (((old_value & howto->dst_mask) - relocation)
+ & howto->dst_mask);
+ break;
case R_RISCV_SUB8:
case R_RISCV_SUB16:
case R_RISCV_SUB32:
reply other threads:[~2022-11-23 2:46 UTC|newest]
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