From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1386) id 117093858D32; Thu, 1 Dec 2022 09:00:49 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 117093858D32 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Jan Beulich To: bfd-cvs@sourceware.org Subject: [binutils-gdb] x86/Intel: restrict use of LONG_DOUBLE_MNEM_SUFFIX X-Act-Checkin: binutils-gdb X-Git-Author: Jan Beulich X-Git-Refname: refs/heads/master X-Git-Oldrev: f0cb4aa909d0e3c1c656b2ba9758a59a2cde75de X-Git-Newrev: f210f0a05ea30b5bca75aa516873f1784ae331b4 Message-Id: <20221201090049.117093858D32@sourceware.org> Date: Thu, 1 Dec 2022 09:00:49 +0000 (GMT) X-BeenThere: binutils-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 01 Dec 2022 09:00:49 -0000 https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3Df210f0a05ea3= 0b5bca75aa516873f1784ae331b4 commit f210f0a05ea30b5bca75aa516873f1784ae331b4 Author: Jan Beulich Date: Thu Dec 1 09:59:11 2022 +0100 x86/Intel: restrict use of LONG_DOUBLE_MNEM_SUFFIX =20 As a comment near the top of match_template() already says: We really only need this pseudo-suffix for far branch handling. Stop "deriving" it for floating point insns. (Don't bother renaming the now properly misnamed LONG_DOUBLE_MNEM_SUFFIX, to e.g. FAR_BRANCH_SUFFIX - it's going to disappear anyway.) Diff: --- gas/config/tc-i386-intel.c | 14 +++++++------- opcodes/i386-opc.tbl | 8 ++++---- opcodes/i386-tbl.h | 8 ++++---- 3 files changed, 15 insertions(+), 15 deletions(-) diff --git a/gas/config/tc-i386-intel.c b/gas/config/tc-i386-intel.c index ce4be6ac7dd..650a24bc00b 100644 --- a/gas/config/tc-i386-intel.c +++ b/gas/config/tc-i386-intel.c @@ -749,13 +749,13 @@ i386_intel_operand (char *operand_string, int got_a_f= loat) =20 case O_tbyte_ptr: i.types[this_operand].bitfield.tbyte =3D 1; - if (got_a_float =3D=3D 1) - suffix =3D LONG_DOUBLE_MNEM_SUFFIX; - else if ((current_templates->start->operand_types[0].bitfield.fword - || current_templates->start->operand_types[0].bitfield.tbyte - || current_templates->start->opcode_modifier.jump =3D=3D JUMP_DWORD - || current_templates->start->opcode_modifier.jump =3D=3D JUMP) - && flag_code =3D=3D CODE_64BIT) + if (got_a_float) + break; + if (flag_code =3D=3D CODE_64BIT + && (current_templates->start->operand_types[0].bitfield.fword + || current_templates->start->operand_types[0].bitfield.tbyte + || current_templates->start->opcode_modifier.jump =3D=3D JUMP_DWORD + || current_templates->start->opcode_modifier.jump =3D=3D JUMP)) suffix =3D QWORD_MNEM_SUFFIX; /* l[fgs]s, [ls][gi]dt, call, jmp */ else i.types[this_operand].bitfield.byte =3D 1; /* cause an error */ diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 2100352132c..390491ef0cd 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -607,12 +607,12 @@ fld, 0xd9c0, None, CpuFP, NoSuf, { FloatReg } fld, 0xd9, 0, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dwo= rd|Qword|Unspecified|BaseIndex } fld, 0xd9c0, None, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ld= Suf|Ugh, { FloatReg } // Intel Syntax -fld, 0xdb, 5, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Tbyt= e|Unspecified|BaseIndex } +fld, 0xdb, 5, CpuFP, Modrm|NoSuf, { Tbyte|Unspecified|BaseIndex } fild, 0xdf, 0, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Wo= rd|Dword|Unspecified|BaseIndex } fild, 0xdf, 5, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex= 64, { Qword|Unspecified|BaseIndex } fildll, 0xdf, 5, CpuFP, Modrm|NoSuf|ATTSyntax, { Unspecified|BaseIndex } fldt, 0xdb, 5, CpuFP, Modrm|NoSuf, { Unspecified|BaseIndex } -fbld, 0xdf, 4, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Tby= te|Unspecified|BaseIndex } +fbld, 0xdf, 4, CpuFP, Modrm|NoSuf, { Tbyte|Unspecified|BaseIndex } =20 // store (no pop) fst, 0xddd0, None, CpuFP, NoSuf, { FloatReg } @@ -625,12 +625,12 @@ fstp, 0xddd8, None, CpuFP, NoSuf, { FloatReg } fstp, 0xd9, 3, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dw= ord|Qword|Unspecified|BaseIndex } fstp, 0xddd8, None, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_l= dSuf|Ugh, { FloatReg } // Intel Syntax -fstp, 0xdb, 7, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Tby= te|Unspecified|BaseIndex } +fstp, 0xdb, 7, CpuFP, Modrm|NoSuf, { Tbyte|Unspecified|BaseIndex } fistp, 0xdf, 3, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { W= ord|Dword|Unspecified|BaseIndex } fistp, 0xdf, 7, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRe= x64, { Qword|Unspecified|BaseIndex } fistpll, 0xdf, 7, CpuFP, Modrm|NoSuf|ATTSyntax, { Unspecified|BaseIndex } fstpt, 0xdb, 7, CpuFP, Modrm|NoSuf, { Unspecified|BaseIndex } -fbstp, 0xdf, 6, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Tb= yte|Unspecified|BaseIndex } +fbstp, 0xdf, 6, CpuFP, Modrm|NoSuf, { Tbyte|Unspecified|BaseIndex } =20 // exchange %st with %st0 fxch, 0xd9c8, None, CpuFP, NoSuf, { FloatReg } diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index 2b334700d89..752478b28e3 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -5710,7 +5710,7 @@ const insn_template i386_optab[] =3D { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } } } }, { "fld", 0xdb, 1, 5, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, @@ -5775,7 +5775,7 @@ const insn_template i386_optab[] =3D { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } } } }, { "fbld", 0xdf, 1, 4, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, @@ -5879,7 +5879,7 @@ const insn_template i386_optab[] =3D { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } } } }, { "fstp", 0xdb, 1, 7, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, @@ -5944,7 +5944,7 @@ const insn_template i386_optab[] =3D { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } } } }, { "fbstp", 0xdf, 1, 6, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0,