* [binutils-gdb] x86-64: LAR and LSL don't need REX.W
@ 2023-02-22 13:13 Jan Beulich
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From: Jan Beulich @ 2023-02-22 13:13 UTC (permalink / raw)
To: bfd-cvs
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=ba25141c1e520f20c210b42fec19823667e83b8e
commit ba25141c1e520f20c210b42fec19823667e83b8e
Author: Jan Beulich <jbeulich@suse.com>
Date: Wed Feb 22 14:12:52 2023 +0100
x86-64: LAR and LSL don't need REX.W
Just like we suppress emitting REX.W for e.g. MOV from/to segment
register, there's also no need for it for LAR and LSL - these can only
ever return 32-bit values and hence always zero-extend their results
anyway.
While there also drop the redundant Word from the first operand of
the second template each - this is already implied by Reg16.
Diff:
---
gas/testsuite/gas/i386/x86_64-intel.d | 24 ++++++++++++------------
gas/testsuite/gas/i386/x86_64.d | 24 ++++++++++++------------
opcodes/i386-opc.tbl | 8 ++++----
opcodes/i386-tbl.h | 8 ++++----
4 files changed, 32 insertions(+), 32 deletions(-)
diff --git a/gas/testsuite/gas/i386/x86_64-intel.d b/gas/testsuite/gas/i386/x86_64-intel.d
index a2d5668eebf..bd99ce0db51 100644
--- a/gas/testsuite/gas/i386/x86_64-intel.d
+++ b/gas/testsuite/gas/i386/x86_64-intel.d
@@ -260,34 +260,34 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 89 0c 25 00 00 00 00 mov QWORD PTR (ds:)?0x0,rcx
[ ]*[a-f0-9]+: 66 0f 02 d2 lar dx,dx
[ ]*[a-f0-9]+: 0f 02 d2 lar edx,edx
-[ ]*[a-f0-9]+: 48 0f 02 d2 lar rdx,rdx
[ ]*[a-f0-9]+: 0f 02 d2 lar edx,edx
-[ ]*[a-f0-9]+: 48 0f 02 d2 lar rdx,rdx
+[ ]*[a-f0-9]+: 0f 02 d2 lar edx,edx
+[ ]*[a-f0-9]+: 0f 02 d2 lar edx,edx
[ ]*[a-f0-9]+: 66 0f 02 12 lar dx,WORD PTR \[rdx\]
[ ]*[a-f0-9]+: 0f 02 12 lar edx,WORD PTR \[rdx\]
-[ ]*[a-f0-9]+: 48 0f 02 12 lar rdx,WORD PTR \[rdx\]
+[ ]*[a-f0-9]+: 0f 02 12 lar edx,WORD PTR \[rdx\]
[ ]*[a-f0-9]+: 66 0f 03 d2 lsl dx,dx
[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,edx
-[ ]*[a-f0-9]+: 48 0f 03 d2 lsl rdx,rdx
[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,edx
-[ ]*[a-f0-9]+: 48 0f 03 d2 lsl rdx,rdx
+[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,edx
+[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,edx
[ ]*[a-f0-9]+: 66 0f 03 12 lsl dx,WORD PTR \[rdx\]
[ ]*[a-f0-9]+: 0f 03 12 lsl edx,WORD PTR \[rdx\]
-[ ]*[a-f0-9]+: 48 0f 03 12 lsl rdx,WORD PTR \[rdx\]
+[ ]*[a-f0-9]+: 0f 03 12 lsl edx,WORD PTR \[rdx\]
[ ]*[a-f0-9]+: 66 0f 02 d2 lar dx,dx
[ ]*[a-f0-9]+: 0f 02 d2 lar edx,edx
-[ ]*[a-f0-9]+: 48 0f 02 d2 lar rdx,rdx
[ ]*[a-f0-9]+: 0f 02 d2 lar edx,edx
-[ ]*[a-f0-9]+: 48 0f 02 d2 lar rdx,rdx
+[ ]*[a-f0-9]+: 0f 02 d2 lar edx,edx
+[ ]*[a-f0-9]+: 0f 02 d2 lar edx,edx
[ ]*[a-f0-9]+: 66 0f 02 12 lar dx,WORD PTR \[rdx\]
[ ]*[a-f0-9]+: 0f 02 12 lar edx,WORD PTR \[rdx\]
-[ ]*[a-f0-9]+: 48 0f 02 12 lar rdx,WORD PTR \[rdx\]
+[ ]*[a-f0-9]+: 0f 02 12 lar edx,WORD PTR \[rdx\]
[ ]*[a-f0-9]+: 66 0f 03 d2 lsl dx,dx
[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,edx
-[ ]*[a-f0-9]+: 48 0f 03 d2 lsl rdx,rdx
[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,edx
-[ ]*[a-f0-9]+: 48 0f 03 d2 lsl rdx,rdx
+[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,edx
+[ ]*[a-f0-9]+: 0f 03 d2 lsl edx,edx
[ ]*[a-f0-9]+: 66 0f 03 12 lsl dx,WORD PTR \[rdx\]
[ ]*[a-f0-9]+: 0f 03 12 lsl edx,WORD PTR \[rdx\]
-[ ]*[a-f0-9]+: 48 0f 03 12 lsl rdx,WORD PTR \[rdx\]
+[ ]*[a-f0-9]+: 0f 03 12 lsl edx,WORD PTR \[rdx\]
#pass
diff --git a/gas/testsuite/gas/i386/x86_64.d b/gas/testsuite/gas/i386/x86_64.d
index 3bd2c269e36..8897bb30d03 100644
--- a/gas/testsuite/gas/i386/x86_64.d
+++ b/gas/testsuite/gas/i386/x86_64.d
@@ -260,34 +260,34 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 48 89 0c 25 00 00 00 00 mov %rcx,0x0
[ ]*[a-f0-9]+: 66 0f 02 d2 lar %dx,%dx
[ ]*[a-f0-9]+: 0f 02 d2 lar %edx,%edx
-[ ]*[a-f0-9]+: 48 0f 02 d2 lar %rdx,%rdx
[ ]*[a-f0-9]+: 0f 02 d2 lar %edx,%edx
-[ ]*[a-f0-9]+: 48 0f 02 d2 lar %rdx,%rdx
+[ ]*[a-f0-9]+: 0f 02 d2 lar %edx,%edx
+[ ]*[a-f0-9]+: 0f 02 d2 lar %edx,%edx
[ ]*[a-f0-9]+: 66 0f 02 12 lar \(%rdx\),%dx
[ ]*[a-f0-9]+: 0f 02 12 lar \(%rdx\),%edx
-[ ]*[a-f0-9]+: 48 0f 02 12 lar \(%rdx\),%rdx
+[ ]*[a-f0-9]+: 0f 02 12 lar \(%rdx\),%edx
[ ]*[a-f0-9]+: 66 0f 03 d2 lsl %dx,%dx
[ ]*[a-f0-9]+: 0f 03 d2 lsl %edx,%edx
-[ ]*[a-f0-9]+: 48 0f 03 d2 lsl %rdx,%rdx
[ ]*[a-f0-9]+: 0f 03 d2 lsl %edx,%edx
-[ ]*[a-f0-9]+: 48 0f 03 d2 lsl %rdx,%rdx
+[ ]*[a-f0-9]+: 0f 03 d2 lsl %edx,%edx
+[ ]*[a-f0-9]+: 0f 03 d2 lsl %edx,%edx
[ ]*[a-f0-9]+: 66 0f 03 12 lsl \(%rdx\),%dx
[ ]*[a-f0-9]+: 0f 03 12 lsl \(%rdx\),%edx
-[ ]*[a-f0-9]+: 48 0f 03 12 lsl \(%rdx\),%rdx
+[ ]*[a-f0-9]+: 0f 03 12 lsl \(%rdx\),%edx
[ ]*[a-f0-9]+: 66 0f 02 d2 lar %dx,%dx
[ ]*[a-f0-9]+: 0f 02 d2 lar %edx,%edx
-[ ]*[a-f0-9]+: 48 0f 02 d2 lar %rdx,%rdx
[ ]*[a-f0-9]+: 0f 02 d2 lar %edx,%edx
-[ ]*[a-f0-9]+: 48 0f 02 d2 lar %rdx,%rdx
+[ ]*[a-f0-9]+: 0f 02 d2 lar %edx,%edx
+[ ]*[a-f0-9]+: 0f 02 d2 lar %edx,%edx
[ ]*[a-f0-9]+: 66 0f 02 12 lar \(%rdx\),%dx
[ ]*[a-f0-9]+: 0f 02 12 lar \(%rdx\),%edx
-[ ]*[a-f0-9]+: 48 0f 02 12 lar \(%rdx\),%rdx
+[ ]*[a-f0-9]+: 0f 02 12 lar \(%rdx\),%edx
[ ]*[a-f0-9]+: 66 0f 03 d2 lsl %dx,%dx
[ ]*[a-f0-9]+: 0f 03 d2 lsl %edx,%edx
-[ ]*[a-f0-9]+: 48 0f 03 d2 lsl %rdx,%rdx
[ ]*[a-f0-9]+: 0f 03 d2 lsl %edx,%edx
-[ ]*[a-f0-9]+: 48 0f 03 d2 lsl %rdx,%rdx
+[ ]*[a-f0-9]+: 0f 03 d2 lsl %edx,%edx
+[ ]*[a-f0-9]+: 0f 03 d2 lsl %edx,%edx
[ ]*[a-f0-9]+: 66 0f 03 12 lsl \(%rdx\),%dx
[ ]*[a-f0-9]+: 0f 03 12 lsl \(%rdx\),%edx
-[ ]*[a-f0-9]+: 48 0f 03 12 lsl \(%rdx\),%rdx
+[ ]*[a-f0-9]+: 0f 03 12 lsl \(%rdx\),%edx
#pass
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 5bd759507ad..464e54a80e2 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -567,16 +567,16 @@ nop, 0x90, 0, NoSuf|RepPrefixOk, {}
// Protection control.
arpl, 0x63, i286|No64, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16, Reg16|Word|Unspecified|BaseIndex }
-lar, 0xf02, i286, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 }
-lar, 0xf02, i286, Modrm|No_bSuf|No_sSuf, { Reg16|Word|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+lar, 0xf02, i286, Modrm|CheckOperandSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 }
+lar, 0xf02, i286, Modrm|No_bSuf|No_sSuf|NoRex64, { Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
lgdt, 0xf01/2, i286|No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex }
lgdt, 0xf01/2, x64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
lidt, 0xf01/3, i286|No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex }
lidt, 0xf01/3, x64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
lldt, 0xf00/2, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
lmsw, 0xf01/6, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
-lsl, 0xf03, i286, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 }
-lsl, 0xf03, i286, Modrm|No_bSuf|No_sSuf, { Reg16|Word|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+lsl, 0xf03, i286, Modrm|CheckOperandSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 }
+lsl, 0xf03, i286, Modrm|No_bSuf|No_sSuf|NoRex64, { Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
ltr, 0xf00/3, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
sgdt, 0xf01/0, i286|No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex }
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 262a05d8bd0..b2d5f2b8ff7 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -4564,7 +4564,7 @@ static const insn_template i386_optab[] =
0, 0, 0, 0, 1, 0 } } } },
{ MN_lar, 0x02, 2, SPACE_0F, None,
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -4578,7 +4578,7 @@ static const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0 } } } },
{ MN_lar, 0x02, 2, SPACE_0F, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -4664,7 +4664,7 @@ static const insn_template i386_optab[] =
0, 0, 0, 0, 1, 0 } } } },
{ MN_lsl, 0x03, 2, SPACE_0F, None,
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -4678,7 +4678,7 @@ static const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0 } } } },
{ MN_lsl, 0x03, 2, SPACE_0F, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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