From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1130) id 38D0F3858428; Thu, 30 Mar 2023 10:10:59 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 38D0F3858428 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Richard Sandiford To: bfd-cvs@sourceware.org Subject: [binutils-gdb] aarch64: Make SME instructions use F_STRICT X-Act-Checkin: binutils-gdb X-Git-Author: Richard Sandiford X-Git-Refname: refs/heads/master X-Git-Oldrev: eee2ecccdaa37d6c5d283d6346f70897ba27166b X-Git-Newrev: a5791d5814226054215b7aab9f87dec6b8e41664 Message-Id: <20230330101059.38D0F3858428@sourceware.org> Date: Thu, 30 Mar 2023 10:10:59 +0000 (GMT) X-BeenThere: binutils-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 30 Mar 2023 10:10:59 -0000 https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3Da5791d581422= 6054215b7aab9f87dec6b8e41664 commit a5791d5814226054215b7aab9f87dec6b8e41664 Author: Richard Sandiford Date: Thu Mar 30 11:09:02 2023 +0100 aarch64: Make SME instructions use F_STRICT =20 This patch makes all SME instructions use F_STRICT, so that qualifiers have to be provided explicitly rather than being inferred from other operands. The main change is to move the qualifier setting from the operand-level decoders to the opcode level. =20 This is one step towards consolidating the ZA parsing code and extending it to handle SME2. Diff: --- include/opcode/aarch64.h | 2 ++ opcodes/aarch64-asm.c | 8 ++++- opcodes/aarch64-dis.c | 93 ++++++++++++++++++++++++--------------------= ---- opcodes/aarch64-tbl.h | 18 +++++----- 4 files changed, 64 insertions(+), 57 deletions(-) diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index d0a0b629d99..691247aa934 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -659,7 +659,9 @@ enum aarch64_insn_class pcreladdr, ic_system, sme_misc, + sme_mov, sme_ldr, + sme_psel, sme_str, sme_start, sme_stop, diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index e050197e8be..bfabcb9e3a2 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -1852,6 +1852,11 @@ aarch64_encode_variant_using_iclass (struct aarch64_= inst *inst) int variant =3D 0; switch (inst->opcode->iclass) { + case sme_mov: + case sme_psel: + /* The variant is encoded as part of the immediate. */ + break; + case sve_cpy: insert_fields (&inst->value, aarch64_get_variant (inst), 0, 2, FLD_SVE_M_14, FLD_size); @@ -1872,8 +1877,9 @@ aarch64_encode_variant_using_iclass (struct aarch64_i= nst *inst) encoding. */ break; =20 + case sme_misc: case sve_misc: - /* sve_misc instructions have only a single variant. */ + /* These instructions have only a single variant. */ break; =20 case sve_movprfx: diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index 02ce8345979..01881ea377d 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -1785,44 +1785,35 @@ aarch64_ext_sme_za_hv_tiles (const aarch64_operand = *self, =20 /* Deduce qualifier encoded in size and Q fields. */ if (fld_size =3D=3D 0) - info->qualifier =3D AARCH64_OPND_QLF_S_B; - else if (fld_size =3D=3D 1) - info->qualifier =3D AARCH64_OPND_QLF_S_H; - else if (fld_size =3D=3D 2) - info->qualifier =3D AARCH64_OPND_QLF_S_S; - else if (fld_size =3D=3D 3 && fld_q =3D=3D 0) - info->qualifier =3D AARCH64_OPND_QLF_S_D; - else if (fld_size =3D=3D 3 && fld_q =3D=3D 1) - info->qualifier =3D AARCH64_OPND_QLF_S_Q; - - info->za_tile_vector.index.regno =3D fld_rv + 12; - info->za_tile_vector.v =3D fld_v; - - switch (info->qualifier) { - case AARCH64_OPND_QLF_S_B: info->za_tile_vector.regno =3D 0; info->za_tile_vector.index.imm =3D fld_zan_imm; - break; - case AARCH64_OPND_QLF_S_H: + } + else if (fld_size =3D=3D 1) + { info->za_tile_vector.regno =3D fld_zan_imm >> 3; info->za_tile_vector.index.imm =3D fld_zan_imm & 0x07; - break; - case AARCH64_OPND_QLF_S_S: + } + else if (fld_size =3D=3D 2) + { info->za_tile_vector.regno =3D fld_zan_imm >> 2; info->za_tile_vector.index.imm =3D fld_zan_imm & 0x03; - break; - case AARCH64_OPND_QLF_S_D: + } + else if (fld_size =3D=3D 3 && fld_q =3D=3D 0) + { info->za_tile_vector.regno =3D fld_zan_imm >> 1; info->za_tile_vector.index.imm =3D fld_zan_imm & 0x01; - break; - case AARCH64_OPND_QLF_S_Q: + } + else if (fld_size =3D=3D 3 && fld_q =3D=3D 1) + { info->za_tile_vector.regno =3D fld_zan_imm; info->za_tile_vector.index.imm =3D 0; - break; - default: - return false; } + else + return false; + + info->za_tile_vector.index.regno =3D fld_rv + 12; + info->za_tile_vector.v =3D fld_v; =20 return true; } @@ -1914,26 +1905,14 @@ aarch64_ext_sme_pred_reg_with_index (const aarch64_= operand *self, info->za_tile_vector.regno =3D fld_pn; info->za_tile_vector.index.regno =3D fld_rm + 12; =20 - if (fld_tszh =3D=3D 0x1 && fld_tszl =3D=3D 0x0) - { - info->qualifier =3D AARCH64_OPND_QLF_S_D; - imm =3D fld_i1; - } - else if (fld_tszl =3D=3D 0x4) - { - info->qualifier =3D AARCH64_OPND_QLF_S_S; - imm =3D (fld_i1 << 1) | fld_tszh; - } - else if ((fld_tszl & 0x3) =3D=3D 0x2) - { - info->qualifier =3D AARCH64_OPND_QLF_S_H; - imm =3D (fld_i1 << 2) | (fld_tszh << 1) | (fld_tszl >> 2); - } - else if (fld_tszl & 0x1) - { - info->qualifier =3D AARCH64_OPND_QLF_S_B; - imm =3D (fld_i1 << 3) | (fld_tszh << 2) | (fld_tszl >> 1); - } + if (fld_tszl & 0x1) + imm =3D (fld_i1 << 3) | (fld_tszh << 2) | (fld_tszl >> 1); + else if (fld_tszl & 0x2) + imm =3D (fld_i1 << 2) | (fld_tszh << 1) | (fld_tszl >> 2); + else if (fld_tszl & 0x4) + imm =3D (fld_i1 << 1) | fld_tszh; + else if (fld_tszh) + imm =3D fld_i1; else return false; =20 @@ -2975,6 +2954,25 @@ aarch64_decode_variant_using_iclass (aarch64_inst *i= nst) variant =3D 0; switch (inst->opcode->iclass) { + case sme_mov: + variant =3D extract_fields (inst->value, 0, 2, FLD_SME_Q, FLD_SME_si= ze_10); + if (variant >=3D 4 && variant < 7) + return false; + if (variant =3D=3D 7) + variant =3D 4; + break; + + case sme_psel: + i =3D extract_fields (inst->value, 0, 2, FLD_SME_tszh, FLD_SME_tszl); + if (i =3D=3D 0) + return false; + while ((i & 1) =3D=3D 0) + { + i >>=3D 1; + variant +=3D 1; + } + break; + case sve_cpy: variant =3D extract_fields (inst->value, 0, 2, FLD_size, FLD_SVE_M_1= 4); break; @@ -3002,8 +3000,9 @@ aarch64_decode_variant_using_iclass (aarch64_inst *in= st) variant =3D 3; break; =20 + case sme_misc: case sve_misc: - /* sve_misc instructions have only a single variant. */ + /* These instructions have only a single variant. */ break; =20 case sve_movprfx: diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 96e6c136282..6c2862eacf3 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2650,16 +2650,16 @@ static const aarch64_feature_set aarch64_feature_cs= sc =3D FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } #define SME_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SME, OPS, QUALS, \ - FLAGS, 0, TIED, NULL } + F_STRICT | FLAGS, 0, TIED, NULL } #define SME_F64F64_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SME_F64F64, OPS, QUALS, \ - FLAGS, 0, TIED, NULL } + F_STRICT | FLAGS, 0, TIED, NULL } #define SME_I16I64_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SME_I16I64, OPS, QUALS, \ - FLAGS, 0, TIED, NULL } + F_STRICT | FLAGS, 0, TIED, NULL } #define SME_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TI= ED) \ { NAME, OPCODE, MASK, CLASS, OP, SME, OPS, QUALS, \ - FLAGS, CONSTRAINTS, TIED, NULL } + F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL } #define SVE2BITPERM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2_BITPERM, OPS, QUALS, \ FLAGS | F_STRICT, 0, TIED, NULL } @@ -5238,10 +5238,10 @@ const struct aarch64_opcode aarch64_opcode_table[] = =3D SME_INSN ("usmops", 0xa1800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2= b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0), SME_I16I64_INSN ("usmops", 0xa1c00010, 0xffe00018, sme_misc, 0, OP5 (SME= _ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, = 0), =20 - SME_INSN ("mov", 0xc0020000, 0xff3e0200, sme_misc, 0, OP3 (SVE_Zd, SVE_P= g3, SME_ZA_HV_idx_src), OP_SME_BHSDQ_PM_BHSDQ, 0, 0), - SME_INSN ("mov", 0xc0000000, 0xff3e0010, sme_misc, 0, OP3 (SME_ZA_HV_idx= _dest, SVE_Pg3, SVE_Zn), OP_SME_BHSDQ_PM_BHSDQ, 0, 0), - SME_INSN ("mova", 0xc0020000, 0xff3e0200, sme_misc, 0, OP3 (SVE_Zd, SVE_= Pg3, SME_ZA_HV_idx_src), OP_SME_BHSDQ_PM_BHSDQ, 0, 0), - SME_INSN ("mova", 0xc0000000, 0xff3e0010, sme_misc, 0, OP3 (SME_ZA_HV_id= x_dest, SVE_Pg3, SVE_Zn), OP_SME_BHSDQ_PM_BHSDQ, 0, 0), + SME_INSN ("mov", 0xc0020000, 0xff3e0200, sme_mov, 0, OP3 (SVE_Zd, SVE_Pg= 3, SME_ZA_HV_idx_src), OP_SME_BHSDQ_PM_BHSDQ, 0, 0), + SME_INSN ("mov", 0xc0000000, 0xff3e0010, sme_mov, 0, OP3 (SME_ZA_HV_idx_= dest, SVE_Pg3, SVE_Zn), OP_SME_BHSDQ_PM_BHSDQ, 0, 0), + SME_INSN ("mova", 0xc0020000, 0xff3e0200, sme_mov, 0, OP3 (SVE_Zd, SVE_P= g3, SME_ZA_HV_idx_src), OP_SME_BHSDQ_PM_BHSDQ, 0, 0), + SME_INSN ("mova", 0xc0000000, 0xff3e0010, sme_mov, 0, OP3 (SME_ZA_HV_idx= _dest, SVE_Pg3, SVE_Zn), OP_SME_BHSDQ_PM_BHSDQ, 0, 0), =20 SME_INSN ("zero", 0xc0080000, 0xffffff00, sme_misc, 0, OP1 (SME_list_of_= 64bit_tiles), {}, 0, 0), =20 @@ -5275,7 +5275,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =3D SME_INSNC ("revd", 0x52e8000, 0xffffe000, sme_misc, 0, OP3 (SVE_Zd, SVE_= Pg3, SVE_Zn), OP_SVE_QMQ, 0, C_SCAN_MOVPRFX, 0), SME_INSNC ("sclamp", 0x4400c000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_= Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0), SME_INSNC ("uclamp", 0x4400c400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_= Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0), - SME_INSN ("psel", 0x25204000, 0xff20c210, sme_misc, 0, OP3 (SVE_Pd, SVE_= Pg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0), + SME_INSN ("psel", 0x25204000, 0xff20c210, sme_psel, 0, OP3 (SVE_Pd, SVE_= Pg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0), =20 /* SIMD Dot Product (optional in v8.2-A). */ DOT_INSN ("udot", 0x2e009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), = QL_V3DOT, F_SIZEQ),