From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1130) id 90DCF3858C50; Thu, 30 Mar 2023 10:11:24 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 90DCF3858C50 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Richard Sandiford To: bfd-cvs@sourceware.org Subject: [binutils-gdb] aarch64: Rework parse_typed_reg interface X-Act-Checkin: binutils-gdb X-Git-Author: Richard Sandiford X-Git-Refname: refs/heads/master X-Git-Oldrev: 363c5c8b973d72b4c2cba2c79ed0dcd98bc97934 X-Git-Newrev: 074c89d29b4066a913991dd73ac35ce8742c1d9b Message-Id: <20230330101124.90DCF3858C50@sourceware.org> Date: Thu, 30 Mar 2023 10:11:24 +0000 (GMT) X-BeenThere: binutils-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 30 Mar 2023 10:11:24 -0000 https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D074c89d29b40= 66a913991dd73ac35ce8742c1d9b commit 074c89d29b4066a913991dd73ac35ce8742c1d9b Author: Richard Sandiford Date: Thu Mar 30 11:09:03 2023 +0100 aarch64: Rework parse_typed_reg interface =20 parse_typed_reg returned a register number and passed the register type back using a pointer parameter. It seems simpler to return the register entry instead, since that has both pieces of information in one place. =20 The patch also replaces the boolean in_reg_list parameter with a mask of flags. This hopefully makes calls easier to read (more self-documenting than "true" or "false"), but more importantly, it allows a later patch to add a second flag. Diff: --- gas/config/tc-aarch64.c | 124 +++++++++++++++++++++-----------------------= ---- 1 file changed, 53 insertions(+), 71 deletions(-) diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 7de0f5c83f6..8c3d627a08b 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -1006,19 +1006,19 @@ parse_predication_for_operand (struct vector_type_e= l *parsed_type, char **str) =20 /* Parse a register of the type TYPE. =20 - Return PARSE_FAIL if the string pointed by *CCP is not a valid register + Return null if the string pointed to by *CCP is not a valid register name or the parsed register is not of TYPE. =20 - Otherwise return the register number, and optionally fill in the actual - type of the register in *RTYPE when multiple alternatives were given, a= nd - return the register shape and element index information in *TYPEINFO. + Otherwise return the register, and optionally return the register + shape and element index information in *TYPEINFO. =20 - IN_REG_LIST should be set with TRUE if the caller is parsing a register - list. */ + FLAGS includes PTR_IN_REGLIST if the caller is parsing a register list.= */ =20 -static int -parse_typed_reg (char **ccp, aarch64_reg_type type, aarch64_reg_type *rtyp= e, - struct vector_type_el *typeinfo, bool in_reg_list) +#define PTR_IN_REGLIST (1U << 0) + +static const reg_entry * +parse_typed_reg (char **ccp, aarch64_reg_type type, + struct vector_type_el *typeinfo, unsigned int flags) { char *str =3D *ccp; const reg_entry *reg =3D parse_reg (&str); @@ -1036,14 +1036,14 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,= aarch64_reg_type *rtype, if (typeinfo) *typeinfo =3D atype; set_default_error (); - return PARSE_FAIL; + return NULL; } =20 if (! aarch64_check_reg_type (reg, type)) { DEBUG_TRACE ("reg type check failed"); set_default_error (); - return PARSE_FAIL; + return NULL; } type =3D reg->type; =20 @@ -1053,12 +1053,12 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,= aarch64_reg_type *rtype, if (*str =3D=3D '.') { if (!parse_vector_type_for_operand (type, &parsetype, &str)) - return PARSE_FAIL; + return NULL; } else { if (!parse_predication_for_operand (&parsetype, &str)) - return PARSE_FAIL; + return NULL; } =20 /* Register if of the form Vn.[bhsdq]. */ @@ -1092,13 +1092,13 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,= aarch64_reg_type *rtype, if (!is_typed_vecreg) { first_error (_("this type of register can't be indexed")); - return PARSE_FAIL; + return NULL; } =20 - if (in_reg_list) + if (flags & PTR_IN_REGLIST) { first_error (_("index not allowed inside register list")); - return PARSE_FAIL; + return NULL; } =20 atype.defined |=3D NTA_HASINDEX; @@ -1108,19 +1108,19 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,= aarch64_reg_type *rtype, if (exp.X_op !=3D O_constant) { first_error (_("constant expression required")); - return PARSE_FAIL; + return NULL; } =20 if (! skip_past_char (&str, ']')) - return PARSE_FAIL; + return NULL; =20 atype.index =3D exp.X_add_number; } - else if (!in_reg_list && (atype.defined & NTA_HASINDEX) !=3D 0) + else if (!(flags & PTR_IN_REGLIST) && (atype.defined & NTA_HASINDEX) != =3D 0) { /* Indexed vector register expected. */ first_error (_("indexed vector register expected")); - return PARSE_FAIL; + return NULL; } =20 /* A vector reg Vn should be typed or indexed. */ @@ -1132,44 +1132,25 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,= aarch64_reg_type *rtype, if (typeinfo) *typeinfo =3D atype; =20 - if (rtype) - *rtype =3D type; - *ccp =3D str; =20 - return reg->number; + return reg; } =20 /* Parse register. =20 - Return the register number on success; return PARSE_FAIL otherwise. - - If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of - the register (e.g. NEON double or quad reg when either has been request= ed). + Return the register on success; return null otherwise. =20 If this is a NEON vector register with additional type information, fill in the struct pointed to by VECTYPE (if non-NULL). =20 - This parser does not handle register list. */ + This parser does not handle register lists. */ =20 -static int +static const reg_entry * aarch64_reg_parse (char **ccp, aarch64_reg_type type, - aarch64_reg_type *rtype, struct vector_type_el *vectype) + struct vector_type_el *vectype) { - struct vector_type_el atype; - char *str =3D *ccp; - int reg =3D parse_typed_reg (&str, type, rtype, &atype, - /*in_reg_list=3D */ false); - - if (reg =3D=3D PARSE_FAIL) - return PARSE_FAIL; - - if (vectype) - *vectype =3D atype; - - *ccp =3D str; - - return reg; + return parse_typed_reg (ccp, type, vectype, 0); } =20 static inline bool @@ -1239,14 +1220,15 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type= type, str++; /* skip over '-' */ val_range =3D val; } - val =3D parse_typed_reg (&str, type, NULL, &typeinfo, - /*in_reg_list=3D */ true); - if (val =3D=3D PARSE_FAIL) + const reg_entry *reg =3D parse_typed_reg (&str, type, &typeinfo, + PTR_IN_REGLIST); + if (!reg) { set_first_syntax_error (_("invalid vector register in list")); error =3D true; continue; } + val =3D reg->number; /* reject [bhsd]n */ if (type =3D=3D REG_TYPE_VN && typeinfo.defined =3D=3D 0) { @@ -2271,18 +2253,18 @@ const pseudo_typeS md_pseudo_table[] =3D { static bool reg_name_p (char *str, aarch64_reg_type reg_type) { - int reg; + const reg_entry *reg; =20 /* Prevent the diagnostics state from being spoiled. */ if (error_p ()) return false; =20 - reg =3D aarch64_reg_parse (&str, reg_type, NULL, NULL); + reg =3D aarch64_reg_parse (&str, reg_type, NULL); =20 /* Clear the parsing error that may be set by the reg parser. */ clear_error (); =20 - if (reg =3D=3D PARSE_FAIL) + if (!reg) return false; =20 skip_whitespace (str); @@ -4957,8 +4939,8 @@ parse_sys_ins_reg (char **str, htab_t sys_ins_regs) } while (0) =20 #define po_reg_or_fail(regtype) do { \ - val =3D aarch64_reg_parse (&str, regtype, &rtype, NULL); \ - if (val =3D=3D PARSE_FAIL) \ + reg =3D aarch64_reg_parse (&str, regtype, NULL); \ + if (!reg) \ { \ set_default_error (); \ goto failure; \ @@ -6344,7 +6326,6 @@ parse_operands (char *str, const aarch64_opcode *opco= de) int64_t val; const reg_entry *reg; int comma_skipped_p =3D 0; - aarch64_reg_type rtype; struct vector_type_el vectype; aarch64_opnd_qualifier_t qualifier, base_qualifier, offset_qualifier; aarch64_opnd_info *info =3D &inst.base.operands[i]; @@ -6443,16 +6424,17 @@ parse_operands (char *str, const aarch64_opcode *op= code) case AARCH64_OPND_SVE_Vd: case AARCH64_OPND_SVE_Vm: case AARCH64_OPND_SVE_Vn: - val =3D aarch64_reg_parse (&str, REG_TYPE_BHSDQ, &rtype, NULL); - if (val =3D=3D PARSE_FAIL) + reg =3D aarch64_reg_parse (&str, REG_TYPE_BHSDQ, NULL); + if (!reg) { first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ))); goto failure; } - gas_assert (rtype >=3D REG_TYPE_FP_B && rtype <=3D REG_TYPE_FP_Q); + gas_assert (reg->type >=3D REG_TYPE_FP_B + && reg->type <=3D REG_TYPE_FP_Q); =20 - info->reg.regno =3D val; - info->qualifier =3D AARCH64_OPND_QLF_S_B + (rtype - REG_TYPE_FP_B); + info->reg.regno =3D reg->number; + info->qualifier =3D AARCH64_OPND_QLF_S_B + (reg->type - REG_TYPE_FP_B); break; =20 case AARCH64_OPND_SVE_Pd: @@ -6483,8 +6465,8 @@ parse_operands (char *str, const aarch64_opcode *opco= de) case AARCH64_OPND_Vm: reg_type =3D REG_TYPE_VN; vector_reg: - val =3D aarch64_reg_parse (&str, reg_type, NULL, &vectype); - if (val =3D=3D PARSE_FAIL) + reg =3D aarch64_reg_parse (&str, reg_type, &vectype); + if (!reg) { first_error (_(get_reg_expected_msg (reg_type))); goto failure; @@ -6492,7 +6474,7 @@ parse_operands (char *str, const aarch64_opcode *opco= de) if (vectype.defined & NTA_HASINDEX) goto failure; =20 - info->reg.regno =3D val; + info->reg.regno =3D reg->number; if ((reg_type =3D=3D REG_TYPE_PN || reg_type =3D=3D REG_TYPE_ZN) && vectype.type =3D=3D NT_invtype) /* Unqualified Pn and Zn registers are allowed in certain @@ -6509,8 +6491,8 @@ parse_operands (char *str, const aarch64_opcode *opco= de) =20 case AARCH64_OPND_VdD1: case AARCH64_OPND_VnD1: - val =3D aarch64_reg_parse (&str, REG_TYPE_VN, NULL, &vectype); - if (val =3D=3D PARSE_FAIL) + reg =3D aarch64_reg_parse (&str, REG_TYPE_VN, &vectype); + if (!reg) { set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN))); goto failure; @@ -6521,7 +6503,7 @@ parse_operands (char *str, const aarch64_opcode *opco= de) (_("the top half of a 128-bit FP/SIMD register is expected")); goto failure; } - info->reg.regno =3D val; + info->reg.regno =3D reg->number; /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register here; it is correct for the purpose of encoding/decoding since only the register number is explicitly encoded in the related @@ -6545,8 +6527,8 @@ parse_operands (char *str, const aarch64_opcode *opco= de) case AARCH64_OPND_SM3_IMM2: reg_type =3D REG_TYPE_VN; vector_reg_index: - val =3D aarch64_reg_parse (&str, reg_type, NULL, &vectype); - if (val =3D=3D PARSE_FAIL) + reg =3D aarch64_reg_parse (&str, reg_type, &vectype); + if (!reg) { first_error (_(get_reg_expected_msg (reg_type))); goto failure; @@ -6554,7 +6536,7 @@ parse_operands (char *str, const aarch64_opcode *opco= de) if (vectype.type =3D=3D NT_invtype || !(vectype.defined & NTA_HASINDEX)) goto failure; =20 - info->reglane.regno =3D val; + info->reglane.regno =3D reg->number; info->reglane.index =3D vectype.index; info->qualifier =3D vectype_to_qualifier (&vectype); if (info->qualifier =3D=3D AARCH64_OPND_QLF_NIL) @@ -6576,13 +6558,13 @@ parse_operands (char *str, const aarch64_opcode *op= code) && get_opcode_dependent_value (opcode) =3D=3D 1 && *str !=3D '{') { - val =3D aarch64_reg_parse (&str, reg_type, NULL, &vectype); - if (val =3D=3D PARSE_FAIL) + reg =3D aarch64_reg_parse (&str, reg_type, &vectype); + if (!reg) { first_error (_(get_reg_expected_msg (reg_type))); goto failure; } - info->reglist.first_regno =3D val; + info->reglist.first_regno =3D reg->number; info->reglist.num_regs =3D 1; } else