From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1130) id 939C3385840F; Thu, 30 Mar 2023 10:12:30 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 939C3385840F Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Richard Sandiford To: bfd-cvs@sourceware.org Subject: [binutils-gdb] aarch64: Tweak parsing of integer & FP registers X-Act-Checkin: binutils-gdb X-Git-Author: Richard Sandiford X-Git-Refname: refs/heads/master X-Git-Oldrev: 72c1dab0ea9ba6319dddd4af934b71b98f3fe81c X-Git-Newrev: 30ba1d7e2fe36f6bcddb2aa0693f198c96c735b7 Message-Id: <20230330101230.939C3385840F@sourceware.org> Date: Thu, 30 Mar 2023 10:12:30 +0000 (GMT) X-BeenThere: binutils-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 30 Mar 2023 10:12:30 -0000 https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D30ba1d7e2fe3= 6f6bcddb2aa0693f198c96c735b7 commit 30ba1d7e2fe36f6bcddb2aa0693f198c96c735b7 Author: Richard Sandiford Date: Thu Mar 30 11:09:06 2023 +0100 aarch64: Tweak parsing of integer & FP registers =20 Integer registers were parsed indirectly through aarch64_reg_parse_32_64 (and thus aarch64_addr_reg_parse) rather than directly through parse_reg. This was because we need the qualifier associated with the register, and the logic to calculate that was buried in aarch64_addr_reg_parse. =20 The code that parses FP registers had the same need, but it open-coded the calculation of the qualifier. =20 This patch tries to handle both cases in the same way. It is needed by a later patch that tries to improve the register-related diagnostics. Diff: --- gas/config/tc-aarch64.c | 71 +++++++++++++++++++++++++++++----------------= ---- 1 file changed, 42 insertions(+), 29 deletions(-) diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index ee88c8fe7c9..e8dfcb81bdf 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -801,6 +801,38 @@ parse_reg (char **ccp) return reg; } =20 +/* Return the operand qualifier associated with all uses of REG, or + AARCH64_OPND_QLF_NIL if none. AARCH64_OPND_QLF_NIL means either + that qualifiers don't apply to REG or that qualifiers are added + using suffixes. */ + +static aarch64_opnd_qualifier_t +inherent_reg_qualifier (const reg_entry *reg) +{ + switch (reg->type) + { + case REG_TYPE_R_32: + case REG_TYPE_SP_32: + case REG_TYPE_Z_32: + return AARCH64_OPND_QLF_W; + + case REG_TYPE_R_64: + case REG_TYPE_SP_64: + case REG_TYPE_Z_64: + return AARCH64_OPND_QLF_X; + + case REG_TYPE_FP_B: + case REG_TYPE_FP_H: + case REG_TYPE_FP_S: + case REG_TYPE_FP_D: + case REG_TYPE_FP_Q: + return AARCH64_OPND_QLF_S_B + (reg->type - REG_TYPE_FP_B); + + default: + return AARCH64_OPND_QLF_NIL; + } +} + /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise return FALSE. */ static bool @@ -828,18 +860,6 @@ aarch64_addr_reg_parse (char **ccp, aarch64_reg_type r= eg_type, =20 switch (reg->type) { - case REG_TYPE_R_32: - case REG_TYPE_SP_32: - case REG_TYPE_Z_32: - *qualifier =3D AARCH64_OPND_QLF_W; - break; - - case REG_TYPE_R_64: - case REG_TYPE_SP_64: - case REG_TYPE_Z_64: - *qualifier =3D AARCH64_OPND_QLF_X; - break; - case REG_TYPE_ZN: if ((reg_type_masks[reg_type] & (1 << REG_TYPE_ZN)) =3D=3D 0 || str[0] !=3D '.') @@ -859,7 +879,10 @@ aarch64_addr_reg_parse (char **ccp, aarch64_reg_type r= eg_type, break; =20 default: - return NULL; + if (!aarch64_check_reg_type (reg, REG_TYPE_R_Z_SP)) + return NULL; + *qualifier =3D inherent_reg_qualifier (reg); + break; } =20 *ccp =3D str; @@ -4744,15 +4767,15 @@ parse_sys_ins_reg (char **str, htab_t sys_ins_regs) } \ } while (0) =20 -#define po_int_reg_or_fail(reg_type) do { \ - reg =3D aarch64_reg_parse_32_64 (&str, &qualifier); \ +#define po_int_fp_reg_or_fail(reg_type) do { \ + reg =3D parse_reg (&str); \ if (!reg || !aarch64_check_reg_type (reg, reg_type)) \ { \ set_default_error (); \ goto failure; \ } \ info->reg.regno =3D reg->number; \ - info->qualifier =3D qualifier; \ + info->qualifier =3D inherent_reg_qualifier (reg); \ } while (0) =20 #define po_imm_nc_or_fail() do { \ @@ -6163,7 +6186,7 @@ parse_operands (char *str, const aarch64_opcode *opco= de) case AARCH64_OPND_Rt_SYS: case AARCH64_OPND_PAIRREG: case AARCH64_OPND_SVE_Rm: - po_int_reg_or_fail (REG_TYPE_R_Z); + po_int_fp_reg_or_fail (REG_TYPE_R_Z); =20 /* In LS64 load/store instructions Rt register number must be even and <=3D22. */ @@ -6186,7 +6209,7 @@ parse_operands (char *str, const aarch64_opcode *opco= de) case AARCH64_OPND_Rt_SP: case AARCH64_OPND_SVE_Rn_SP: case AARCH64_OPND_Rm_SP: - po_int_reg_or_fail (REG_TYPE_R_SP); + po_int_fp_reg_or_fail (REG_TYPE_R_SP); break; =20 case AARCH64_OPND_Rm_EXT: @@ -6221,17 +6244,7 @@ parse_operands (char *str, const aarch64_opcode *opc= ode) case AARCH64_OPND_SVE_Vd: case AARCH64_OPND_SVE_Vm: case AARCH64_OPND_SVE_Vn: - reg =3D aarch64_reg_parse (&str, REG_TYPE_BHSDQ, NULL); - if (!reg) - { - first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ))); - goto failure; - } - gas_assert (reg->type >=3D REG_TYPE_FP_B - && reg->type <=3D REG_TYPE_FP_Q); - - info->reg.regno =3D reg->number; - info->qualifier =3D AARCH64_OPND_QLF_S_B + (reg->type - REG_TYPE_FP_B); + po_int_fp_reg_or_fail (REG_TYPE_BHSDQ); break; =20 case AARCH64_OPND_SVE_Pd: