From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1130) id 387223858436; Thu, 30 Mar 2023 10:13:06 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 387223858436 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Richard Sandiford To: bfd-cvs@sourceware.org Subject: [binutils-gdb] aarch64: Commonise checks for index operands X-Act-Checkin: binutils-gdb X-Git-Author: Richard Sandiford X-Git-Refname: refs/heads/master X-Git-Oldrev: 859f51df4d0e23c21adc2167d738cf1e6c0f2613 X-Git-Newrev: 56ead579a51f797beebc0d7745a613895383fe51 Message-Id: <20230330101306.387223858436@sourceware.org> Date: Thu, 30 Mar 2023 10:13:06 +0000 (GMT) X-BeenThere: binutils-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 30 Mar 2023 10:13:06 -0000 https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D56ead579a51f= 797beebc0d7745a613895383fe51 commit 56ead579a51f797beebc0d7745a613895383fe51 Author: Richard Sandiford Date: Thu Mar 30 11:09:07 2023 +0100 aarch64: Commonise checks for index operands =20 This patch splits out the constraint checking for index operands, so that it can be reused by new SME2 operands. Diff: --- opcodes/aarch64-opc.c | 50 ++++++++++++++++++++++++++++++++---------------= --- 1 file changed, 32 insertions(+), 18 deletions(-) diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index c36e4cc67f6..6b9b19ffc57 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -1450,6 +1450,31 @@ set_other_error (aarch64_operand_error *mismatch_det= ail, int idx, set_error (mismatch_detail, AARCH64_OPDE_OTHER_ERROR, idx, error); } =20 +/* Check that indexed register operand OPND has a register in the range + [MIN_REGNO, MAX_REGNO] and an index in the range [MIN_INDEX, MAX_INDEX]. + PREFIX is the register prefix, such as "z" for SVE vector registers. */ + +static bool +check_reglane (const aarch64_opnd_info *opnd, + aarch64_operand_error *mismatch_detail, int idx, + const char *prefix, int min_regno, int max_regno, + int min_index, int max_index) +{ + if (!value_in_range_p (opnd->reglane.regno, min_regno, max_regno)) + { + set_invalid_regno_error (mismatch_detail, idx, prefix, min_regno, + max_regno); + return false; + } + if (!value_in_range_p (opnd->reglane.index, min_index, max_index)) + { + set_elem_idx_out_of_range_error (mismatch_detail, idx, min_index, + max_index); + return false; + } + return true; +} + /* Check that indexed ZA operand OPND has: =20 - a selection register in the range [MIN_WREG, MIN_WREG + 3] @@ -1578,28 +1603,17 @@ operand_general_constraint_met_p (const aarch64_opn= d_info *opnds, int idx, case AARCH64_OPND_SVE_Zm4_INDEX: size =3D get_operand_fields_width (get_operand_from_code (type)); shift =3D get_operand_specific_data (&aarch64_operands[type]); - mask =3D (1 << shift) - 1; - if (opnd->reg.regno > mask) - { - set_invalid_regno_error (mismatch_detail, idx, "z", 0, mask); - return 0; - } - mask =3D (1u << (size - shift)) - 1; - if (!value_in_range_p (opnd->reglane.index, 0, mask)) - { - set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, mask); - return 0; - } + if (!check_reglane (opnd, mismatch_detail, idx, + "z", 0, (1 << shift) - 1, + 0, (1u << (size - shift)) - 1)) + return 0; break; =20 case AARCH64_OPND_SVE_Zn_INDEX: size =3D aarch64_get_qualifier_esize (opnd->qualifier); - if (!value_in_range_p (opnd->reglane.index, 0, 64 / size - 1)) - { - set_elem_idx_out_of_range_error (mismatch_detail, idx, - 0, 64 / size - 1); - return 0; - } + if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 31, + 0, 64 / size - 1)) + return 0; break; =20 case AARCH64_OPND_SVE_ZnxN: