From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1130) id CA5553857B98; Thu, 30 Mar 2023 10:13:46 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org CA5553857B98 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Richard Sandiford To: bfd-cvs@sourceware.org Subject: [binutils-gdb] aarch64: Add a aarch64_cpu_supports_inst_p helper X-Act-Checkin: binutils-gdb X-Git-Author: Richard Sandiford X-Git-Refname: refs/heads/master X-Git-Oldrev: d09b87e0b11f14c267014e22716b91ba61c1e458 X-Git-Newrev: 199cfcc4754cea6f4c42dcbb8d8d5161f5b2d186 Message-Id: <20230330101346.CA5553857B98@sourceware.org> Date: Thu, 30 Mar 2023 10:13:46 +0000 (GMT) X-BeenThere: binutils-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 30 Mar 2023 10:13:46 -0000 https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D199cfcc4754c= ea6f4c42dcbb8d8d5161f5b2d186 commit 199cfcc4754cea6f4c42dcbb8d8d5161f5b2d186 Author: Richard Sandiford Date: Thu Mar 30 11:09:09 2023 +0100 aarch64: Add a aarch64_cpu_supports_inst_p helper =20 Quite a lot of SME2 instructions have an opcode bit that selects between 32-bit and 64-bit forms of an instruction, with the 32-bit forms being part of base SME2 and with the 64-bit forms being part of an optional extension. It's nevertheless useful to have a single opcode entry for both forms since (a) that matches the ISA definition and (b) it tends to improve error reporting. =20 This patch therefore adds a libopcodes function called aarch64_cpu_supports_inst_p that tests whether the target supports a particular instruction. In future it will depend on internal libopcodes routines. Diff: --- gas/config/tc-aarch64.c | 3 +-- include/opcode/aarch64.h | 3 +++ opcodes/aarch64-opc.c | 13 +++++++++++++ 3 files changed, 17 insertions(+), 2 deletions(-) diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index c8e37623d9e..71b63d3f7b3 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -8116,8 +8116,7 @@ md_assemble (char *str) && do_encode (inst_base->opcode, &inst.base, &inst_base->value)) { /* Check that this instruction is supported for this CPU. */ - if (!opcode->avariant - || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant, *opcode->avariant)) + if (!aarch64_cpu_supports_inst_p (cpu_variant, inst_base)) { as_bad (_("selected processor does not support `%s'"), str); return; diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index d09897f48d4..61afe561a12 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -1471,6 +1471,9 @@ aarch64_get_operand_desc (enum aarch64_opnd); extern bool aarch64_sve_dupm_mov_immediate_p (uint64_t, int); =20 +extern bool +aarch64_cpu_supports_inst_p (uint64_t, aarch64_inst *); + #ifdef DEBUG_AARCH64 extern int debug_dump; =20 diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index b9029010c47..7a88c19633d 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -6158,6 +6158,19 @@ aarch64_sve_dupm_mov_immediate_p (uint64_t uvalue, i= nt esize) return svalue < -128 || svalue >=3D 128; } =20 +/* Return true if a CPU with the AARCH64_FEATURE_* bits in CPU_VARIANT + supports the instruction described by INST. */ + +bool +aarch64_cpu_supports_inst_p (uint64_t cpu_variant, aarch64_inst *inst) +{ + if (!inst->opcode->avariant + || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant, *inst->opcode->avaria= nt)) + return false; + + return true; +} + /* Include the opcode description table as well as the operand description table. */ #define VERIFIER(x) verify_##x