From: Richard Sandiford <rsandifo@sourceware.org>
To: bfd-cvs@sourceware.org
Subject: [binutils-gdb] aarch64: Add +sme2
Date: Thu, 30 Mar 2023 10:14:22 +0000 (GMT) [thread overview]
Message-ID: <20230330101422.E5C263857C5A@sourceware.org> (raw)
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=60336e19658f1b820753ac09797f14b26e594cfa
commit 60336e19658f1b820753ac09797f14b26e594cfa
Author: Richard Sandiford <richard.sandiford@arm.com>
Date: Thu Mar 30 11:09:10 2023 +0100
aarch64: Add +sme2
This patch adds bare-bones support for +sme2. Later patches
fill in the rest.
Diff:
---
gas/NEWS | 2 ++
gas/config/tc-aarch64.c | 2 ++
gas/doc/c-aarch64.texi | 2 ++
include/opcode/aarch64.h | 1 +
4 files changed, 7 insertions(+)
diff --git a/gas/NEWS b/gas/NEWS
index 4ae2089901c..05fbed113c2 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
-*- text -*-
+* Add SME2 support to the AArch64 port.
+
Changes in 2.40:
* Add support for Intel RAO-INT instructions.
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 2d4c6106506..6ebfcda7dff 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10183,6 +10183,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
AARCH64_FEATURE (AARCH64_FEATURE_SME, 0)},
{"sme-i16i64", AARCH64_FEATURE (AARCH64_FEATURE_SME_I16I64, 0),
AARCH64_FEATURE (AARCH64_FEATURE_SME, 0)},
+ {"sme2", AARCH64_FEATURE (AARCH64_FEATURE_SME2, 0),
+ AARCH64_FEATURE (AARCH64_FEATURE_SME, 0)},
{"bf16", AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16, 0),
AARCH64_FEATURE (AARCH64_FEATURE_FP, 0)},
{"i8mm", AARCH64_FEATURE (AARCH64_FEATURE_I8MM, 0),
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 3921c0d368e..acde4a77dd2 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -235,6 +235,8 @@ automatically cause those extensions to be disabled.
@tab Enable SME F64F64 Extension.
@item @code{sme-i16i64} @tab Armv9-A @tab No
@tab Enable SME I16I64 Extension.
+@item @code{sme2} @tab Armv9-A @tab No
+ @tab Enable SME2. This implies @code{sme}.
@item @code{ssbs} @tab ARMv8-A @tab ARMv8.5-A or later
@tab Enable Speculative Store Bypassing Safe state read and write.
@item @code{sve} @tab ARMv8.2-A @tab Armv9-A or later
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index ef59d531d17..5c9b5e5dac1 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -100,6 +100,7 @@ typedef uint32_t aarch64_insn;
#define AARCH64_FEATURE_SME_I16I64 (1ULL << 58) /* SME I16I64. */
#define AARCH64_FEATURE_V8_8 (1ULL << 59) /* Armv8.8 processors. */
#define AARCH64_FEATURE_CSSC (1ULL << 60) /* Common Short Sequence Compression instructions. */
+#define AARCH64_FEATURE_SME2 (1ULL << 61) /* SME2. */
/* Crypto instructions are the combination of AES and SHA2. */
#define AARCH64_FEATURE_CRYPTO (AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_AES)
reply other threads:[~2023-03-30 10:14 UTC|newest]
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