From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1130) id B918B3858421; Thu, 30 Mar 2023 10:15:13 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B918B3858421 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Richard Sandiford To: bfd-cvs@sourceware.org Subject: [binutils-gdb] aarch64: Add the SME2 ADD and SUB instructions X-Act-Checkin: binutils-gdb X-Git-Author: Richard Sandiford X-Git-Refname: refs/heads/master X-Git-Oldrev: cbd11b8818335007cf960e0cecc4dec445f80327 X-Git-Newrev: e87ff6724fe32ecff11fc36a19a09ab8fbc66c13 Message-Id: <20230330101513.B918B3858421@sourceware.org> Date: Thu, 30 Mar 2023 10:15:13 +0000 (GMT) X-BeenThere: binutils-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 30 Mar 2023 10:15:13 -0000 https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3De87ff6724fe3= 2ecff11fc36a19a09ab8fbc66c13 commit e87ff6724fe32ecff11fc36a19a09ab8fbc66c13 Author: Richard Sandiford Date: Thu Mar 30 11:09:13 2023 +0100 aarch64: Add the SME2 ADD and SUB instructions =20 Add support for the SME2 ADD. SUB, FADD and FSUB instructions. SUB and FSUB have the same form as ADD and FADD, except that ADD also has a 2-operand accumulating form. =20 The 64-bit ADD/SUB instructions require FEAT_SME_I16I64 and the 64-bit FADD/FSUB instructions require FEAT_SME_F64F64. =20 These are the first instructions to have tied register list operands, as opposed to tied single registers. =20 The parse_operands change prevents unsuffixed Z registers (width=3D=3D-= 1) from being treated as though they had an Advanced SIMD-style suffix (.4s etc.). It means that: =20 Error: expected element type rather than vector type at operand 2 -- = `add za\.s\[w8,0\],{z0-z1}' =20 becomes: =20 Error: missing type suffix at operand 2 -- `add za\.s\[w8,0\],{z0-z1}' Diff: --- gas/config/tc-aarch64.c | 3 +- gas/testsuite/gas/aarch64/sme2-9-invalid.d | 3 + gas/testsuite/gas/aarch64/sme2-9-invalid.l | 179 ++++ gas/testsuite/gas/aarch64/sme2-9-invalid.s | 128 +++ gas/testsuite/gas/aarch64/sme2-9-noarch.d | 3 + gas/testsuite/gas/aarch64/sme2-9-noarch.l | 177 ++++ gas/testsuite/gas/aarch64/sme2-9.d | 185 ++++ gas/testsuite/gas/aarch64/sme2-9.s | 199 ++++ gas/testsuite/gas/aarch64/sme2-f64f64-1-invalid.d | 3 + gas/testsuite/gas/aarch64/sme2-f64f64-1-invalid.l | 27 + gas/testsuite/gas/aarch64/sme2-f64f64-1-invalid.s | 20 + gas/testsuite/gas/aarch64/sme2-f64f64-1-noarch.d | 3 + gas/testsuite/gas/aarch64/sme2-f64f64-1-noarch.l | 33 + gas/testsuite/gas/aarch64/sme2-f64f64-1.d | 41 + gas/testsuite/gas/aarch64/sme2-f64f64-1.s | 35 + gas/testsuite/gas/aarch64/sme2-i16i64-1-invalid.d | 3 + gas/testsuite/gas/aarch64/sme2-i16i64-1-invalid.l | 111 +++ gas/testsuite/gas/aarch64/sme2-i16i64-1-invalid.s | 86 ++ gas/testsuite/gas/aarch64/sme2-i16i64-1-noarch.d | 3 + gas/testsuite/gas/aarch64/sme2-i16i64-1-noarch.l | 57 ++ gas/testsuite/gas/aarch64/sme2-i16i64-1.d | 65 ++ gas/testsuite/gas/aarch64/sme2-i16i64-1.s | 61 ++ include/opcode/aarch64.h | 3 + opcodes/aarch64-asm-2.c | 51 +- opcodes/aarch64-asm.c | 2 + opcodes/aarch64-dis-2.c | 1089 ++++++++++++-----= ---- opcodes/aarch64-dis.c | 2 + opcodes/aarch64-opc-2.c | 1 + opcodes/aarch64-opc.c | 71 +- opcodes/aarch64-opc.h | 1 + opcodes/aarch64-tbl.h | 20 + 31 files changed, 2177 insertions(+), 488 deletions(-) diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 652fd4e6ff3..5e023152c17 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -6659,6 +6659,7 @@ parse_operands (char *str, const aarch64_opcode *opco= de) case AARCH64_OPND_SVE_Zm_16: case AARCH64_OPND_SVE_Zn: case AARCH64_OPND_SVE_Zt: + case AARCH64_OPND_SME_Zm: reg_type =3D REG_TYPE_Z; goto vector_reg; =20 @@ -6811,7 +6812,7 @@ parse_operands (char *str, const aarch64_opcode *opco= de) goto failure; } =20 - if (vectype.width !=3D 0 && *str !=3D ',') + if ((int) vectype.width > 0 && *str !=3D ',') { set_fatal_syntax_error (_("expected element type rather than vector type")); diff --git a/gas/testsuite/gas/aarch64/sme2-9-invalid.d b/gas/testsuite/gas= /aarch64/sme2-9-invalid.d new file mode 100644 index 00000000000..78b3fa2875b --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-9-invalid.d @@ -0,0 +1,3 @@ +#as: -march=3Darmv8-a +#source: sme2-9-invalid.s +#error_output: sme2-9-invalid.l diff --git a/gas/testsuite/gas/aarch64/sme2-9-invalid.l b/gas/testsuite/gas= /aarch64/sme2-9-invalid.l new file mode 100644 index 00000000000..e181f0b7378 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-9-invalid.l @@ -0,0 +1,179 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 --= `add 0,{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected '{' at operand 2 -- `add za\.s\[w8,0\],0' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at= operand 1 -- `add za\.s\[w7,0\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at= operand 1 -- `add za\.s\[w12,0\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 --= `add za\.s\[w8,-1\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 --= `add za\.s\[w8,8\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- = `add za\.s\[w8,0\],{z0\.s-z2\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\= .s\[w8,0\],{z1\.s-z2\.s}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at= operand 1 -- `add za\.s\[w7,0\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at= operand 1 -- `add za\.s\[w12,0\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 --= `add za\.s\[w8,-1\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 --= `add za\.s\[w8,8\],{z1\.s-z3\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\= .s\[w8,0\],{z1\.s-z4\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\= .s\[w8,0\],{z2\.s-z5\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\= .s\[w8,0\],{z3\.s-z6\.s}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `add = za\.s\[w8,0,vgx4\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `add = za\.s\[w8,0,vgx2\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\[w8,0\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d} +[^ :]+:[0-9]+: Error: missing type suffix at operand 2 -- `add za\.s\[w8,0= \],{z0-z1}' +[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 --= `add 0,{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected '{' at operand 2 -- `add za\.s\[w8,0\],0,z0= \.s' +[^ :]+:[0-9]+: Error: expected a register or register list at operand 3 --= `add za\.s\[w8,0\],{z0\.s-z1\.s},0' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at= operand 1 -- `add za\.s\[w0,0\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a 32-bit selection register at operand 1 --= `add za\.s\[w31,0\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 --= `add za\.s\[w8,1<<63\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `add za\.s\[w8,0\],{= z0\.s-z1\.s},z31\.s' +[^ :]+:[0-9]+: Error: the last offset is equal to the first offset at oper= and 1 -- `add za\.s\[w8,0:0\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: the last offset is less than the first offset at ope= rand 1 -- `add za\.s\[w8,0:-1\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a single offset rather than a range at oper= and 1 -- `add za\.s\[w8,0:1\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a single offset rather than a range at oper= and 1 -- `add za\.s\[w8,0:100\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at= operand 1 -- `add za\.s\[w7,0\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at= operand 1 -- `add za\.s\[w12,0\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 --= `add za\.s\[w8,-1\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 --= `add za\.s\[w8,8\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `add za\.s\[w8,0\],{= z0\.s-z1\.s},z16\.s' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at= operand 1 -- `add za\.s\[w7,0\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at= operand 1 -- `add za\.s\[w12,0\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 --= `add za\.s\[w8,-1\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 --= `add za\.s\[w8,8\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `add za\.s\[w8,0\],{= z0\.s-z3\.s},z16\.s' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- = `add za\.s\[w8,0\],{z0\.s-z2\.s},z0\.s' +[^ :]+:[0-9]+: Error: too many registers in vector register list at operan= d 2 -- `add za\.s\[w8,0\],{z0\.s-z4\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- = `add za\.s\[w8,0\],{z0\.s,z1\.s,z2\.s},z0\.s' +[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `add za\.s\[w8= ,0\],{z0\.s,z1\.s,z5\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `add = za\.s\[w8,0,vgx4\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `add = za\.s\[w8,0,vgx2\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\[w8,0\],{z0\.s-z1\.s},z0= \.s' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d +[^ :]+:[0-9]+: Error: missing type suffix at operand 2 -- `add za\.s\[w8,0= \],{z0-z1},z0\.s' +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\.s\[w8,0\],{z0\.s-z1\.s}= ,z0' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\[w8,0\],{z0\.s-z1\.s},z0' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at= operand 1 -- `add za\.s\[w7,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at= operand 1 -- `add za\.s\[w12,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 --= `add za\.s\[w8,-1\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 --= `add za\.s\[w8,8\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\= .s\[w8,0\],{z1\.s-z2\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `add za\= .s\[w8,0\],{z0\.s-z1\.s},{z15\.s-z16\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `add za\= .s\[w8,0\],{z0\.s-z1\.s},{z31\.s,z0\.s}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at= operand 1 -- `add za\.s\[w7,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at= operand 1 -- `add za\.s\[w12,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 --= `add za\.s\[w8,-1\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 --= `add za\.s\[w8,8\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\= .s\[w8,0\],{z1\.s-z4\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\= .s\[w8,0\],{z2\.s-z5\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\= .s\[w8,0\],{z3\.s-z6\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `add za\= .s\[w8,0\],{z0\.s-z3\.s},{z15\.s-z18\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `add za\= .s\[w8,0\],{z0\.s-z3\.s},{z29\.s,z30\.s,z31\.s,z0\.s}' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- = `add za\.s\[w8,0\],{z0\.s-z2\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `add = za\.s\[w8,0\],{z0\.s-z3\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `add = za\.s\[w8,0\],{z0\.s-z1\.s},{z0\.s-z2\.s}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `add = za\.s\[w8,0\],{z0\.s-z1\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: too many registers in vector register list at operan= d 3 -- `add za\.s\[w8,0\],{z0\.s-z1\.s},{z0\.s-z4\.s}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `add = za\.s\[w8,0,vgx4\],{z0\.s-z1\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `add = za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `add = za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `add = za\.s\[w8,0,vgx2\],{z0\.s-z3\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\[w8,0\],{z0\.s-z1\.s},{z= 0\.s-z1\.s}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\[w8,0\],{z0\.s-z3\.s},{z= 0\.s-z3\.s}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- = `add {z0\.b-z1\.b},{z0\.b-z2\.b},z0\.b' +[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- = `add {z0\.b-z1\.b},{z0\.b-z3\.b},z0\.b' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 1 -- = `add {z0\.b-z2\.b},{z0\.b-z2\.b},z0\.b' +[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- = `add {z0\.b-z1\.b},{z2\.b-z3\.b},z0\.b' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `add {z1= \.b-z2\.b},{z1\.b-z2\.b},z0\.b' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `add {z3= 1\.b,z0\.b},{z31\.b,z0\.b},z0\.b' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `add {z0\.b-z1\.b},{= z0\.b-z1\.b},z16\.b' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `add {z0\.b-z1\.b},{= z0\.b-z1\.b},z31\.b' +[^ :]+:[0-9]+: Error: operand mismatch -- `add {z0\.b-z1\.b},{z0\.h-z1\.h}= ,z0\.b' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add {z0\.b-z1\.b}, {z0\.b-z1\.b}, z0\.b +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add {z0\.h-z1\.h}, {z0\.h-z1\.h}, z0\.h +[^ :]+:[0-9]+: Info: add {z0\.s-z1\.s}, {z0\.s-z1\.s}, z0\.s +[^ :]+:[0-9]+: Info: add {z0\.d-z1\.d}, {z0\.d-z1\.d}, z0\.d +[^ :]+:[0-9]+: Error: operand mismatch -- `add {z0\.b-z1\.b},{z0\.b-z1\.b}= ,z0\.h' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add {z0\.b-z1\.b}, {z0\.b-z1\.b}, z0\.b +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add {z0\.h-z1\.h}, {z0\.h-z1\.h}, z0\.h +[^ :]+:[0-9]+: Info: add {z0\.s-z1\.s}, {z0\.s-z1\.s}, z0\.s +[^ :]+:[0-9]+: Info: add {z0\.d-z1\.d}, {z0\.d-z1\.d}, z0\.d +[^ :]+:[0-9]+: Error: operand mismatch -- `add {z0\.q-z1\.q},{z0\.q-z1\.q}= ,z0\.q' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add {z0\.b-z1\.b}, {z0\.b-z1\.b}, z0\.b +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add {z0\.h-z1\.h}, {z0\.h-z1\.h}, z0\.h +[^ :]+:[0-9]+: Info: add {z0\.s-z1\.s}, {z0\.s-z1\.s}, z0\.s +[^ :]+:[0-9]+: Info: add {z0\.d-z1\.d}, {z0\.d-z1\.d}, z0\.d +[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- = `add {z0\.b-z3\.b},{z0\.b-z2\.b},z0\.b' +[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- = `add {z0\.b-z3\.b},{z0\.b-z1\.b},z0\.b' +[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- = `add {z0\.b-z3\.b},{z2\.b-z5\.b},z0\.b' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `add {z1= \.b-z4\.b},{z1\.b-z4\.b},z0\.b' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `add {z2= \.b-z5\.b},{z2\.b-z5\.b},z0\.b' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `add {z3= \.b-z6\.b},{z3\.b-z6\.b},z0\.b' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `add {z3= 1\.b,z0\.b,z1\.b,z2\.b},{z31\.b,z0\.b,z1\.b,z2\.b},z0\.b' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `add {z0\.b-z3\.b},{= z0\.b-z3\.b},z16\.b' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `add {z0\.b-z3\.b},{= z0\.b-z3\.b},z31\.b' +[^ :]+:[0-9]+: Error: operand mismatch -- `add {z0\.b-z3\.b},{z0\.h-z3\.h}= ,z0\.b' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add {z0\.b-z3\.b}, {z0\.b-z3\.b}, z0\.b +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add {z0\.h-z3\.h}, {z0\.h-z3\.h}, z0\.h +[^ :]+:[0-9]+: Info: add {z0\.s-z3\.s}, {z0\.s-z3\.s}, z0\.s +[^ :]+:[0-9]+: Info: add {z0\.d-z3\.d}, {z0\.d-z3\.d}, z0\.d +[^ :]+:[0-9]+: Error: operand mismatch -- `add {z0\.b-z3\.b},{z0\.b-z3\.b}= ,z0\.h' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add {z0\.b-z3\.b}, {z0\.b-z3\.b}, z0\.b +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add {z0\.h-z3\.h}, {z0\.h-z3\.h}, z0\.h +[^ :]+:[0-9]+: Info: add {z0\.s-z3\.s}, {z0\.s-z3\.s}, z0\.s +[^ :]+:[0-9]+: Info: add {z0\.d-z3\.d}, {z0\.d-z3\.d}, z0\.d +[^ :]+:[0-9]+: Error: operand mismatch -- `add {z0\.q-z3\.q},{z0\.q-z3\.q}= ,z0\.q' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add {z0\.b-z3\.b}, {z0\.b-z3\.b}, z0\.b +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add {z0\.h-z3\.h}, {z0\.h-z3\.h}, z0\.h +[^ :]+:[0-9]+: Info: add {z0\.s-z3\.s}, {z0\.s-z3\.s}, z0\.s +[^ :]+:[0-9]+: Info: add {z0\.d-z3\.d}, {z0\.d-z3\.d}, z0\.d +[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sub {z0\.b-z1\.= b},{z0\.b-z1\.b},z0\.b' +[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sub {z0\.h-z1\.= h},{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sub {z0\.s-z1\.= s},{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sub {z0\.d-z1\.= d},{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sub {z0\.b-z3\.= b},{z0\.b-z3\.b},z0\.b' +[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sub {z0\.h-z3\.= h},{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sub {z0\.s-z3\.= s},{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sub {z0\.d-z3\.= d},{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: operand mismatch -- `fadd za\.b\[w8,0\],{z0\.b-z1\.b= }' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: fadd za\.s\[w8, 0\], {z0\.s-z1\.s} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: fadd za\.d\[w8, 0\], {z0\.d-z1\.d} +[^ :]+:[0-9]+: Error: operand mismatch -- `fadd za\.h\[w8,0\],{z0\.h-z1\.h= }' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: fadd za\.s\[w8, 0\], {z0\.s-z1\.s} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: fadd za\.d\[w8, 0\], {z0\.d-z1\.d} diff --git a/gas/testsuite/gas/aarch64/sme2-9-invalid.s b/gas/testsuite/gas= /aarch64/sme2-9-invalid.s new file mode 100644 index 00000000000..d5bfc095e21 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-9-invalid.s @@ -0,0 +1,128 @@ + add 0, { z0.s - z1.s } + add za.s[w8, 0], 0 + + add za.s[w7, 0], { z0.s - z1.s } + add za.s[w12, 0], { z0.s - z1.s } + add za.s[w8, -1], { z0.s - z1.s } + add za.s[w8, 8], { z0.s - z1.s } + add za.s[w8, 0], { z0.s - z2.s } + add za.s[w8, 0], { z1.s - z2.s } + + add za.s[w7, 0], { z0.s - z3.s } + add za.s[w12, 0], { z0.s - z3.s } + add za.s[w8, -1], { z0.s - z3.s } + add za.s[w8, 8], { z1.s - z3.s } + add za.s[w8, 0], { z1.s - z4.s } + add za.s[w8, 0], { z2.s - z5.s } + add za.s[w8, 0], { z3.s - z6.s } + + add za.s[w8, 0, vgx4], { z0.s - z1.s } + add za.s[w8, 0, vgx2], { z0.s - z3.s } + add za[w8, 0], { z0.s - z1.s } + add za.s[w8, 0], { z0 - z1 } + + add 0, { z0.s - z1.s }, z0.s + add za.s[w8, 0], 0, z0.s + add za.s[w8, 0], { z0.s - z1.s }, 0 + + add za.s[w0, 0], { z0.s - z1.s }, z0.s + add za.s[w31, 0], { z0.s - z1.s }, z0.s + add za.s[w8, 1<<63], { z0.s - z1.s }, z0.s + add za.s[w8, 0], { z0.s - z1.s }, z31.s + add za.s[w8, 0:0], { z0.s - z1.s }, z0.s + add za.s[w8, 0:-1], { z0.s - z1.s }, z0.s + add za.s[w8, 0:1], { z0.s - z1.s }, z0.s + add za.s[w8, 0:100], { z0.s - z1.s }, z0.s + + add za.s[w7, 0], { z0.s - z1.s }, z0.s + add za.s[w12, 0], { z0.s - z1.s }, z0.s + add za.s[w8, -1], { z0.s - z1.s }, z0.s + add za.s[w8, 8], { z0.s - z1.s }, z0.s + add za.s[w8, 0], { z0.s - z1.s }, z16.s + + add za.s[w7, 0], { z0.s - z3.s }, z0.s + add za.s[w12, 0], { z0.s - z3.s }, z0.s + add za.s[w8, -1], { z0.s - z3.s }, z0.s + add za.s[w8, 8], { z0.s - z3.s }, z0.s + add za.s[w8, 0], { z0.s - z3.s }, z16.s + + add za.s[w8, 0], { z0.s - z2.s }, z0.s + add za.s[w8, 0], { z0.s - z4.s }, z0.s + add za.s[w8, 0], { z0.s, z1.s, z2.s }, z0.s + add za.s[w8, 0], { z0.s, z1.s, z5.s }, z0.s + + add za.s[w8, 0, vgx4], { z0.s - z1.s }, z0.s + add za.s[w8, 0, vgx2], { z0.s - z3.s }, z0.s + add za[w8, 0], { z0.s - z1.s }, z0.s + add za.s[w8, 0], { z0 - z1 }, z0.s + add za.s[w8, 0], { z0.s - z1.s }, z0 + add za[w8, 0], { z0.s - z1.s }, z0 + + add za.s[w7, 0], { z0.s - z1.s }, { z0.s - z1.s } + add za.s[w12, 0], { z0.s - z1.s }, { z0.s - z1.s } + add za.s[w8, -1], { z0.s - z1.s }, { z0.s - z1.s } + add za.s[w8, 8], { z0.s - z1.s }, { z0.s - z1.s } + add za.s[w8, 0], { z1.s - z2.s }, { z0.s - z1.s } + add za.s[w8, 0], { z0.s - z1.s }, { z15.s - z16.s } + add za.s[w8, 0], { z0.s - z1.s }, { z31.s, z0.s } + + add za.s[w7, 0], { z0.s - z3.s }, { z0.s - z3.s } + add za.s[w12, 0], { z0.s - z3.s }, { z0.s - z3.s } + add za.s[w8, -1], { z0.s - z3.s }, { z0.s - z3.s } + add za.s[w8, 8], { z0.s - z3.s }, { z0.s - z3.s } + add za.s[w8, 0], { z1.s - z4.s }, { z0.s - z3.s } + add za.s[w8, 0], { z2.s - z5.s }, { z0.s - z3.s } + add za.s[w8, 0], { z3.s - z6.s }, { z0.s - z3.s } + add za.s[w8, 0], { z0.s - z3.s }, { z15.s - z18.s } + add za.s[w8, 0], { z0.s - z3.s }, { z29.s, z30.s, z31.s, z0.s } + + add za.s[w8, 0], { z0.s - z2.s }, { z0.s - z1.s } + add za.s[w8, 0], { z0.s - z3.s }, { z0.s - z1.s } + add za.s[w8, 0], { z0.s - z1.s }, { z0.s - z2.s } + add za.s[w8, 0], { z0.s - z1.s }, { z0.s - z3.s } + add za.s[w8, 0], { z0.s - z1.s }, { z0.s - z4.s } + + add za.s[w8, 0, vgx4], { z0.s - z1.s }, { z0.s - z3.s } + add za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z1.s } + add za.s[w8, 0, vgx2], { z0.s - z1.s }, { z0.s - z3.s } + add za.s[w8, 0, vgx2], { z0.s - z3.s }, { z0.s - z1.s } + add za[w8, 0], { z0.s - z1.s }, { z0.s - z1.s } + add za[w8, 0], { z0.s - z3.s }, { z0.s - z3.s } + + add { z0.b - z1.b }, { z0.b - z2.b }, z0.b + add { z0.b - z1.b }, { z0.b - z3.b }, z0.b + add { z0.b - z2.b }, { z0.b - z2.b }, z0.b + add { z0.b - z1.b }, { z2.b - z3.b }, z0.b + add { z1.b - z2.b }, { z1.b - z2.b }, z0.b + add { z31.b, z0.b }, { z31.b, z0.b }, z0.b + add { z0.b - z1.b }, { z0.b - z1.b }, z16.b + add { z0.b - z1.b }, { z0.b - z1.b }, z31.b + add { z0.b - z1.b }, { z0.h - z1.h }, z0.b + add { z0.b - z1.b }, { z0.b - z1.b }, z0.h + add { z0.q - z1.q }, { z0.q - z1.q }, z0.q + + add { z0.b - z3.b }, { z0.b - z2.b }, z0.b + add { z0.b - z3.b }, { z0.b - z1.b }, z0.b + add { z0.b - z3.b }, { z2.b - z5.b }, z0.b + add { z1.b - z4.b }, { z1.b - z4.b }, z0.b + add { z2.b - z5.b }, { z2.b - z5.b }, z0.b + add { z3.b - z6.b }, { z3.b - z6.b }, z0.b + add { z31.b, z0.b, z1.b, z2.b }, { z31.b, z0.b, z1.b, z2.b }, z0.b + add { z0.b - z3.b }, { z0.b - z3.b }, z16.b + add { z0.b - z3.b }, { z0.b - z3.b }, z31.b + add { z0.b - z3.b }, { z0.h - z3.h }, z0.b + add { z0.b - z3.b }, { z0.b - z3.b }, z0.h + add { z0.q - z3.q }, { z0.q - z3.q }, z0.q + + sub { z0.b - z1.b }, { z0.b - z1.b }, z0.b + sub { z0.h - z1.h }, { z0.h - z1.h }, z0.h + sub { z0.s - z1.s }, { z0.s - z1.s }, z0.s + sub { z0.d - z1.d }, { z0.d - z1.d }, z0.d + + sub { z0.b - z3.b }, { z0.b - z3.b }, z0.b + sub { z0.h - z3.h }, { z0.h - z3.h }, z0.h + sub { z0.s - z3.s }, { z0.s - z3.s }, z0.s + sub { z0.d - z3.d }, { z0.d - z3.d }, z0.d + + fadd za.b[w8, 0], { z0.b - z1.b } + fadd za.h[w8, 0], { z0.h - z1.h } diff --git a/gas/testsuite/gas/aarch64/sme2-9-noarch.d b/gas/testsuite/gas/= aarch64/sme2-9-noarch.d new file mode 100644 index 00000000000..076b3dabf58 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-9-noarch.d @@ -0,0 +1,3 @@ +#as: -march=3Darmv8-a+sme +#source: sme2-9.s +#error_output: sme2-9-noarch.l diff --git a/gas/testsuite/gas/aarch64/sme2-9-noarch.l b/gas/testsuite/gas/= aarch64/sme2-9-noarch.l new file mode 100644 index 00000000000..1a2ad07a209 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-9-noarch.l @@ -0,0 +1,177 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0= \],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0= ,vgx2\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.s\[W8,0= ,VGx2\],{Z0\.s-Z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.S\[W8,0= ,VGX2\],{Z0\.S-Z1\.S}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w11,= 0\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,7= \],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0= \],{z30\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w10,= 3\],{z10\.s-z11\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0= \],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0= ,vgx4\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.s\[W8,0= ,VGx4\],{Z0\.s-Z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.S\[W8,0= ,VGX4\],{Z0\.S-Z3\.S}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w11,= 0\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,7= \],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0= \],{z28\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w11,= 1\],{z12\.s-z15\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0= \],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0= ,vgx2\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.s\[W8,0= ,VGx2\],{Z0\.s-Z1\.s},Z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.S\[W8,0= ,VGX2\],{Z0\.S-Z1\.S},Z0\.S' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w11,= 0\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,7= \],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0= \],{z30\.s-z31\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0= \],{z31\.s,z0\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0= \],{z31\.s-z0\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0= \],{z0\.s-z1\.s},z15\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w9,5= \],{z9\.s-z10\.s},z6\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0= \],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0= ,vgx4\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.s\[W8,0= ,VGx4\],{Z0\.s-Z3\.s},Z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.S\[W8,0= ,VGX4\],{Z0\.S-Z3\.S},Z0\.S' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w11,= 0\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,7= \],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0= \],{z28\.s-z31\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0= \],{z31\.s,z0\.s,z1\.s,z2\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0= \],{z31\.s-z2\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0= \],{z0\.s-z3\.s},z15\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w11,= 2\],{z23\.s-z26\.s},z13\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0= \],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0= ,vgx2\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.s\[W8,0= ,VGx2\],{Z0\.s-Z1\.s},{Z0\.s-Z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.S\[W8,0= ,VGX2\],{Z0\.S-Z1\.S},{Z0\.S-Z1\.S}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w11,= 0\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,7= \],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0= \],{z30\.s-z31\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0= \],{z0\.s-z1\.s},{z30\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w10,= 1\],{z22\.s-z23\.s},{z18\.s-z19\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0= \],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0= ,vgx4\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.s\[W8,0= ,VGx4\],{Z0\.s-Z3\.s},{Z0\.s-Z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.S\[W8,0= ,VGX4\],{Z0\.S-Z3\.S},{Z0\.S-Z3\.S}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w11,= 0\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,7= \],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0= \],{z28\.s-z31\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0= \],{z0\.s-z3\.s},{z28\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w11,= 3\],{z16\.s-z19\.s},{z24\.s-z27\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.b-z1\.= b},{z0\.b-z1\.b},z0\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z30\.b-z31= \.b},{z30\.b-z31\.b},z0\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.b-z1\.= b},{z0\.b-z1\.b},z15\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z14\.b-z15= \.b},{z14\.b-z15\.b},z5\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.h-z1\.= h},{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z30\.h-z31= \.h},{z30\.h-z31\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.h-z1\.= h},{z0\.h-z1\.h},z15\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z20\.h-z21= \.h},{z20\.h-z21\.h},z11\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.s-z1\.= s},{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z30\.s-z31= \.s},{z30\.s-z31\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.s-z1\.= s},{z0\.s-z1\.s},z15\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z2\.s-z3\.= s},{z2\.s-z3\.s},z9\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.d-z1\.= d},{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z30\.d-z31= \.d},{z30\.d-z31\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.d-z1\.= d},{z0\.d-z1\.d},z15\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z28\.d-z29= \.d},{z28\.d-z29\.d},z1\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.b-z3\.= b},{z0\.b-z3\.b},z0\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z28\.b-z31= \.b},{z28\.b-z31\.b},z0\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.b-z3\.= b},{z0\.b-z3\.b},z15\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z24\.b-z27= \.b},{z24\.b-z27\.b},z5\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.h-z3\.= h},{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z28\.h-z31= \.h},{z28\.h-z31\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.h-z3\.= h},{z0\.h-z3\.h},z15\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z20\.h-z23= \.h},{z20\.h-z23\.h},z11\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.s-z3\.= s},{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z28\.s-z31= \.s},{z28\.s-z31\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.s-z3\.= s},{z0\.s-z3\.s},z15\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z4\.s-z7\.= s},{z4\.s-z7\.s},z9\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.d-z3\.= d},{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z28\.d-z31= \.d},{z28\.d-z31\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.d-z3\.= d},{z0\.d-z3\.d},z15\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z16\.d-z19= \.d},{z16\.d-z19\.d},z3\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0= \],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0= ,vgx2\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.s\[W8,0= ,VGx2\],{Z0\.s-Z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.S\[W8,0= ,VGX2\],{Z0\.S-Z1\.S}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w11,= 0\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,7= \],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0= \],{z30\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w10,= 3\],{z10\.s-z11\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0= \],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0= ,vgx4\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.s\[W8,0= ,VGx4\],{Z0\.s-Z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.S\[W8,0= ,VGX4\],{Z0\.S-Z3\.S}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w11,= 0\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,7= \],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0= \],{z28\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w11,= 1\],{z12\.s-z15\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0= \],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0= ,vgx2\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.s\[W8,0= ,VGx2\],{Z0\.s-Z1\.s},Z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.S\[W8,0= ,VGX2\],{Z0\.S-Z1\.S},Z0\.S' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w11,= 0\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,7= \],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0= \],{z30\.s-z31\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0= \],{z31\.s,z0\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0= \],{z31\.s-z0\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0= \],{z0\.s-z1\.s},z15\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w9,5= \],{z9\.s-z10\.s},z6\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0= \],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0= ,vgx4\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.s\[W8,0= ,VGx4\],{Z0\.s-Z3\.s},Z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.S\[W8,0= ,VGX4\],{Z0\.S-Z3\.S},Z0\.S' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w11,= 0\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,7= \],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0= \],{z28\.s-z31\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0= \],{z31\.s,z0\.s,z1\.s,z2\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0= \],{z31\.s-z2\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0= \],{z0\.s-z3\.s},z15\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w11,= 2\],{z23\.s-z26\.s},z13\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0= \],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0= ,vgx2\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.s\[W8,0= ,VGx2\],{Z0\.s-Z1\.s},{Z0\.s-Z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.S\[W8,0= ,VGX2\],{Z0\.S-Z1\.S},{Z0\.S-Z1\.S}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w11,= 0\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,7= \],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0= \],{z30\.s-z31\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0= \],{z0\.s-z1\.s},{z30\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w10,= 1\],{z22\.s-z23\.s},{z18\.s-z19\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0= \],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0= ,vgx4\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.s\[W8,0= ,VGx4\],{Z0\.s-Z3\.s},{Z0\.s-Z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.S\[W8,0= ,VGX4\],{Z0\.S-Z3\.S},{Z0\.S-Z3\.S}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w11,= 0\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,7= \],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0= \],{z28\.s-z31\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0= \],{z0\.s-z3\.s},{z28\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w11,= 3\],{z16\.s-z19\.s},{z24\.s-z27\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w8,= 0\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w8,= 0,vgx2\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd ZA\.s\[W8,= 0,VGx2\],{Z0\.s-Z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd ZA\.S\[W8,= 0,VGX2\],{Z0\.S-Z1\.S}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w11= ,0\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w8,= 7\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w8,= 0\],{z30\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w10= ,3\],{z10\.s-z11\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w8,= 0\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w8,= 0,vgx4\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd ZA\.s\[W8,= 0,VGx4\],{Z0\.s-Z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd ZA\.S\[W8,= 0,VGX4\],{Z0\.S-Z3\.S}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w11= ,0\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w8,= 7\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w8,= 0\],{z28\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w11= ,1\],{z12\.s-z15\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w8,= 0\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w8,= 0,vgx2\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub ZA\.s\[W8,= 0,VGx2\],{Z0\.s-Z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub ZA\.S\[W8,= 0,VGX2\],{Z0\.S-Z1\.S}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w11= ,0\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w8,= 7\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w8,= 0\],{z30\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w10= ,3\],{z10\.s-z11\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w8,= 0\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w8,= 0,vgx4\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub ZA\.s\[W8,= 0,VGx4\],{Z0\.s-Z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub ZA\.S\[W8,= 0,VGX4\],{Z0\.S-Z3\.S}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w11= ,0\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w8,= 7\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w8,= 0\],{z28\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w11= ,1\],{z12\.s-z15\.s}' diff --git a/gas/testsuite/gas/aarch64/sme2-9.d b/gas/testsuite/gas/aarch64= /sme2-9.d new file mode 100644 index 00000000000..ece09550d66 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-9.d @@ -0,0 +1,185 @@ +#as: -march=3Darmv8-a+sme2 +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +[^:]+: c1a01c10 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c10 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c10 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c10 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a07c10 add za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c17 add za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01fd0 add za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s} +[^:]+: c1a05d53 add za\.s\[w10, 3, vgx2\], {z10\.s-z11\.s} +[^:]+: c1a11c10 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c10 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c10 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c10 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a17c10 add za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c17 add za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11f90 add za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s} +[^:]+: c1a17d91 add za\.s\[w11, 1, vgx4\], {z12\.s-z15\.s} +[^:]+: c1201810 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1201810 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1201810 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1201810 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1207810 add za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1201817 add za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1201bd0 add za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}, z0\.s +[^:]+: c1201bf0 add za\.s\[w8, 0, vgx2\], {z31\.s-z0\.s}, z0\.s +[^:]+: c1201bf0 add za\.s\[w8, 0, vgx2\], {z31\.s-z0\.s}, z0\.s +[^:]+: c12f1810 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z15\.s +[^:]+: c1263935 add za\.s\[w9, 5, vgx2\], {z9\.s-z10\.s}, z6\.s +[^:]+: c1301810 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1301810 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1301810 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1301810 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1307810 add za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1301817 add za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1301b90 add za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}, z0\.s +[^:]+: c1301bf0 add za\.s\[w8, 0, vgx4\], {z31\.s-z2\.s}, z0\.s +[^:]+: c1301bf0 add za\.s\[w8, 0, vgx4\], {z31\.s-z2\.s}, z0\.s +[^:]+: c13f1810 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z15\.s +[^:]+: c13d7af2 add za\.s\[w11, 2, vgx4\], {z23\.s-z26\.s}, z13\.s +[^:]+: c1a01810 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a01810 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a01810 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a01810 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a07810 add za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a01817 add za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a01bd0 add za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}, {z0\.s-z1\.s} +[^:]+: c1be1810 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z30\.s-z31\.s} +[^:]+: c1b25ad1 add za\.s\[w10, 1, vgx2\], {z22\.s-z23\.s}, {z18\.s-z19\.= s} +[^:]+: c1a11810 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a11810 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a11810 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a11810 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a17810 add za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a11817 add za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a11b90 add za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}, {z0\.s-z3\.s} +[^:]+: c1bd1810 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z28\.s-z31\.s} +[^:]+: c1b97a13 add za\.s\[w11, 3, vgx4\], {z16\.s-z19\.s}, {z24\.s-z27\.= s} +[^:]+: c120a300 add {z0\.b-z1\.b}, {z0\.b-z1\.b}, z0\.b +[^:]+: c120a31e add {z30\.b-z31\.b}, {z30\.b-z31\.b}, z0\.b +[^:]+: c12fa300 add {z0\.b-z1\.b}, {z0\.b-z1\.b}, z15\.b +[^:]+: c125a30e add {z14\.b-z15\.b}, {z14\.b-z15\.b}, z5\.b +[^:]+: c160a300 add {z0\.h-z1\.h}, {z0\.h-z1\.h}, z0\.h +[^:]+: c160a31e add {z30\.h-z31\.h}, {z30\.h-z31\.h}, z0\.h +[^:]+: c16fa300 add {z0\.h-z1\.h}, {z0\.h-z1\.h}, z15\.h +[^:]+: c16ba314 add {z20\.h-z21\.h}, {z20\.h-z21\.h}, z11\.h +[^:]+: c1a0a300 add {z0\.s-z1\.s}, {z0\.s-z1\.s}, z0\.s +[^:]+: c1a0a31e add {z30\.s-z31\.s}, {z30\.s-z31\.s}, z0\.s +[^:]+: c1afa300 add {z0\.s-z1\.s}, {z0\.s-z1\.s}, z15\.s +[^:]+: c1a9a302 add {z2\.s-z3\.s}, {z2\.s-z3\.s}, z9\.s +[^:]+: c1e0a300 add {z0\.d-z1\.d}, {z0\.d-z1\.d}, z0\.d +[^:]+: c1e0a31e add {z30\.d-z31\.d}, {z30\.d-z31\.d}, z0\.d +[^:]+: c1efa300 add {z0\.d-z1\.d}, {z0\.d-z1\.d}, z15\.d +[^:]+: c1e1a31c add {z28\.d-z29\.d}, {z28\.d-z29\.d}, z1\.d +[^:]+: c120ab00 add {z0\.b-z3\.b}, {z0\.b-z3\.b}, z0\.b +[^:]+: c120ab1c add {z28\.b-z31\.b}, {z28\.b-z31\.b}, z0\.b +[^:]+: c12fab00 add {z0\.b-z3\.b}, {z0\.b-z3\.b}, z15\.b +[^:]+: c125ab18 add {z24\.b-z27\.b}, {z24\.b-z27\.b}, z5\.b +[^:]+: c160ab00 add {z0\.h-z3\.h}, {z0\.h-z3\.h}, z0\.h +[^:]+: c160ab1c add {z28\.h-z31\.h}, {z28\.h-z31\.h}, z0\.h +[^:]+: c16fab00 add {z0\.h-z3\.h}, {z0\.h-z3\.h}, z15\.h +[^:]+: c16bab14 add {z20\.h-z23\.h}, {z20\.h-z23\.h}, z11\.h +[^:]+: c1a0ab00 add {z0\.s-z3\.s}, {z0\.s-z3\.s}, z0\.s +[^:]+: c1a0ab1c add {z28\.s-z31\.s}, {z28\.s-z31\.s}, z0\.s +[^:]+: c1afab00 add {z0\.s-z3\.s}, {z0\.s-z3\.s}, z15\.s +[^:]+: c1a9ab04 add {z4\.s-z7\.s}, {z4\.s-z7\.s}, z9\.s +[^:]+: c1e0ab00 add {z0\.d-z3\.d}, {z0\.d-z3\.d}, z0\.d +[^:]+: c1e0ab1c add {z28\.d-z31\.d}, {z28\.d-z31\.d}, z0\.d +[^:]+: c1efab00 add {z0\.d-z3\.d}, {z0\.d-z3\.d}, z15\.d +[^:]+: c1e3ab10 add {z16\.d-z19\.d}, {z16\.d-z19\.d}, z3\.d +[^:]+: c1a01c18 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c18 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c18 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c18 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a07c18 sub za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c1f sub za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01fd8 sub za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s} +[^:]+: c1a05d5b sub za\.s\[w10, 3, vgx2\], {z10\.s-z11\.s} +[^:]+: c1a11c18 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c18 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c18 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c18 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a17c18 sub za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c1f sub za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11f98 sub za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s} +[^:]+: c1a17d99 sub za\.s\[w11, 1, vgx4\], {z12\.s-z15\.s} +[^:]+: c1201818 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1201818 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1201818 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1201818 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1207818 sub za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c120181f sub za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1201bd8 sub za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}, z0\.s +[^:]+: c1201bf8 sub za\.s\[w8, 0, vgx2\], {z31\.s-z0\.s}, z0\.s +[^:]+: c1201bf8 sub za\.s\[w8, 0, vgx2\], {z31\.s-z0\.s}, z0\.s +[^:]+: c12f1818 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z15\.s +[^:]+: c126393d sub za\.s\[w9, 5, vgx2\], {z9\.s-z10\.s}, z6\.s +[^:]+: c1301818 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1301818 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1301818 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1301818 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1307818 sub za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c130181f sub za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1301b98 sub za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}, z0\.s +[^:]+: c1301bf8 sub za\.s\[w8, 0, vgx4\], {z31\.s-z2\.s}, z0\.s +[^:]+: c1301bf8 sub za\.s\[w8, 0, vgx4\], {z31\.s-z2\.s}, z0\.s +[^:]+: c13f1818 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z15\.s +[^:]+: c13d7afa sub za\.s\[w11, 2, vgx4\], {z23\.s-z26\.s}, z13\.s +[^:]+: c1a01818 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a01818 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a01818 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a01818 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a07818 sub za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a0181f sub za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a01bd8 sub za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}, {z0\.s-z1\.s} +[^:]+: c1be1818 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z30\.s-z31\.s} +[^:]+: c1b25ad9 sub za\.s\[w10, 1, vgx2\], {z22\.s-z23\.s}, {z18\.s-z19\.= s} +[^:]+: c1a11818 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a11818 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a11818 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a11818 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a17818 sub za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a1181f sub za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a11b98 sub za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}, {z0\.s-z3\.s} +[^:]+: c1bd1818 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z28\.s-z31\.s} +[^:]+: c1b97a1b sub za\.s\[w11, 3, vgx4\], {z16\.s-z19\.s}, {z24\.s-z27\.= s} +[^:]+: c1a01c00 fadd za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c00 fadd za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c00 fadd za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c00 fadd za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a07c00 fadd za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c07 fadd za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01fc0 fadd za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s} +[^:]+: c1a05d43 fadd za\.s\[w10, 3, vgx2\], {z10\.s-z11\.s} +[^:]+: c1a11c00 fadd za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c00 fadd za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c00 fadd za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c00 fadd za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a17c00 fadd za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c07 fadd za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11f80 fadd za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s} +[^:]+: c1a17d81 fadd za\.s\[w11, 1, vgx4\], {z12\.s-z15\.s} +[^:]+: c1a01c08 fsub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c08 fsub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c08 fsub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c08 fsub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a07c08 fsub za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c0f fsub za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01fc8 fsub za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s} +[^:]+: c1a05d4b fsub za\.s\[w10, 3, vgx2\], {z10\.s-z11\.s} +[^:]+: c1a11c08 fsub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c08 fsub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c08 fsub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c08 fsub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a17c08 fsub za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c0f fsub za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11f88 fsub za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s} +[^:]+: c1a17d89 fsub za\.s\[w11, 1, vgx4\], {z12\.s-z15\.s} diff --git a/gas/testsuite/gas/aarch64/sme2-9.s b/gas/testsuite/gas/aarch64= /sme2-9.s new file mode 100644 index 00000000000..838e75b684e --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-9.s @@ -0,0 +1,199 @@ + add za.s[w8, 0], { z0.s - z1.s } + add za.s[w8, 0, vgx2], { z0.s - z1.s } + ADD ZA.s[W8, 0, VGx2], { Z0.s - Z1.s } + ADD ZA.S[W8, 0, VGX2], { Z0.S - Z1.S } + add za.s[w11, 0], { z0.s - z1.s } + add za.s[w8, 7], { z0.s - z1.s } + add za.s[w8, 0], { z30.s - z31.s } + add za.s[w10, 3], { z10.s - z11.s } + + add za.s[w8, 0], { z0.s - z3.s } + add za.s[w8, 0, vgx4], { z0.s - z3.s } + ADD ZA.s[W8, 0, VGx4], { Z0.s - Z3.s } + ADD ZA.S[W8, 0, VGX4], { Z0.S - Z3.S } + add za.s[w11, 0], { z0.s - z3.s } + add za.s[w8, 7], { z0.s - z3.s } + add za.s[w8, 0], { z28.s - z31.s } + add za.s[w11, 1], { z12.s - z15.s } + + add za.s[w8, 0], { z0.s - z1.s }, z0.s + add za.s[w8, 0, vgx2], { z0.s - z1.s }, z0.s + ADD ZA.s[W8, 0, VGx2], { Z0.s - Z1.s }, Z0.s + ADD ZA.S[W8, 0, VGX2], { Z0.S - Z1.S }, Z0.S + add za.s[w11, 0], { z0.s - z1.s }, z0.s + add za.s[w8, 7], { z0.s - z1.s }, z0.s + add za.s[w8, 0], { z30.s - z31.s }, z0.s + add za.s[w8, 0], { z31.s, z0.s }, z0.s + add za.s[w8, 0], { z31.s - z0.s }, z0.s + add za.s[w8, 0], { z0.s - z1.s }, z15.s + add za.s[w9, 5], { z9.s - z10.s }, z6.s + + add za.s[w8, 0], { z0.s - z3.s }, z0.s + add za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s + ADD ZA.s[W8, 0, VGx4], { Z0.s - Z3.s }, Z0.s + ADD ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, Z0.S + add za.s[w11, 0], { z0.s - z3.s }, z0.s + add za.s[w8, 7], { z0.s - z3.s }, z0.s + add za.s[w8, 0], { z28.s - z31.s }, z0.s + add za.s[w8, 0], { z31.s, z0.s, z1.s, z2.s }, z0.s + add za.s[w8, 0], { z31.s - z2.s }, z0.s + add za.s[w8, 0], { z0.s - z3.s }, z15.s + add za.s[w11, 2], { z23.s - z26.s }, z13.s + + add za.s[w8, 0], { z0.s - z1.s }, { z0.s - z1.s } + add za.s[w8, 0, vgx2], { z0.s - z1.s }, { z0.s - z1.s } + ADD ZA.s[W8, 0, VGx2], { Z0.s - Z1.s }, { Z0.s - Z1.s } + ADD ZA.S[W8, 0, VGX2], { Z0.S - Z1.S }, { Z0.S - Z1.S } + add za.s[w11, 0], { z0.s - z1.s }, { z0.s - z1.s } + add za.s[w8, 7], { z0.s - z1.s }, { z0.s - z1.s } + add za.s[w8, 0], { z30.s - z31.s }, { z0.s - z1.s } + add za.s[w8, 0], { z0.s - z1.s }, { z30.s - z31.s } + add za.s[w10, 1], { z22.s - z23.s }, { z18.s - z19.s } + + add za.s[w8, 0], { z0.s - z3.s }, { z0.s - z3.s } + add za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s } + ADD ZA.s[W8, 0, VGx4], { Z0.s - Z3.s }, { Z0.s - Z3.s } + ADD ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, { Z0.S - Z3.S } + add za.s[w11, 0], { z0.s - z3.s }, { z0.s - z3.s } + add za.s[w8, 7], { z0.s - z3.s }, { z0.s - z3.s } + add za.s[w8, 0], { z28.s - z31.s }, { z0.s - z3.s } + add za.s[w8, 0], { z0.s - z3.s }, { z28.s - z31.s } + add za.s[w11, 3], { z16.s - z19.s }, { z24.s - z27.s } + + add { z0.b - z1.b }, { z0.b - z1.b }, z0.b + add { z30.b - z31.b }, { z30.b - z31.b }, z0.b + add { z0.b - z1.b }, { z0.b - z1.b }, z15.b + add { z14.b - z15.b }, { z14.b - z15.b }, z5.b + + add { z0.h - z1.h }, { z0.h - z1.h }, z0.h + add { z30.h - z31.h }, { z30.h - z31.h }, z0.h + add { z0.h - z1.h }, { z0.h - z1.h }, z15.h + add { z20.h - z21.h }, { z20.h - z21.h }, z11.h + + add { z0.s - z1.s }, { z0.s - z1.s }, z0.s + add { z30.s - z31.s }, { z30.s - z31.s }, z0.s + add { z0.s - z1.s }, { z0.s - z1.s }, z15.s + add { z2.s - z3.s }, { z2.s - z3.s }, z9.s + + add { z0.d - z1.d }, { z0.d - z1.d }, z0.d + add { z30.d - z31.d }, { z30.d - z31.d }, z0.d + add { z0.d - z1.d }, { z0.d - z1.d }, z15.d + add { z28.d - z29.d }, { z28.d - z29.d }, z1.d + + add { z0.b - z3.b }, { z0.b - z3.b }, z0.b + add { z28.b - z31.b }, { z28.b - z31.b }, z0.b + add { z0.b - z3.b }, { z0.b - z3.b }, z15.b + add { z24.b - z27.b }, { z24.b - z27.b }, z5.b + + add { z0.h - z3.h }, { z0.h - z3.h }, z0.h + add { z28.h - z31.h }, { z28.h - z31.h }, z0.h + add { z0.h - z3.h }, { z0.h - z3.h }, z15.h + add { z20.h - z23.h }, { z20.h - z23.h }, z11.h + + add { z0.s - z3.s }, { z0.s - z3.s }, z0.s + add { z28.s - z31.s }, { z28.s - z31.s }, z0.s + add { z0.s - z3.s }, { z0.s - z3.s }, z15.s + add { z4.s - z7.s }, { z4.s - z7.s }, z9.s + + add { z0.d - z3.d }, { z0.d - z3.d }, z0.d + add { z28.d - z31.d }, { z28.d - z31.d }, z0.d + add { z0.d - z3.d }, { z0.d - z3.d }, z15.d + add { z16.d - z19.d }, { z16.d - z19.d }, z3.d + + sub za.s[w8, 0], { z0.s - z1.s } + sub za.s[w8, 0, vgx2], { z0.s - z1.s } + SUB ZA.s[W8, 0, VGx2], { Z0.s - Z1.s } + SUB ZA.S[W8, 0, VGX2], { Z0.S - Z1.S } + sub za.s[w11, 0], { z0.s - z1.s } + sub za.s[w8, 7], { z0.s - z1.s } + sub za.s[w8, 0], { z30.s - z31.s } + sub za.s[w10, 3], { z10.s - z11.s } + + sub za.s[w8, 0], { z0.s - z3.s } + sub za.s[w8, 0, vgx4], { z0.s - z3.s } + SUB ZA.s[W8, 0, VGx4], { Z0.s - Z3.s } + SUB ZA.S[W8, 0, VGX4], { Z0.S - Z3.S } + sub za.s[w11, 0], { z0.s - z3.s } + sub za.s[w8, 7], { z0.s - z3.s } + sub za.s[w8, 0], { z28.s - z31.s } + sub za.s[w11, 1], { z12.s - z15.s } + + sub za.s[w8, 0], { z0.s - z1.s }, z0.s + sub za.s[w8, 0, vgx2], { z0.s - z1.s }, z0.s + SUB ZA.s[W8, 0, VGx2], { Z0.s - Z1.s }, Z0.s + SUB ZA.S[W8, 0, VGX2], { Z0.S - Z1.S }, Z0.S + sub za.s[w11, 0], { z0.s - z1.s }, z0.s + sub za.s[w8, 7], { z0.s - z1.s }, z0.s + sub za.s[w8, 0], { z30.s - z31.s }, z0.s + sub za.s[w8, 0], { z31.s, z0.s }, z0.s + sub za.s[w8, 0], { z31.s - z0.s }, z0.s + sub za.s[w8, 0], { z0.s - z1.s }, z15.s + sub za.s[w9, 5], { z9.s - z10.s }, z6.s + + sub za.s[w8, 0], { z0.s - z3.s }, z0.s + sub za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s + SUB ZA.s[W8, 0, VGx4], { Z0.s - Z3.s }, Z0.s + SUB ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, Z0.S + sub za.s[w11, 0], { z0.s - z3.s }, z0.s + sub za.s[w8, 7], { z0.s - z3.s }, z0.s + sub za.s[w8, 0], { z28.s - z31.s }, z0.s + sub za.s[w8, 0], { z31.s, z0.s, z1.s, z2.s }, z0.s + sub za.s[w8, 0], { z31.s - z2.s }, z0.s + sub za.s[w8, 0], { z0.s - z3.s }, z15.s + sub za.s[w11, 2], { z23.s - z26.s }, z13.s + + sub za.s[w8, 0], { z0.s - z1.s }, { z0.s - z1.s } + sub za.s[w8, 0, vgx2], { z0.s - z1.s }, { z0.s - z1.s } + SUB ZA.s[W8, 0, VGx2], { Z0.s - Z1.s }, { Z0.s - Z1.s } + SUB ZA.S[W8, 0, VGX2], { Z0.S - Z1.S }, { Z0.S - Z1.S } + sub za.s[w11, 0], { z0.s - z1.s }, { z0.s - z1.s } + sub za.s[w8, 7], { z0.s - z1.s }, { z0.s - z1.s } + sub za.s[w8, 0], { z30.s - z31.s }, { z0.s - z1.s } + sub za.s[w8, 0], { z0.s - z1.s }, { z30.s - z31.s } + sub za.s[w10, 1], { z22.s - z23.s }, { z18.s - z19.s } + + sub za.s[w8, 0], { z0.s - z3.s }, { z0.s - z3.s } + sub za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s } + SUB ZA.s[W8, 0, VGx4], { Z0.s - Z3.s }, { Z0.s - Z3.s } + SUB ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, { Z0.S - Z3.S } + sub za.s[w11, 0], { z0.s - z3.s }, { z0.s - z3.s } + sub za.s[w8, 7], { z0.s - z3.s }, { z0.s - z3.s } + sub za.s[w8, 0], { z28.s - z31.s }, { z0.s - z3.s } + sub za.s[w8, 0], { z0.s - z3.s }, { z28.s - z31.s } + sub za.s[w11, 3], { z16.s - z19.s }, { z24.s - z27.s } + + fadd za.s[w8, 0], { z0.s - z1.s } + fadd za.s[w8, 0, vgx2], { z0.s - z1.s } + FADD ZA.s[W8, 0, VGx2], { Z0.s - Z1.s } + FADD ZA.S[W8, 0, VGX2], { Z0.S - Z1.S } + fadd za.s[w11, 0], { z0.s - z1.s } + fadd za.s[w8, 7], { z0.s - z1.s } + fadd za.s[w8, 0], { z30.s - z31.s } + fadd za.s[w10, 3], { z10.s - z11.s } + + fadd za.s[w8, 0], { z0.s - z3.s } + fadd za.s[w8, 0, vgx4], { z0.s - z3.s } + FADD ZA.s[W8, 0, VGx4], { Z0.s - Z3.s } + FADD ZA.S[W8, 0, VGX4], { Z0.S - Z3.S } + fadd za.s[w11, 0], { z0.s - z3.s } + fadd za.s[w8, 7], { z0.s - z3.s } + fadd za.s[w8, 0], { z28.s - z31.s } + fadd za.s[w11, 1], { z12.s - z15.s } + + fsub za.s[w8, 0], { z0.s - z1.s } + fsub za.s[w8, 0, vgx2], { z0.s - z1.s } + FSUB ZA.s[W8, 0, VGx2], { Z0.s - Z1.s } + FSUB ZA.S[W8, 0, VGX2], { Z0.S - Z1.S } + fsub za.s[w11, 0], { z0.s - z1.s } + fsub za.s[w8, 7], { z0.s - z1.s } + fsub za.s[w8, 0], { z30.s - z31.s } + fsub za.s[w10, 3], { z10.s - z11.s } + + fsub za.s[w8, 0], { z0.s - z3.s } + fsub za.s[w8, 0, vgx4], { z0.s - z3.s } + FSUB ZA.s[W8, 0, VGx4], { Z0.s - Z3.s } + FSUB ZA.S[W8, 0, VGX4], { Z0.S - Z3.S } + fsub za.s[w11, 0], { z0.s - z3.s } + fsub za.s[w8, 7], { z0.s - z3.s } + fsub za.s[w8, 0], { z28.s - z31.s } + fsub za.s[w11, 1], { z12.s - z15.s } diff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-1-invalid.d b/gas/testsu= ite/gas/aarch64/sme2-f64f64-1-invalid.d new file mode 100644 index 00000000000..f3a623dd9e8 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-f64f64-1-invalid.d @@ -0,0 +1,3 @@ +#as: -march=3Darmv8-a +#source: sme2-f64f64-1-invalid.s +#error_output: sme2-f64f64-1-invalid.l diff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-1-invalid.l b/gas/testsu= ite/gas/aarch64/sme2-f64f64-1-invalid.l new file mode 100644 index 00000000000..60ee8bd0f8e --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-f64f64-1-invalid.l @@ -0,0 +1,27 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at= operand 1 -- `fadd za\.d\[w7,0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at= operand 1 -- `fadd za\.d\[w12,0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 --= `fadd za\.d\[w8,-1\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 --= `fadd za\.d\[w8,8\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- = `fadd za\.d\[w8,0\],{z0\.d-z2\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fadd za= \.d\[w8,0\],{z1\.d-z2\.d}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at= operand 1 -- `fadd za\.d\[w7,0\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at= operand 1 -- `fadd za\.d\[w12,0\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 --= `fadd za\.d\[w8,-1\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 --= `fadd za\.d\[w8,8\],{z1\.d-z3\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fadd za= \.d\[w8,0\],{z1\.d-z4\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fadd za= \.d\[w8,0\],{z2\.d-z5\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fadd za= \.d\[w8,0\],{z3\.d-z6\.d}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `fadd= za\.d\[w8,0,vgx4\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `fadd= za\.d\[w8,0,vgx2\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: operand mismatch -- `fadd za\[w8,0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: fadd za\.d\[w8, 0\], {z0\.d-z1\.d} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: fadd za\.s\[w8, 0\], {z0\.s-z1\.s} +[^ :]+:[0-9]+: Error: missing type suffix at operand 2 -- `fadd za\.d\[w8,= 0\],{z0-z1}' +[^ :]+:[0-9]+: Error: operand mismatch -- `fadd za\.d\[w8,0\],{z0\.s-z1\.s= }' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: fadd za\.s\[w8, 0\], {z0\.s-z1\.s} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: fadd za\.d\[w8, 0\], {z0\.d-z1\.d} diff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-1-invalid.s b/gas/testsu= ite/gas/aarch64/sme2-f64f64-1-invalid.s new file mode 100644 index 00000000000..e045dcd984a --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-f64f64-1-invalid.s @@ -0,0 +1,20 @@ + fadd za.d[w7, 0], { z0.d - z1.d } + fadd za.d[w12, 0], { z0.d - z1.d } + fadd za.d[w8, -1], { z0.d - z1.d } + fadd za.d[w8, 8], { z0.d - z1.d } + fadd za.d[w8, 0], { z0.d - z2.d } + fadd za.d[w8, 0], { z1.d - z2.d } + + fadd za.d[w7, 0], { z0.d - z3.d } + fadd za.d[w12, 0], { z0.d - z3.d } + fadd za.d[w8, -1], { z0.d - z3.d } + fadd za.d[w8, 8], { z1.d - z3.d } + fadd za.d[w8, 0], { z1.d - z4.d } + fadd za.d[w8, 0], { z2.d - z5.d } + fadd za.d[w8, 0], { z3.d - z6.d } + + fadd za.d[w8, 0, vgx4], { z0.d - z1.d } + fadd za.d[w8, 0, vgx2], { z0.d - z3.d } + fadd za[w8, 0], { z0.d - z1.d } + fadd za.d[w8, 0], { z0 - z1 } + fadd za.d[w8, 0], { z0.s - z1.s } diff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-1-noarch.d b/gas/testsui= te/gas/aarch64/sme2-f64f64-1-noarch.d new file mode 100644 index 00000000000..fe14d018a2f --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-f64f64-1-noarch.d @@ -0,0 +1,3 @@ +#as: -march=3Darmv8-a+sme2 +#source: sme2-f64f64-1.s +#error_output: sme2-f64f64-1-noarch.l diff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-1-noarch.l b/gas/testsui= te/gas/aarch64/sme2-f64f64-1-noarch.l new file mode 100644 index 00000000000..f3750f5b171 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-f64f64-1-noarch.l @@ -0,0 +1,33 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w8,= 0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w8,= 0,vgx2\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd ZA\.d\[W8,= 0,VGx2\],{Z0\.d-Z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd ZA\.D\[W8,= 0,VGX2\],{Z0\.D-Z1\.D}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w11= ,0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w8,= 7\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w8,= 0\],{z30\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w10= ,3\],{z10\.d-z11\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w8,= 0\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w8,= 0,vgx4\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd ZA\.d\[W8,= 0,VGx4\],{Z0\.d-Z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd ZA\.D\[W8,= 0,VGX4\],{Z0\.D-Z3\.D}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w11= ,0\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w8,= 7\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w8,= 0\],{z28\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w11= ,1\],{z12\.d-z15\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w8,= 0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w8,= 0,vgx2\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub ZA\.d\[W8,= 0,VGx2\],{Z0\.d-Z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub ZA\.D\[W8,= 0,VGX2\],{Z0\.D-Z1\.D}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w11= ,0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w8,= 7\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w8,= 0\],{z30\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w10= ,3\],{z10\.d-z11\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w8,= 0\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w8,= 0,vgx4\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub ZA\.d\[W8,= 0,VGx4\],{Z0\.d-Z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub ZA\.D\[W8,= 0,VGX4\],{Z0\.D-Z3\.D}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w11= ,0\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w8,= 7\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w8,= 0\],{z28\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w11= ,1\],{z12\.d-z15\.d}' diff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-1.d b/gas/testsuite/gas/= aarch64/sme2-f64f64-1.d new file mode 100644 index 00000000000..3f3d167a4e8 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-f64f64-1.d @@ -0,0 +1,41 @@ +#as: -march=3Darmv8-a+sme2+sme-f64f64 +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +[^:]+: c1e01c00 fadd za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01c00 fadd za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01c00 fadd za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01c00 fadd za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e07c00 fadd za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01c07 fadd za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01fc0 fadd za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d} +[^:]+: c1e05d43 fadd za\.d\[w10, 3, vgx2\], {z10\.d-z11\.d} +[^:]+: c1e11c00 fadd za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11c00 fadd za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11c00 fadd za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11c00 fadd za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e17c00 fadd za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11c07 fadd za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11f80 fadd za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d} +[^:]+: c1e17d81 fadd za\.d\[w11, 1, vgx4\], {z12\.d-z15\.d} +[^:]+: c1e01c08 fsub za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01c08 fsub za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01c08 fsub za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01c08 fsub za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e07c08 fsub za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01c0f fsub za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01fc8 fsub za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d} +[^:]+: c1e05d4b fsub za\.d\[w10, 3, vgx2\], {z10\.d-z11\.d} +[^:]+: c1e11c08 fsub za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11c08 fsub za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11c08 fsub za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11c08 fsub za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e17c08 fsub za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11c0f fsub za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11f88 fsub za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d} +[^:]+: c1e17d89 fsub za\.d\[w11, 1, vgx4\], {z12\.d-z15\.d} diff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-1.s b/gas/testsuite/gas/= aarch64/sme2-f64f64-1.s new file mode 100644 index 00000000000..546f20dd44d --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-f64f64-1.s @@ -0,0 +1,35 @@ + fadd za.d[w8, 0], { z0.d - z1.d } + fadd za.d[w8, 0, vgx2], { z0.d - z1.d } + FADD ZA.d[W8, 0, VGx2], { Z0.d - Z1.d } + FADD ZA.D[W8, 0, VGX2], { Z0.D - Z1.D } + fadd za.d[w11, 0], { z0.d - z1.d } + fadd za.d[w8, 7], { z0.d - z1.d } + fadd za.d[w8, 0], { z30.d - z31.d } + fadd za.d[w10, 3], { z10.d - z11.d } + + fadd za.d[w8, 0], { z0.d - z3.d } + fadd za.d[w8, 0, vgx4], { z0.d - z3.d } + FADD ZA.d[W8, 0, VGx4], { Z0.d - Z3.d } + FADD ZA.D[W8, 0, VGX4], { Z0.D - Z3.D } + fadd za.d[w11, 0], { z0.d - z3.d } + fadd za.d[w8, 7], { z0.d - z3.d } + fadd za.d[w8, 0], { z28.d - z31.d } + fadd za.d[w11, 1], { z12.d - z15.d } + + fsub za.d[w8, 0], { z0.d - z1.d } + fsub za.d[w8, 0, vgx2], { z0.d - z1.d } + FSUB ZA.d[W8, 0, VGx2], { Z0.d - Z1.d } + FSUB ZA.D[W8, 0, VGX2], { Z0.D - Z1.D } + fsub za.d[w11, 0], { z0.d - z1.d } + fsub za.d[w8, 7], { z0.d - z1.d } + fsub za.d[w8, 0], { z30.d - z31.d } + fsub za.d[w10, 3], { z10.d - z11.d } + + fsub za.d[w8, 0], { z0.d - z3.d } + fsub za.d[w8, 0, vgx4], { z0.d - z3.d } + FSUB ZA.d[W8, 0, VGx4], { Z0.d - Z3.d } + FSUB ZA.D[W8, 0, VGX4], { Z0.D - Z3.D } + fsub za.d[w11, 0], { z0.d - z3.d } + fsub za.d[w8, 7], { z0.d - z3.d } + fsub za.d[w8, 0], { z28.d - z31.d } + fsub za.d[w11, 1], { z12.d - z15.d } diff --git a/gas/testsuite/gas/aarch64/sme2-i16i64-1-invalid.d b/gas/testsu= ite/gas/aarch64/sme2-i16i64-1-invalid.d new file mode 100644 index 00000000000..01172951481 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-i16i64-1-invalid.d @@ -0,0 +1,3 @@ +#as: -march=3Darmv8-a +#source: sme2-i16i64-1-invalid.s +#error_output: sme2-i16i64-1-invalid.l diff --git a/gas/testsuite/gas/aarch64/sme2-i16i64-1-invalid.l b/gas/testsu= ite/gas/aarch64/sme2-i16i64-1-invalid.l new file mode 100644 index 00000000000..d9d537a63d4 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-i16i64-1-invalid.l @@ -0,0 +1,111 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at= operand 1 -- `add za\.d\[w7,0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at= operand 1 -- `add za\.d\[w12,0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 --= `add za\.d\[w8,-1\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 --= `add za\.d\[w8,8\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- = `add za\.d\[w8,0\],{z0\.d-z2\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\= .d\[w8,0\],{z1\.d-z2\.d}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at= operand 1 -- `add za\.d\[w7,0\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at= operand 1 -- `add za\.d\[w12,0\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 --= `add za\.d\[w8,-1\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 --= `add za\.d\[w8,8\],{z1\.d-z3\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\= .d\[w8,0\],{z1\.d-z4\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\= .d\[w8,0\],{z2\.d-z5\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\= .d\[w8,0\],{z3\.d-z6\.d}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `add = za\.d\[w8,0,vgx4\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `add = za\.d\[w8,0,vgx2\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\[w8,0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s} +[^ :]+:[0-9]+: Error: missing type suffix at operand 2 -- `add za\.d\[w8,0= \],{z0-z1}' +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\.d\[w8,0\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d} +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at= operand 1 -- `add za\.d\[w0,0\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: expected a 32-bit selection register at operand 1 --= `add za\.d\[w31,0\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 --= `add za\.d\[w8,1<<63\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `add za\.d\[w8,0\],{= z0\.d-z1\.d},z31\.d' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at= operand 1 -- `add za\.d\[w7,0\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at= operand 1 -- `add za\.d\[w12,0\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 --= `add za\.d\[w8,-1\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 --= `add za\.d\[w8,8\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `add za\.d\[w8,0\],{= z0\.d-z1\.d},z16\.d' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at= operand 1 -- `add za\.d\[w7,0\],{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at= operand 1 -- `add za\.d\[w12,0\],{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 --= `add za\.d\[w8,-1\],{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 --= `add za\.d\[w8,8\],{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `add za\.d\[w8,0\],{= z0\.d-z3\.d},z16\.d' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- = `add za\.d\[w8,0\],{z0\.d-z2\.d},z0\.d' +[^ :]+:[0-9]+: Error: too many registers in vector register list at operan= d 2 -- `add za\.d\[w8,0\],{z0\.d-z4\.d},z0\.d' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- = `add za\.d\[w8,0\],{z0\.d,z1\.d,z2\.d},z0\.d' +[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `add za\.d\[w8= ,0\],{z0\.d,z1\.d,z5\.d},z0\.d' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `add = za\.d\[w8,0,vgx4\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `add = za\.d\[w8,0,vgx2\],{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\[w8,0\],{z0\.d-z1\.d},z0= \.d' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s +[^ :]+:[0-9]+: Error: missing type suffix at operand 2 -- `add za\.d\[w8,0= \],{z0-z1},z0\.d' +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\.d\[w8,0\],{z0\.d-z1\.d}= ,z0' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\[w8,0\],{z0\.d-z1\.d},z0' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\.s\[w8,0\],{z0\.d-z1\.d}= ,z0\.s' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\.d\[w8,0\],{z0\.s-z1\.s}= ,z0\.d' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at= operand 1 -- `add za\.d\[w0,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a 32-bit selection register at operand 1 --= `add za\.d\[w31,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 --= `add za\.d\[w8,1<<63\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at= operand 1 -- `add za\.d\[w7,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at= operand 1 -- `add za\.d\[w12,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 --= `add za\.d\[w8,-1\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 --= `add za\.d\[w8,8\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 --= `add za\.d\[w8,8\],{z1\.d-z2\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `add za\= .d\[w8,0\],{z0\.d-z1\.d},{z15\.d-z16\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `add za\= .d\[w8,0\],{z0\.d-z1\.d},{z31\.d,z0\.d}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at= operand 1 -- `add za\.d\[w7,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at= operand 1 -- `add za\.d\[w12,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 --= `add za\.d\[w8,-1\],{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 --= `add za\.d\[w8,8\],{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\= .d\[w8,0\],{z1\.d-z4\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\= .d\[w8,0\],{z2\.d-z5\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\= .d\[w8,0\],{z3\.d-z6\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `add za\= .d\[w8,0\],{z0\.d-z3\.d},{z15\.d-z18\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `add za\= .d\[w8,0\],{z0\.d-z3\.d},{z29\.d,z30\.d,z31\.d,z0\.d}' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- = `add za\.d\[w8,0\],{z0\.d-z2\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `add = za\.d\[w8,0\],{z0\.d-z3\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `add = za\.d\[w8,0\],{z0\.d-z1\.d},{z0\.d-z2\.d}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `add = za\.d\[w8,0\],{z0\.d-z1\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: too many registers in vector register list at operan= d 3 -- `add za\.d\[w8,0\],{z0\.d-z1\.d},{z0\.d-z4\.d}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `add = za\.d\[w8,0,vgx4\],{z0\.d-z1\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `add = za\.d\[w8,0,vgx4\],{z0\.d-z3\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `add = za\.d\[w8,0,vgx2\],{z0\.d-z1\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `add = za\.d\[w8,0,vgx2\],{z0\.d-z3\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\[w8,0\],{z0\.d-z1\.d},{z= 0\.d-z1\.d}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\[w8,0\],{z0\.d-z3\.d},{z= 0\.d-z3\.d}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z3\.s}, {z0\.s-z3\.s} diff --git a/gas/testsuite/gas/aarch64/sme2-i16i64-1-invalid.s b/gas/testsu= ite/gas/aarch64/sme2-i16i64-1-invalid.s new file mode 100644 index 00000000000..ef2e48d2477 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-i16i64-1-invalid.s @@ -0,0 +1,86 @@ + add za.d[w7, 0], { z0.d - z1.d } + add za.d[w12, 0], { z0.d - z1.d } + add za.d[w8, -1], { z0.d - z1.d } + add za.d[w8, 8], { z0.d - z1.d } + add za.d[w8, 0], { z0.d - z2.d } + add za.d[w8, 0], { z1.d - z2.d } + + add za.d[w7, 0], { z0.d - z3.d } + add za.d[w12, 0], { z0.d - z3.d } + add za.d[w8, -1], { z0.d - z3.d } + add za.d[w8, 8], { z1.d - z3.d } + add za.d[w8, 0], { z1.d - z4.d } + add za.d[w8, 0], { z2.d - z5.d } + add za.d[w8, 0], { z3.d - z6.d } + + add za.d[w8, 0, vgx4], { z0.d - z1.d } + add za.d[w8, 0, vgx2], { z0.d - z3.d } + add za[w8, 0], { z0.d - z1.d } + add za.d[w8, 0], { z0 - z1 } + add za.d[w8, 0], { z0.s - z1.s } + + add za.d[w0, 0], { z0.d - z1.d }, z0.d + add za.d[w31, 0], { z0.d - z1.d }, z0.d + add za.d[w8, 1<<63], { z0.d - z1.d }, z0.d + add za.d[w8, 0], { z0.d - z1.d }, z31.d + + add za.d[w7, 0], { z0.d - z1.d }, z0.d + add za.d[w12, 0], { z0.d - z1.d }, z0.d + add za.d[w8, -1], { z0.d - z1.d }, z0.d + add za.d[w8, 8], { z0.d - z1.d }, z0.d + add za.d[w8, 0], { z0.d - z1.d }, z16.d + + add za.d[w7, 0], { z0.d - z3.d }, z0.d + add za.d[w12, 0], { z0.d - z3.d }, z0.d + add za.d[w8, -1], { z0.d - z3.d }, z0.d + add za.d[w8, 8], { z0.d - z3.d }, z0.d + add za.d[w8, 0], { z0.d - z3.d }, z16.d + + add za.d[w8, 0], { z0.d - z2.d }, z0.d + add za.d[w8, 0], { z0.d - z4.d }, z0.d + add za.d[w8, 0], { z0.d, z1.d, z2.d }, z0.d + add za.d[w8, 0], { z0.d, z1.d, z5.d }, z0.d + + add za.d[w8, 0, vgx4], { z0.d - z1.d }, z0.d + add za.d[w8, 0, vgx2], { z0.d - z3.d }, z0.d + add za[w8, 0], { z0.d - z1.d }, z0.d + add za.d[w8, 0], { z0 - z1 }, z0.d + add za.d[w8, 0], { z0.d - z1.d }, z0 + add za[w8, 0], { z0.d - z1.d }, z0 + add za.s[w8, 0], { z0.d - z1.d }, z0.s + add za.d[w8, 0], { z0.s - z1.s }, z0.d + + add za.d[w0, 0], { z0.d - z1.d }, { z0.d - z1.d } + add za.d[w31, 0], { z0.d - z1.d }, { z0.d - z1.d } + add za.d[w8, 1<<63], { z0.d - z1.d }, { z0.d - z1.d } + + add za.d[w7, 0], { z0.d - z1.d }, { z0.d - z1.d } + add za.d[w12, 0], { z0.d - z1.d }, { z0.d - z1.d } + add za.d[w8, -1], { z0.d - z1.d }, { z0.d - z1.d } + add za.d[w8, 8], { z0.d - z1.d }, { z0.d - z1.d } + add za.d[w8, 8], { z1.d - z2.d }, { z0.d - z1.d } + add za.d[w8, 0], { z0.d - z1.d }, { z15.d - z16.d } + add za.d[w8, 0], { z0.d - z1.d }, { z31.d, z0.d } + + add za.d[w7, 0], { z0.d - z3.d }, { z0.d - z3.d } + add za.d[w12, 0], { z0.d - z3.d }, { z0.d - z3.d } + add za.d[w8, -1], { z0.d - z3.d }, { z0.d - z3.d } + add za.d[w8, 8], { z0.d - z3.d }, { z0.d - z3.d } + add za.d[w8, 0], { z1.d - z4.d }, { z0.d - z3.d } + add za.d[w8, 0], { z2.d - z5.d }, { z0.d - z3.d } + add za.d[w8, 0], { z3.d - z6.d }, { z0.d - z3.d } + add za.d[w8, 0], { z0.d - z3.d }, { z15.d - z18.d } + add za.d[w8, 0], { z0.d - z3.d }, { z29.d, z30.d, z31.d, z0.d } + + add za.d[w8, 0], { z0.d - z2.d }, { z0.d - z1.d } + add za.d[w8, 0], { z0.d - z3.d }, { z0.d - z1.d } + add za.d[w8, 0], { z0.d - z1.d }, { z0.d - z2.d } + add za.d[w8, 0], { z0.d - z1.d }, { z0.d - z3.d } + add za.d[w8, 0], { z0.d - z1.d }, { z0.d - z4.d } + + add za.d[w8, 0, vgx4], { z0.d - z1.d }, { z0.d - z3.d } + add za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z1.d } + add za.d[w8, 0, vgx2], { z0.d - z1.d }, { z0.d - z3.d } + add za.d[w8, 0, vgx2], { z0.d - z3.d }, { z0.d - z1.d } + add za[w8, 0], { z0.d - z1.d }, { z0.d - z1.d } + add za[w8, 0], { z0.d - z3.d }, { z0.d - z3.d } diff --git a/gas/testsuite/gas/aarch64/sme2-i16i64-1-noarch.d b/gas/testsui= te/gas/aarch64/sme2-i16i64-1-noarch.d new file mode 100644 index 00000000000..fe924efd561 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-i16i64-1-noarch.d @@ -0,0 +1,3 @@ +#as: -march=3Darmv8-a+sme2 +#source: sme2-i16i64-1.s +#error_output: sme2-i16i64-1-noarch.l diff --git a/gas/testsuite/gas/aarch64/sme2-i16i64-1-noarch.l b/gas/testsui= te/gas/aarch64/sme2-i16i64-1-noarch.l new file mode 100644 index 00000000000..bbdccc7ac63 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-i16i64-1-noarch.l @@ -0,0 +1,57 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0= \],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0= ,vgx2\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.d\[W8,0= ,VGx2\],{Z0\.d-Z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.D\[W8,0= ,VGX2\],{Z0\.D-Z1\.D}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w11,= 0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,7= \],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0= \],{z30\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w10,= 3\],{z10\.d-z11\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0= \],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0= ,vgx4\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.d\[W8,0= ,VGx4\],{Z0\.d-Z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.D\[W8,0= ,VGX4\],{Z0\.D-Z3\.D}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w11,= 0\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,7= \],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0= \],{z28\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w11,= 1\],{z12\.d-z15\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0= \],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0= ,vgx2\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.d\[W8,0= ,VGx2\],{Z0\.d-Z1\.d},Z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.D\[W8,0= ,VGX2\],{Z0\.D-Z1\.D},Z0\.D' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w11,= 0\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,7= \],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0= \],{z30\.d-z31\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0= \],{z31\.d,z0\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0= \],{z31\.d-z0\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0= \],{z0\.d-z1\.d},z15\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w9,5= \],{z9\.d-z10\.d},z6\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0= \],{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0= ,vgx4\],{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.d\[W8,0= ,VGx4\],{Z0\.d-Z3\.d},Z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.D\[W8,0= ,VGX4\],{Z0\.D-Z3\.D},Z0\.D' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w11,= 0\],{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,7= \],{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0= \],{z28\.d-z31\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0= \],{z31\.d,z0\.d,z1\.d,z2\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0= \],{z31\.d-z2\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0= \],{z0\.d-z3\.d},z15\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w11,= 2\],{z23\.d-z26\.d},z13\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0= \],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0= ,vgx2\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.d\[W8,0= ,VGx2\],{Z0\.d-Z1\.d},{Z0\.d-Z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.D\[W8,0= ,VGX2\],{Z0\.D-Z1\.D},{Z0\.D-Z1\.D}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w11,= 0\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,7= \],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0= \],{z30\.d-z31\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0= \],{z0\.d-z1\.d},{z30\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w10,= 1\],{z22\.d-z23\.d},{z18\.d-z19\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0= \],{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0= ,vgx4\],{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.d\[W8,0= ,VGx4\],{Z0\.d-Z3\.d},{Z0\.d-Z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.D\[W8,0= ,VGX4\],{Z0\.D-Z3\.D},{Z0\.D-Z3\.D}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w11,= 0\],{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,7= \],{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0= \],{z28\.d-z31\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0= \],{z0\.d-z3\.d},{z28\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w11,= 3\],{z16\.d-z19\.d},{z24\.d-z27\.d}' diff --git a/gas/testsuite/gas/aarch64/sme2-i16i64-1.d b/gas/testsuite/gas/= aarch64/sme2-i16i64-1.d new file mode 100644 index 00000000000..8b95f5d3974 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-i16i64-1.d @@ -0,0 +1,65 @@ +#as: -march=3Darmv8-a+sme2+sme-i16i64 +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +[^:]+: c1e01c10 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01c10 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01c10 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01c10 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e07c10 add za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01c17 add za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01fd0 add za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d} +[^:]+: c1e05d53 add za\.d\[w10, 3, vgx2\], {z10\.d-z11\.d} +[^:]+: c1e11c10 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11c10 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11c10 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11c10 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e17c10 add za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11c17 add za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11f90 add za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d} +[^:]+: c1e17d91 add za\.d\[w11, 1, vgx4\], {z12\.d-z15\.d} +[^:]+: c1601810 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d +[^:]+: c1601810 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d +[^:]+: c1601810 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d +[^:]+: c1601810 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d +[^:]+: c1607810 add za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d}, z0\.d +[^:]+: c1601817 add za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d}, z0\.d +[^:]+: c1601bd0 add za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d}, z0\.d +[^:]+: c1601bf0 add za\.d\[w8, 0, vgx2\], {z31\.d-z0\.d}, z0\.d +[^:]+: c1601bf0 add za\.d\[w8, 0, vgx2\], {z31\.d-z0\.d}, z0\.d +[^:]+: c16f1810 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z15\.d +[^:]+: c1663935 add za\.d\[w9, 5, vgx2\], {z9\.d-z10\.d}, z6\.d +[^:]+: c1701810 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d +[^:]+: c1701810 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d +[^:]+: c1701810 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d +[^:]+: c1701810 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d +[^:]+: c1707810 add za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d}, z0\.d +[^:]+: c1701817 add za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d}, z0\.d +[^:]+: c1701b90 add za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d}, z0\.d +[^:]+: c1701bf0 add za\.d\[w8, 0, vgx4\], {z31\.d-z2\.d}, z0\.d +[^:]+: c1701bf0 add za\.d\[w8, 0, vgx4\], {z31\.d-z2\.d}, z0\.d +[^:]+: c17f1810 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z15\.d +[^:]+: c17d7af2 add za\.d\[w11, 2, vgx4\], {z23\.d-z26\.d}, z13\.d +[^:]+: c1e01810 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^:]+: c1e01810 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^:]+: c1e01810 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^:]+: c1e01810 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^:]+: c1e07810 add za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^:]+: c1e01817 add za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^:]+: c1e01bd0 add za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d}, {z0\.d-z1\.d} +[^:]+: c1fe1810 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z30\.d-z31\.d} +[^:]+: c1f25ad1 add za\.d\[w10, 1, vgx2\], {z22\.d-z23\.d}, {z18\.d-z19\.= d} +[^:]+: c1e11810 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^:]+: c1e11810 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^:]+: c1e11810 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^:]+: c1e11810 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^:]+: c1e17810 add za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^:]+: c1e11817 add za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^:]+: c1e11b90 add za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d}, {z0\.d-z3\.d} +[^:]+: c1fd1810 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z28\.d-z31\.d} +[^:]+: c1f97a13 add za\.d\[w11, 3, vgx4\], {z16\.d-z19\.d}, {z24\.d-z27\.= d} diff --git a/gas/testsuite/gas/aarch64/sme2-i16i64-1.s b/gas/testsuite/gas/= aarch64/sme2-i16i64-1.s new file mode 100644 index 00000000000..537669a1b93 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-i16i64-1.s @@ -0,0 +1,61 @@ + add za.d[w8, 0], { z0.d - z1.d } + add za.d[w8, 0, vgx2], { z0.d - z1.d } + ADD ZA.d[W8, 0, VGx2], { Z0.d - Z1.d } + ADD ZA.D[W8, 0, VGX2], { Z0.D - Z1.D } + add za.d[w11, 0], { z0.d - z1.d } + add za.d[w8, 7], { z0.d - z1.d } + add za.d[w8, 0], { z30.d - z31.d } + add za.d[w10, 3], { z10.d - z11.d } + + add za.d[w8, 0], { z0.d - z3.d } + add za.d[w8, 0, vgx4], { z0.d - z3.d } + ADD ZA.d[W8, 0, VGx4], { Z0.d - Z3.d } + ADD ZA.D[W8, 0, VGX4], { Z0.D - Z3.D } + add za.d[w11, 0], { z0.d - z3.d } + add za.d[w8, 7], { z0.d - z3.d } + add za.d[w8, 0], { z28.d - z31.d } + add za.d[w11, 1], { z12.d - z15.d } + + add za.d[w8, 0], { z0.d - z1.d }, z0.d + add za.d[w8, 0, vgx2], { z0.d - z1.d }, z0.d + ADD ZA.d[W8, 0, VGx2], { Z0.d - Z1.d }, Z0.d + ADD ZA.D[W8, 0, VGX2], { Z0.D - Z1[...] [diff truncated at 100000 bytes]