From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1130) id A6433385842B; Thu, 30 Mar 2023 10:16:09 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A6433385842B Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Richard Sandiford To: bfd-cvs@sourceware.org Subject: [binutils-gdb] aarch64: Add the SME2 saturating conversion instructions X-Act-Checkin: binutils-gdb X-Git-Author: Richard Sandiford X-Git-Refname: refs/heads/master X-Git-Oldrev: c04965ec7d8819448f7d7b48cee9fa6567e67455 X-Git-Newrev: ce623e7aa486d1330c9a4529c77a302d2fdcb801 Message-Id: <20230330101609.A6433385842B@sourceware.org> Date: Thu, 30 Mar 2023 10:16:09 +0000 (GMT) X-BeenThere: binutils-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 30 Mar 2023 10:16:09 -0000 https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3Dce623e7aa486= d1330c9a4529c77a302d2fdcb801 commit ce623e7aa486d1330c9a4529c77a302d2fdcb801 Author: Richard Sandiford Date: Thu Mar 30 11:09:16 2023 +0100 aarch64: Add the SME2 saturating conversion instructions =20 There are two instruction formats here: =20 - SQCVT, SQCVTU and UQCVT, which operate on lists of two or four registers. =20 - SQCVTN, SQCVTUN and UQCVTN, which operate on lists of four registers. Diff: --- gas/testsuite/gas/aarch64/sme2-25-invalid.d | 3 + gas/testsuite/gas/aarch64/sme2-25-invalid.l | 48 ++ gas/testsuite/gas/aarch64/sme2-25-invalid.s | 28 + gas/testsuite/gas/aarch64/sme2-25-noarch.d | 3 + gas/testsuite/gas/aarch64/sme2-25-noarch.l | 37 + gas/testsuite/gas/aarch64/sme2-25.d | 45 ++ gas/testsuite/gas/aarch64/sme2-25.s | 44 ++ gas/testsuite/gas/aarch64/sme2-26-invalid.d | 3 + gas/testsuite/gas/aarch64/sme2-26-invalid.l | 13 + gas/testsuite/gas/aarch64/sme2-26-invalid.s | 14 + gas/testsuite/gas/aarch64/sme2-26-noarch.d | 3 + gas/testsuite/gas/aarch64/sme2-26-noarch.l | 25 + gas/testsuite/gas/aarch64/sme2-26.d | 33 + gas/testsuite/gas/aarch64/sme2-26.s | 29 + include/opcode/aarch64.h | 1 + opcodes/aarch64-asm.c | 5 + opcodes/aarch64-dis-2.c | 1035 +++++++++++++++--------= ---- opcodes/aarch64-dis.c | 4 + opcodes/aarch64-opc.c | 1 + opcodes/aarch64-opc.h | 1 + opcodes/aarch64-tbl.h | 14 + 21 files changed, 921 insertions(+), 468 deletions(-) diff --git a/gas/testsuite/gas/aarch64/sme2-25-invalid.d b/gas/testsuite/ga= s/aarch64/sme2-25-invalid.d new file mode 100644 index 00000000000..62b23cd19a7 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-25-invalid.d @@ -0,0 +1,3 @@ +#as: -march=3Darmv8-a +#source: sme2-25-invalid.s +#error_output: sme2-25-invalid.l diff --git a/gas/testsuite/gas/aarch64/sme2-25-invalid.l b/gas/testsuite/ga= s/aarch64/sme2-25-invalid.l new file mode 100644 index 00000000000..5b18a2ac99c --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-25-invalid.l @@ -0,0 +1,48 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqc= vt 0,{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected '{' at operand 2 -- `sqcvt z0\.h,0' +[^ :]+:[0-9]+: Error: operand mismatch -- `sqcvt z0\.s,{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: sqcvt z0\.b, {z0\.s-z1\.s} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: sqcvt z0\.h, {z0\.d-z1\.d} +[^ :]+:[0-9]+: Error: operand mismatch -- `sqcvt z0\.b,{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: sqcvt z0\.b, {z0\.s-z1\.s} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: sqcvt z0\.h, {z0\.d-z1\.d} +[^ :]+:[0-9]+: Error: operand mismatch -- `sqcvt z0\.s,{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: sqcvt z0\.h, {z0\.d-z1\.d} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: sqcvt z0\.b, {z0\.s-z1\.s} +[^ :]+:[0-9]+: Error: operand mismatch -- `sqcvt z0\.s,{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: sqcvt z0\.b, {z0\.s-z3\.s} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: sqcvt z0\.h, {z0\.d-z3\.d} +[^ :]+:[0-9]+: Error: operand mismatch -- `sqcvt z0\.b,{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: sqcvt z0\.b, {z0\.s-z3\.s} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: sqcvt z0\.h, {z0\.d-z3\.d} +[^ :]+:[0-9]+: Error: operand mismatch -- `sqcvt z0\.s,{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: sqcvt z0\.h, {z0\.d-z3\.d} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: sqcvt z0\.b, {z0\.s-z3\.s} +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `sqcv= t z0\.h,{z0\.s-z2\.s}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `sqcv= t z0\.h,{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: the register list must have a stride of 1 at operand= 2 -- `sqcvt z0\.h,{z0\.s,z8\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvt z= 0\.h,{z1\.s-z2\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvt z= 0\.h,{z31\.s,z0\.s}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `sqcv= t z0\.b,{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `sqcv= t z0\.b,{z0\.s-z2\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvt z= 0\.b,{z1\.s-z4\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvt z= 0\.b,{z2\.s-z5\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvt z= 0\.b,{z3\.s-z6\.s}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `sqcv= t z0\.h,{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `sqcv= t z0\.h,{z0\.d-z2\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvt z= 0\.h,{z1\.d-z4\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvt z= 0\.h,{z2\.d-z5\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvt z= 0\.h,{z3\.d-z6\.d}' diff --git a/gas/testsuite/gas/aarch64/sme2-25-invalid.s b/gas/testsuite/ga= s/aarch64/sme2-25-invalid.s new file mode 100644 index 00000000000..10395f75c40 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-25-invalid.s @@ -0,0 +1,28 @@ + sqcvt 0, { z0.s - z1.s } + sqcvt z0.h, 0 + + sqcvt z0.s, { z0.s - z1.s } + sqcvt z0.b, { z0.d - z1.d } + sqcvt z0.s, { z0.d - z1.d } + + sqcvt z0.s, { z0.s - z3.s } + sqcvt z0.b, { z0.d - z3.d } + sqcvt z0.s, { z0.d - z3.d } + + sqcvt z0.h, { z0.s - z2.s } + sqcvt z0.h, { z0.s - z3.s } + sqcvt z0.h, { z0.s, z8.s } + sqcvt z0.h, { z1.s - z2.s } + sqcvt z0.h, { z31.s, z0.s } + + sqcvt z0.b, { z0.s - z1.s } + sqcvt z0.b, { z0.s - z2.s } + sqcvt z0.b, { z1.s - z4.s } + sqcvt z0.b, { z2.s - z5.s } + sqcvt z0.b, { z3.s - z6.s } + + sqcvt z0.h, { z0.d - z1.d } + sqcvt z0.h, { z0.d - z2.d } + sqcvt z0.h, { z1.d - z4.d } + sqcvt z0.h, { z2.d - z5.d } + sqcvt z0.h, { z3.d - z6.d } diff --git a/gas/testsuite/gas/aarch64/sme2-25-noarch.d b/gas/testsuite/gas= /aarch64/sme2-25-noarch.d new file mode 100644 index 00000000000..e1e9d3968c8 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-25-noarch.d @@ -0,0 +1,3 @@ +#as: -march=3Darmv8-a+sme +#source: sme2-25.s +#error_output: sme2-25-noarch.l diff --git a/gas/testsuite/gas/aarch64/sme2-25-noarch.l b/gas/testsuite/gas= /aarch64/sme2-25-noarch.l new file mode 100644 index 00000000000..66998fffd32 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-25-noarch.l @@ -0,0 +1,37 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z0\.h,{z0= \.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z31\.h,{z= 0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z0\.h,{z3= 0\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z19\.h,{z= 14\.s-z15\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z0\.b,{z0= \.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z31\.b,{z= 0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z0\.b,{z2= 8\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z11\.b,{z= 20\.s-z23\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z0\.h,{z0= \.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z31\.h,{z= 0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z0\.h,{z2= 8\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z22\.h,{z= 4\.d-z7\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z0\.h,{z= 0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z31\.h,{= z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z0\.h,{z= 30\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z19\.h,{= z14\.s-z15\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z0\.b,{z= 0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z31\.b,{= z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z0\.b,{z= 28\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z11\.b,{= z20\.s-z23\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z0\.h,{z= 0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z31\.h,{= z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z0\.h,{z= 28\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z22\.h,{= z4\.d-z7\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z0\.h,{z0= \.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z31\.h,{z= 0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z0\.h,{z3= 0\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z19\.h,{z= 14\.s-z15\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z0\.b,{z0= \.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z31\.b,{z= 0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z0\.b,{z2= 8\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z11\.b,{z= 20\.s-z23\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z0\.h,{z0= \.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z31\.h,{z= 0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z0\.h,{z2= 8\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z22\.h,{z= 4\.d-z7\.d}' diff --git a/gas/testsuite/gas/aarch64/sme2-25.d b/gas/testsuite/gas/aarch6= 4/sme2-25.d new file mode 100644 index 00000000000..b2fdce756c3 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-25.d @@ -0,0 +1,45 @@ +#as: -march=3Darmv8-a+sme2 +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +[^:]+: c123e000 sqcvt z0\.h, {z0\.s-z1\.s} +[^:]+: c123e01f sqcvt z31\.h, {z0\.s-z1\.s} +[^:]+: c123e3c0 sqcvt z0\.h, {z30\.s-z31\.s} +[^:]+: c123e1d3 sqcvt z19\.h, {z14\.s-z15\.s} +[^:]+: c133e000 sqcvt z0\.b, {z0\.s-z3\.s} +[^:]+: c133e01f sqcvt z31\.b, {z0\.s-z3\.s} +[^:]+: c133e380 sqcvt z0\.b, {z28\.s-z31\.s} +[^:]+: c133e28b sqcvt z11\.b, {z20\.s-z23\.s} +[^:]+: c1b3e000 sqcvt z0\.h, {z0\.d-z3\.d} +[^:]+: c1b3e01f sqcvt z31\.h, {z0\.d-z3\.d} +[^:]+: c1b3e380 sqcvt z0\.h, {z28\.d-z31\.d} +[^:]+: c1b3e096 sqcvt z22\.h, {z4\.d-z7\.d} +[^:]+: c163e000 sqcvtu z0\.h, {z0\.s-z1\.s} +[^:]+: c163e01f sqcvtu z31\.h, {z0\.s-z1\.s} +[^:]+: c163e3c0 sqcvtu z0\.h, {z30\.s-z31\.s} +[^:]+: c163e1d3 sqcvtu z19\.h, {z14\.s-z15\.s} +[^:]+: c173e000 sqcvtu z0\.b, {z0\.s-z3\.s} +[^:]+: c173e01f sqcvtu z31\.b, {z0\.s-z3\.s} +[^:]+: c173e380 sqcvtu z0\.b, {z28\.s-z31\.s} +[^:]+: c173e28b sqcvtu z11\.b, {z20\.s-z23\.s} +[^:]+: c1f3e000 sqcvtu z0\.h, {z0\.d-z3\.d} +[^:]+: c1f3e01f sqcvtu z31\.h, {z0\.d-z3\.d} +[^:]+: c1f3e380 sqcvtu z0\.h, {z28\.d-z31\.d} +[^:]+: c1f3e096 sqcvtu z22\.h, {z4\.d-z7\.d} +[^:]+: c123e020 uqcvt z0\.h, {z0\.s-z1\.s} +[^:]+: c123e03f uqcvt z31\.h, {z0\.s-z1\.s} +[^:]+: c123e3e0 uqcvt z0\.h, {z30\.s-z31\.s} +[^:]+: c123e1f3 uqcvt z19\.h, {z14\.s-z15\.s} +[^:]+: c133e020 uqcvt z0\.b, {z0\.s-z3\.s} +[^:]+: c133e03f uqcvt z31\.b, {z0\.s-z3\.s} +[^:]+: c133e3a0 uqcvt z0\.b, {z28\.s-z31\.s} +[^:]+: c133e2ab uqcvt z11\.b, {z20\.s-z23\.s} +[^:]+: c1b3e020 uqcvt z0\.h, {z0\.d-z3\.d} +[^:]+: c1b3e03f uqcvt z31\.h, {z0\.d-z3\.d} +[^:]+: c1b3e3a0 uqcvt z0\.h, {z28\.d-z31\.d} +[^:]+: c1b3e0b6 uqcvt z22\.h, {z4\.d-z7\.d} diff --git a/gas/testsuite/gas/aarch64/sme2-25.s b/gas/testsuite/gas/aarch6= 4/sme2-25.s new file mode 100644 index 00000000000..45a2a70b021 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-25.s @@ -0,0 +1,44 @@ + sqcvt z0.h, { z0.s - z1.s } + sqcvt z31.h, { z0.s - z1.s } + sqcvt z0.h, { z30.s - z31.s } + sqcvt z19.h, { z14.s - z15.s } + + sqcvt z0.b, { z0.s - z3.s } + sqcvt z31.b, { z0.s - z3.s } + sqcvt z0.b, { z28.s - z31.s } + sqcvt z11.b, { z20.s - z23.s } + + sqcvt z0.h, { z0.d - z3.d } + sqcvt z31.h, { z0.d - z3.d } + sqcvt z0.h, { z28.d - z31.d } + sqcvt z22.h, { z4.d - z7.d } + + sqcvtu z0.h, { z0.s - z1.s } + sqcvtu z31.h, { z0.s - z1.s } + sqcvtu z0.h, { z30.s - z31.s } + sqcvtu z19.h, { z14.s - z15.s } + + sqcvtu z0.b, { z0.s - z3.s } + sqcvtu z31.b, { z0.s - z3.s } + sqcvtu z0.b, { z28.s - z31.s } + sqcvtu z11.b, { z20.s - z23.s } + + sqcvtu z0.h, { z0.d - z3.d } + sqcvtu z31.h, { z0.d - z3.d } + sqcvtu z0.h, { z28.d - z31.d } + sqcvtu z22.h, { z4.d - z7.d } + + uqcvt z0.h, { z0.s - z1.s } + uqcvt z31.h, { z0.s - z1.s } + uqcvt z0.h, { z30.s - z31.s } + uqcvt z19.h, { z14.s - z15.s } + + uqcvt z0.b, { z0.s - z3.s } + uqcvt z31.b, { z0.s - z3.s } + uqcvt z0.b, { z28.s - z31.s } + uqcvt z11.b, { z20.s - z23.s } + + uqcvt z0.h, { z0.d - z3.d } + uqcvt z31.h, { z0.d - z3.d } + uqcvt z0.h, { z28.d - z31.d } + uqcvt z22.h, { z4.d - z7.d } diff --git a/gas/testsuite/gas/aarch64/sme2-26-invalid.d b/gas/testsuite/ga= s/aarch64/sme2-26-invalid.d new file mode 100644 index 00000000000..5e336bf0905 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-26-invalid.d @@ -0,0 +1,3 @@ +#as: -march=3Darmv8-a +#source: sme2-26-invalid.s +#error_output: sme2-26-invalid.l diff --git a/gas/testsuite/gas/aarch64/sme2-26-invalid.l b/gas/testsuite/ga= s/aarch64/sme2-26-invalid.l new file mode 100644 index 00000000000..08c2f7fc7af --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-26-invalid.l @@ -0,0 +1,13 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqc= vtn 0,{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: expected '{' at operand 2 -- `sqcvtn z0\.b,0' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `sqcv= tn z0\.b,{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `sqcv= tn z0\.b,{z0\.s-z2\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvtn = z0\.b,{z1\.s-z4\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvtn = z0\.b,{z2\.s-z5\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvtn = z0\.b,{z3\.s-z6\.s}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `sqcv= tn z0\.h,{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `sqcv= tn z0\.h,{z0\.d-z2\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvtn = z0\.h,{z1\.d-z4\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvtn = z0\.h,{z2\.d-z5\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvtn = z0\.h,{z3\.d-z6\.d}' diff --git a/gas/testsuite/gas/aarch64/sme2-26-invalid.s b/gas/testsuite/ga= s/aarch64/sme2-26-invalid.s new file mode 100644 index 00000000000..2eddec902b2 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-26-invalid.s @@ -0,0 +1,14 @@ + sqcvtn 0, { z0.s - z3.s } + sqcvtn z0.b, 0 + + sqcvtn z0.b, { z0.s - z1.s } + sqcvtn z0.b, { z0.s - z2.s } + sqcvtn z0.b, { z1.s - z4.s } + sqcvtn z0.b, { z2.s - z5.s } + sqcvtn z0.b, { z3.s - z6.s } + + sqcvtn z0.h, { z0.d - z1.d } + sqcvtn z0.h, { z0.d - z2.d } + sqcvtn z0.h, { z1.d - z4.d } + sqcvtn z0.h, { z2.d - z5.d } + sqcvtn z0.h, { z3.d - z6.d } diff --git a/gas/testsuite/gas/aarch64/sme2-26-noarch.d b/gas/testsuite/gas= /aarch64/sme2-26-noarch.d new file mode 100644 index 00000000000..e9af412a1e0 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-26-noarch.d @@ -0,0 +1,3 @@ +#as: -march=3Darmv8-a+sme +#source: sme2-26.s +#error_output: sme2-26-noarch.l diff --git a/gas/testsuite/gas/aarch64/sme2-26-noarch.l b/gas/testsuite/gas= /aarch64/sme2-26-noarch.l new file mode 100644 index 00000000000..b1bd4899d5e --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-26-noarch.l @@ -0,0 +1,25 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtn z0\.b,{z= 0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtn z31\.b,{= z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtn z0\.b,{z= 28\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtn z11\.b,{= z20\.s-z23\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtn z0\.h,{z= 0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtn z31\.h,{= z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtn z0\.h,{z= 28\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtn z22\.h,{= z4\.d-z7\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtun z0\.b,{= z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtun z31\.b,= {z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtun z0\.b,{= z28\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtun z11\.b,= {z20\.s-z23\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtun z0\.h,{= z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtun z31\.h,= {z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtun z0\.h,{= z28\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtun z22\.h,= {z4\.d-z7\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `uqcvtn z0\.b,{z= 0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `uqcvtn z31\.b,{= z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `uqcvtn z0\.b,{z= 28\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `uqcvtn z11\.b,{= z20\.s-z23\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `uqcvtn z0\.h,{z= 0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `uqcvtn z31\.h,{= z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `uqcvtn z0\.h,{z= 28\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `uqcvtn z22\.h,{= z4\.d-z7\.d}' diff --git a/gas/testsuite/gas/aarch64/sme2-26.d b/gas/testsuite/gas/aarch6= 4/sme2-26.d new file mode 100644 index 00000000000..96e0ca990f6 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-26.d @@ -0,0 +1,33 @@ +#as: -march=3Darmv8-a+sme2 +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +[^:]+: c133e040 sqcvtn z0\.b, {z0\.s-z3\.s} +[^:]+: c133e05f sqcvtn z31\.b, {z0\.s-z3\.s} +[^:]+: c133e3c0 sqcvtn z0\.b, {z28\.s-z31\.s} +[^:]+: c133e2cb sqcvtn z11\.b, {z20\.s-z23\.s} +[^:]+: c1b3e040 sqcvtn z0\.h, {z0\.d-z3\.d} +[^:]+: c1b3e05f sqcvtn z31\.h, {z0\.d-z3\.d} +[^:]+: c1b3e3c0 sqcvtn z0\.h, {z28\.d-z31\.d} +[^:]+: c1b3e0d6 sqcvtn z22\.h, {z4\.d-z7\.d} +[^:]+: c173e040 sqcvtun z0\.b, {z0\.s-z3\.s} +[^:]+: c173e05f sqcvtun z31\.b, {z0\.s-z3\.s} +[^:]+: c173e3c0 sqcvtun z0\.b, {z28\.s-z31\.s} +[^:]+: c173e2cb sqcvtun z11\.b, {z20\.s-z23\.s} +[^:]+: c1f3e040 sqcvtun z0\.h, {z0\.d-z3\.d} +[^:]+: c1f3e05f sqcvtun z31\.h, {z0\.d-z3\.d} +[^:]+: c1f3e3c0 sqcvtun z0\.h, {z28\.d-z31\.d} +[^:]+: c1f3e0d6 sqcvtun z22\.h, {z4\.d-z7\.d} +[^:]+: c133e060 uqcvtn z0\.b, {z0\.s-z3\.s} +[^:]+: c133e07f uqcvtn z31\.b, {z0\.s-z3\.s} +[^:]+: c133e3e0 uqcvtn z0\.b, {z28\.s-z31\.s} +[^:]+: c133e2eb uqcvtn z11\.b, {z20\.s-z23\.s} +[^:]+: c1b3e060 uqcvtn z0\.h, {z0\.d-z3\.d} +[^:]+: c1b3e07f uqcvtn z31\.h, {z0\.d-z3\.d} +[^:]+: c1b3e3e0 uqcvtn z0\.h, {z28\.d-z31\.d} +[^:]+: c1b3e0f6 uqcvtn z22\.h, {z4\.d-z7\.d} diff --git a/gas/testsuite/gas/aarch64/sme2-26.s b/gas/testsuite/gas/aarch6= 4/sme2-26.s new file mode 100644 index 00000000000..72bdbf68676 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-26.s @@ -0,0 +1,29 @@ + sqcvtn z0.b, { z0.s - z3.s } + sqcvtn z31.b, { z0.s - z3.s } + sqcvtn z0.b, { z28.s - z31.s } + sqcvtn z11.b, { z20.s - z23.s } + + sqcvtn z0.h, { z0.d - z3.d } + sqcvtn z31.h, { z0.d - z3.d } + sqcvtn z0.h, { z28.d - z31.d } + sqcvtn z22.h, { z4.d - z7.d } + + sqcvtun z0.b, { z0.s - z3.s } + sqcvtun z31.b, { z0.s - z3.s } + sqcvtun z0.b, { z28.s - z31.s } + sqcvtun z11.b, { z20.s - z23.s } + + sqcvtun z0.h, { z0.d - z3.d } + sqcvtun z31.h, { z0.d - z3.d } + sqcvtun z0.h, { z28.d - z31.d } + sqcvtun z22.h, { z4.d - z7.d } + + uqcvtn z0.b, { z0.s - z3.s } + uqcvtn z31.b, { z0.s - z3.s } + uqcvtn z0.b, { z28.s - z31.s } + uqcvtn z11.b, { z20.s - z23.s } + + uqcvtn z0.h, { z0.d - z3.d } + uqcvtn z31.h, { z0.d - z3.d } + uqcvtn z0.h, { z28.d - z31.d } + uqcvtn z22.h, { z4.d - z7.d } diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index f18f383a711..b445bf758fc 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -717,6 +717,7 @@ enum aarch64_insn_class sme_size_12_hs, sme_size_22, sme_size_22_hsd, + sme_sz_23, sme_str, sme_start, sme_stop, diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index b1d2d589a13..5f2e51044ce 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -1970,6 +1970,11 @@ aarch64_encode_variant_using_iclass (struct aarch64_= inst *inst) aarch64_get_variant (inst) + 1, 0); break; =20 + case sme_sz_23: + insert_field (FLD_SME_sz_23, &inst->value, + aarch64_get_variant (inst), 0); + break; + case sve_cpy: insert_fields (&inst->value, aarch64_get_variant (inst), 0, 2, FLD_SVE_M_14, FLD_size); diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index 759f6ab3611..55a01e6e593 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -188,7 +188,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 109876543210987654321= 09876543210 x1000000x10x100xxxxxx= xxxxxxxxxxx zero. */ - return 2865; + return 2874; } } } @@ -856,7 +856,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 x0x00000001xxxxx0= 00xxxxxxxxxxxx0 st1b. */ - return 2699; + return 2705; } else { @@ -864,7 +864,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 x0x00000001xxxxx1= 00xxxxxxxxxxxx0 st1b. */ - return 2700; + return 2706; } } else @@ -875,7 +875,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 x0x00000001xxxxx0= 10xxxxxxxxxxxx0 st1w. */ - return 2723; + return 2729; } else { @@ -883,7 +883,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 x0x00000001xxxxx1= 10xxxxxxxxxxxx0 st1w. */ - return 2724; + return 2730; } } } @@ -897,7 +897,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 x0x00000001xxxxx0= 01xxxxxxxxxxxx0 st1h. */ - return 2715; + return 2721; } else { @@ -905,7 +905,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 x0x00000001xxxxx1= 01xxxxxxxxxxxx0 st1h. */ - return 2716; + return 2722; } } else @@ -916,7 +916,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 x0x00000001xxxxx0= 11xxxxxxxxxxxx0 st1d. */ - return 2707; + return 2713; } else { @@ -924,7 +924,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 x0x00000001xxxxx1= 11xxxxxxxxxxxx0 st1d. */ - return 2708; + return 2714; } } } @@ -941,7 +941,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 x0x00000001xxxxx0= 00xxxxxxxxxxxx1 stnt1b. */ - return 2731; + return 2737; } else { @@ -949,7 +949,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 x0x00000001xxxxx1= 00xxxxxxxxxxxx1 stnt1b. */ - return 2732; + return 2738; } } else @@ -960,7 +960,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 x0x00000001xxxxx0= 10xxxxxxxxxxxx1 stnt1w. */ - return 2755; + return 2761; } else { @@ -968,7 +968,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 x0x00000001xxxxx1= 10xxxxxxxxxxxx1 stnt1w. */ - return 2756; + return 2762; } } } @@ -982,7 +982,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 x0x00000001xxxxx0= 01xxxxxxxxxxxx1 stnt1h. */ - return 2747; + return 2753; } else { @@ -990,7 +990,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 x0x00000001xxxxx1= 01xxxxxxxxxxxx1 stnt1h. */ - return 2748; + return 2754; } } else @@ -1001,7 +1001,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 x0x00000001xxxxx0= 11xxxxxxxxxxxx1 stnt1d. */ - return 2739; + return 2745; } else { @@ -1009,7 +1009,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 x0x00000001xxxxx1= 11xxxxxxxxxxxx1 stnt1d. */ - return 2740; + return 2746; } } } @@ -1073,7 +1073,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 x0x00000011xxxxx0= 00xxxxxxxxxxxx0 st1b. */ - return 2695; + return 2701; } else { @@ -1081,7 +1081,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 x0x00000011xxxxx1= 00xxxxxxxxxxxx0 st1b. */ - return 2696; + return 2702; } } else @@ -1092,7 +1092,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 x0x00000011xxxxx0= 10xxxxxxxxxxxx0 st1w. */ - return 2719; + return 2725; } else { @@ -1100,7 +1100,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 x0x00000011xxxxx1= 10xxxxxxxxxxxx0 st1w. */ - return 2720; + return 2726; } } } @@ -1114,7 +1114,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 x0x00000011xxxxx0= 01xxxxxxxxxxxx0 st1h. */ - return 2711; + return 2717; } else { @@ -1122,7 +1122,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 x0x00000011xxxxx1= 01xxxxxxxxxxxx0 st1h. */ - return 2712; + return 2718; } } else @@ -1133,7 +1133,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 x0x00000011xxxxx0= 11xxxxxxxxxxxx0 st1d. */ - return 2703; + return 2709; } else { @@ -1141,7 +1141,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 x0x00000011xxxxx1= 11xxxxxxxxxxxx0 st1d. */ - return 2704; + return 2710; } } } @@ -1158,7 +1158,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 x0x00000011xxxxx0= 00xxxxxxxxxxxx1 stnt1b. */ - return 2727; + return 2733; } else { @@ -1166,7 +1166,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 x0x00000011xxxxx1= 00xxxxxxxxxxxx1 stnt1b. */ - return 2728; + return 2734; } } else @@ -1177,7 +1177,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 x0x00000011xxxxx0= 10xxxxxxxxxxxx1 stnt1w. */ - return 2751; + return 2757; } else { @@ -1185,7 +1185,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 x0x00000011xxxxx1= 10xxxxxxxxxxxx1 stnt1w. */ - return 2752; + return 2758; } } } @@ -1199,7 +1199,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 x0x00000011xxxxx0= 01xxxxxxxxxxxx1 stnt1h. */ - return 2743; + return 2749; } else { @@ -1207,7 +1207,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 x0x00000011xxxxx1= 01xxxxxxxxxxxx1 stnt1h. */ - return 2744; + return 2750; } } else @@ -1218,7 +1218,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 x0x00000011xxxxx0= 11xxxxxxxxxxxx1 stnt1d. */ - return 2735; + return 2741; } else { @@ -1226,7 +1226,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 x0x00000011xxxxx1= 11xxxxxxxxxxxx1 stnt1d. */ - return 2736; + return 2742; } } } @@ -1326,7 +1326,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 xx0000010000xxxxx= xxxxxxxxxx001xx usmlall. */ - return 2846; + return 2855; } } else @@ -1358,7 +1358,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1098765432109= 8765432109876543210 xx0000010001x= xxx0xxxxxxxxx100xxx usmlall. */ - return 2847; + return 2856; } else { @@ -1366,7 +1366,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1098765432109= 8765432109876543210 xx0000010001x= xxx1xxxxxxxxx100xxx usmlall. */ - return 2848; + return 2857; } } } @@ -1381,7 +1381,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 xx0000010000xxxxx= xxxxxxxxxx100xx umlall. */ - return 2810; + return 2816; } else { @@ -1389,7 +1389,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 xx0000010000xxxxx= xxxxxxxxxx101xx sumlall. */ - return 2770; + return 2776; } } else @@ -1402,7 +1402,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1098765432109= 8765432109876543210 xx0000010001x= xxx0xxxxxxxxx010xxx umlall. */ - return 2811; + return 2817; } else { @@ -1410,7 +1410,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1098765432109= 8765432109876543210 xx0000010001x= xxx1xxxxxxxxx010xxx umlall. */ - return 2812; + return 2818; } } else @@ -1421,7 +1421,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1098765432109= 8765432109876543210 xx0000010001x= xxx0xxxxxxxxx110xxx sumlall. */ - return 2771; + return 2777; } else { @@ -1429,7 +1429,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1098765432109= 8765432109876543210 xx0000010001x= xxx1xxxxxxxxx110xxx sumlall. */ - return 2772; + return 2778; } } } @@ -1475,7 +1475,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 109876543210987654321= 09876543210 xx0000010000xxxxxxxxx= xxxxxx11xxx umlsll. */ - return 2826; + return 2832; } else { @@ -1485,7 +1485,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 xx0000010001xxxx0= xxxxxxxxxx11xxx umlsll. */ - return 2827; + return 2833; } else { @@ -1493,7 +1493,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 xx0000010001xxxx1= xxxxxxxxxx11xxx umlsll. */ - return 2828; + return 2834; } } } @@ -1721,7 +1721,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1098765432109= 8765432109876543210 x10000011000x= xxxxxx0xxxxxxx00xxx smlall. */ - return 2868; + return 2877; } else { @@ -1731,7 +1731,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 109876543= 21098765432109876543210 x10000011= 001xxxx0xx0xxxxxxx00xxx smlall. = */ - return 2869; + return 2878; } else { @@ -1739,7 +1739,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 109876543= 21098765432109876543210 x10000011= 001xxxx1xx0xxxxxxx00xxx smlall. = */ - return 2870; + return 2879; } } } @@ -1806,7 +1806,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1098765432109= 8765432109876543210 x10000011000x= xxxxxx0xxxxxxx10xxx umlall. */ - return 2877; + return 2886; } else { @@ -1816,7 +1816,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 109876543= 21098765432109876543210 x10000011= 001xxxx0xx0xxxxxxx10xxx umlall. = */ - return 2878; + return 2887; } else { @@ -1824,7 +1824,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 109876543= 21098765432109876543210 x10000011= 001xxxx1xx0xxxxxxx10xxx umlall. = */ - return 2879; + return 2888; } } } @@ -1884,7 +1884,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 xx0000011000xxxxx= xx0xxxxxxx01xxx smlsll. */ - return 2871; + return 2880; } else { @@ -1894,7 +1894,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1098765432109= 8765432109876543210 xx0000011001x= xxx0xx0xxxxxxx01xxx smlsll. */ - return 2872; + return 2881; } else { @@ -1902,7 +1902,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1098765432109= 8765432109876543210 xx0000011001x= xxx1xx0xxxxxxx01xxx smlsll. */ - return 2873; + return 2882; } } } @@ -1943,7 +1943,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1098765432109876543210987= 6543210 xx100001100xxxxxxxxxxxxxx= xx01xxx umopa. */ - return 2834; + return 2840; } } else @@ -1958,7 +1958,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 xx0000011000xxxxx= xx0xxxxxxx11xxx umlsll. */ - return 2880; + return 2889; } else { @@ -1968,7 +1968,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1098765432109= 8765432109876543210 xx0000011001x= xxx0xx0xxxxxxx11xxx umlsll. */ - return 2881; + return 2890; } else { @@ -1976,7 +1976,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1098765432109= 8765432109876543210 xx0000011001x= xxx1xx0xxxxxxx11xxx umlsll. */ - return 2882; + return 2891; } } } @@ -2017,7 +2017,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1098765432109876543210987= 6543210 xx100001100xxxxxxxxxxxxxx= xx11xxx umops. */ - return 2835; + return 2841; } } } @@ -2103,7 +2103,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1098765432109= 8765432109876543210 xxx000010101x= xxx0xx0xxxxxx100xxx svdot. */ - return 2776; + return 2782; } else { @@ -2133,7 +2133,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1098765432109= 8765432109876543210 xxx000010101x= xxx0xx1xxxxxx010xxx udot. */ - return 2782; + return 2788; } } else @@ -2144,7 +2144,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1098765432109= 8765432109876543210 xxx000010101x= xxx0xx0xxxxxx110xxx uvdot. */ - return 2855; + return 2864; } else { @@ -2152,7 +2152,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1098765432109= 8765432109876543210 xxx000010101x= xxx0xx1xxxxxx110xxx udot. */ - return 2788; + return 2794; } } } @@ -2232,7 +2232,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1098765432109= 8765432109876543210 xxx000010101x= xxx1xx0xxxxxx100xxx svdot. */ - return 2777; + return 2783; } else { @@ -2262,7 +2262,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1098765432109= 8765432109876543210 xxx000010101x= xxx1xx1xxxxxx010xxx udot. */ - return 2783; + return 2789; } } else @@ -2273,7 +2273,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1098765432109= 8765432109876543210 xxx000010101x= xxx1xx0xxxxxx110xxx uvdot. */ - return 2856; + return 2865; } else { @@ -2281,7 +2281,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1098765432109= 8765432109876543210 xxx000010101x= xxx1xx1xxxxxx110xxx udot. */ - return 2789; + return 2795; } } } @@ -2362,7 +2362,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 xxx000010101xxxx0= xxxxxxxxx101xxx usdot. */ - return 2840; + return 2849; } } else @@ -2392,7 +2392,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 xxx000010101xxxx0= xxxxxxxxx111xxx sudot. */ - return 2766; + return 2772; } } } @@ -2460,7 +2460,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1098765432109= 8765432109876543210 xxx000010101x= xxx1xx0xxxxxx101xxx usvdot. */ - return 2854; + return 2863; } else { @@ -2468,7 +2468,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1098765432109= 8765432109876543210 xxx000010101x= xxx1xx1xxxxxx101xxx usdot. */ - return 2841; + return 2850; } } } @@ -2490,7 +2490,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1098765432109= 8765432109876543210 xxx000010101x= xxx1xx0xxxxxx111xxx suvdot. */ - return 2775; + return 2781; } else { @@ -2498,7 +2498,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1098765432109= 8765432109876543210 xxx000010101x= xxx1xx1xxxxxx111xxx sudot. */ - return 2767; + return 2773; } } } @@ -2522,7 +2522,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 xx000001110xxxxx0= xx0xxxxxxx00xxx fmla. */ - return 2884; + return 2893; } else { @@ -2530,7 +2530,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 xx000001110xxxxx1= xx0xxxxxxx00xxx fmla. */ - return 2885; + return 2894; } } else @@ -2576,7 +2576,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1098765432109= 8765432109876543210 xx000001110xx= xxx0xx00xxxxxx01xxx sdot. */ - return 2866; + return 2875; } else { @@ -2584,7 +2584,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1098765432109= 8765432109876543210 xx000001110xx= xxx1xx00xxxxxx01xxx sdot. */ - return 2867; + return 2876; } } else @@ -2593,7 +2593,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 xx000001110xxxxxx= xx01xxxxxx01xxx svdot. */ - return 2874; + return 2883; } } else @@ -2662,7 +2662,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 xx000001110xxxxx0= xx0xxxxxxx10xxx fmls. */ - return 2886; + return 2895; } else { @@ -2670,7 +2670,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 xx000001110xxxxx1= xx0xxxxxxx10xxx fmls. */ - return 2887; + return 2896; } } else @@ -2681,7 +2681,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 xx0000011100xxxxx= xx1xxxxxxx10xxx umlal. */ - return 2802; + return 2808; } else { @@ -2691,7 +2691,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1098765432109= 8765432109876543210 xx0000011101x= xxx0xx1xxxxxxx10xxx umlal. */ - return 2803; + return 2809; } else { @@ -2699,7 +2699,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1098765432109= 8765432109876543210 xx0000011101x= xxx1xx1xxxxxxx10xxx umlal. */ - return 2804; + return 2810; } } } @@ -2725,7 +2725,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 xxx00001110xxxxx0= xx00xxxxxx11xxx udot. */ - return 2875; + return 2884; } else { @@ -2733,7 +2733,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 xxx00001110xxxxx1= xx00xxxxxx11xxx udot. */ - return 2876; + return 2885; } } else @@ -2742,7 +2742,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 109876543210987654321= 09876543210 xxx00001110xxxxxxxx01= xxxxxx11xxx uvdot. */ - return 2883; + return 2892; } } else @@ -2753,7 +2753,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 109876543210987654321= 09876543210 xxx000011100xxxxxxx1x= xxxxxx11xxx umlsl. */ - return 2818; + return 2824; } else { @@ -2763,7 +2763,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 xxx000011101xxxx0= xx1xxxxxxx11xxx umlsl. */ - return 2819; + return 2825; } else { @@ -2771,7 +2771,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765= 432109876543210 xxx000011101xxxx1= xx1xxxxxxx11xxx umlsl. */ - return 2820; + return 2826; } } } @@ -2868,7 +2868,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1= 0987654321098765432109876543210 x= 10000010x10xxxx0xx000xxxxx001xx u= smlall. */ - retu= rn 2850; + retu= rn 2859; } else { @@ -2876,7 +2876,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1= 0987654321098765432109876543210 x= 10000010x11xxxx0xx000xxxxx001xx u= smlall. */ - retu= rn 2851; + retu= rn 2860; } } else @@ -2887,7 +2887,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1= 0987654321098765432109876543210 x= 10000011x1xxxx00xx000xxxxx001xx u= smlall. */ - retu= rn 2852; + retu= rn 2861; } else { @@ -2895,7 +2895,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1= 0987654321098765432109876543210 x= 10000011x1xxxx10xx000xxxxx001xx u= smlall. */ - retu= rn 2853; + retu= rn 2862; } } } @@ -3092,7 +3092,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 109876543= 21098765432109876543210 x1000001x= x1xxxxx0xx001xxxxx001xx usmlall. = */ - return 2849; + return 2858; } } else @@ -3198,7 +3198,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1= 0987654321098765432109876543210 x= 10000010x10xxxx0xx000xxxxx100xx u= mlall. */ - retu= rn 2814; + retu= rn 2820; } else { @@ -3206,7 +3206,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1= 0987654321098765432109876543210 x= 10000010x11xxxx0xx000xxxxx100xx u= mlall. */ - retu= rn 2815; + retu= rn 2821; } } else @@ -3217,7 +3217,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1= 0987654321098765432109876543210 x= 10000011x1xxxx00xx000xxxxx100xx u= mlall. */ - retu= rn 2816; + retu= rn 2822; } else { @@ -3225,7 +3225,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1= 0987654321098765432109876543210 x= 10000011x1xxxx10xx000xxxxx100xx u= mlall. */ - retu= rn 2817; + retu= rn 2823; } } } @@ -3237,7 +3237,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987= 654321098765432109876543210 x1000= 001xx10xxxx0xx000xxxxx101xx sumla= ll. */ - return 2= 773; + return 2= 779; } else { @@ -3245,7 +3245,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987= 654321098765432109876543210 x1000= 001xx11xxxx0xx000xxxxx101xx sumla= ll. */ - return 2= 774; + return 2= 780; } } } @@ -3346,7 +3346,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1= 0987654321098765432109876543210 x= 10000010110xxxx0xx010xxxxx10xxx u= mlal. */ - retu= rn 2806; + retu= rn 2812; } else { @@ -3354,7 +3354,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1= 0987654321098765432109876543210 x= 10000010111xxxx0xx010xxxxx10xxx u= mlal. */ - retu= rn 2807; + retu= rn 2813; } } else @@ -3365,7 +3365,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1= 0987654321098765432109876543210 x= 1000001111xxxx00xx010xxxxx10xxx u= mlal. */ - retu= rn 2808; + retu= rn 2814; } else { @@ -3373,7 +3373,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1= 0987654321098765432109876543210 x= 1000001111xxxx10xx010xxxxx10xxx u= mlal. */ - retu= rn 2809; + retu= rn 2815; } } } @@ -3431,7 +3431,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1098765432109= 8765432109876543210 x1000001xx1xx= xxx0xx001xxxxx10xxx umlall. */ - return 2813; + return 2819; } else { @@ -3443,7 +3443,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987= 654321098765432109876543210 x1000= 0010x10xxxx0xx101xxxxx10xxx udot.= */ - return 2= 790; + return 2= 796; } else { @@ -3451,7 +3451,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987= 654321098765432109876543210 x1000= 0010x11xxxx0xx101xxxxx10xxx udot.= */ - return 2= 791; + return 2= 797; } } else @@ -3462,7 +3462,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987= 654321098765432109876543210 x1000= 0011x1xxxx00xx101xxxxx10xxx udot.= */ - return 2= 792; + return 2= 798; } else { @@ -3470,7 +3470,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987= 654321098765432109876543210 x1000= 0011x1xxxx10xx101xxxxx10xxx udot.= */ - return 2= 793; + return 2= 799; } } } @@ -3493,7 +3493,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 109876543= 21098765432109876543210 x1000001x= 11xxxxx0xx011xxxxx10xxx umlal. */ - return 2805; + return 2811; } } else @@ -3720,7 +3720,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1= 0987654321098765432109876543210 x= 10000010010xxxx0xx101xxxxx01xxx u= sdot. */ - retu= rn 2842; + retu= rn 2851; } else { @@ -3728,7 +3728,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1= 0987654321098765432109876543210 x= 10000010011xxxx0xx101xxxxx01xxx u= sdot. */ - retu= rn 2843; + retu= rn 2852; } } else @@ -3739,7 +3739,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1= 0987654321098765432109876543210 x= 1000001101xxxx00xx101xxxxx01xxx u= sdot. */ - retu= rn 2844; + retu= rn 2853; } else { @@ -3747,7 +3747,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1= 0987654321098765432109876543210 x= 1000001101xxxx10xx101xxxxx01xxx u= sdot. */ - retu= rn 2845; + retu= rn 2854; } } } @@ -3851,7 +3851,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 109876543= 21098765432109876543210 x10000010= x10xxxx0xxx00xxxxx11xxx umlsll. = */ - return 2830; + return 2836; } else { @@ -3859,7 +3859,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 109876543= 21098765432109876543210 x10000010= x11xxxx0xxx00xxxxx11xxx umlsll. = */ - return 2831; + return 2837; } } else @@ -3870,7 +3870,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 109876543= 21098765432109876543210 x10000011= x1xxxx00xxx00xxxxx11xxx umlsll. = */ - return 2832; + return 2838; } else { @@ -3878,7 +3878,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 109876543= 21098765432109876543210 x10000011= x1xxxx10xxx00xxxxx11xxx umlsll. = */ - return 2833; + return 2839; } } } @@ -3937,7 +3937,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1= 0987654321098765432109876543210 x= 10000010110xxxx0xx010xxxxx11xxx u= mlsl. */ - retu= rn 2822; + retu= rn 2828; } else { @@ -3945,7 +3945,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1= 0987654321098765432109876543210 x= 10000010111xxxx0xx010xxxxx11xxx u= mlsl. */ - retu= rn 2823; + retu= rn 2829; } } else @@ -3956,7 +3956,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1= 0987654321098765432109876543210 x= 1000001111xxxx00xx010xxxxx11xxx u= mlsl. */ - retu= rn 2824; + retu= rn 2830; } else { @@ -3964,7 +3964,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 1= 0987654321098765432109876543210 x= 1000001111xxxx10xx010xxxxx11xxx [...] [diff truncated at 100000 bytes]