From: Andrew Burgess <aburgess@sourceware.org>
To: bfd-cvs@sourceware.org
Subject: [binutils-gdb] opcodes/arm: adjust whitespace in cpsie instruction
Date: Mon, 3 Apr 2023 11:22:44 +0000 (GMT) [thread overview]
Message-ID: <20230403112244.E24BA3858D37@sourceware.org> (raw)
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=4fc808ae2a3dee6a791c2a90b25db9c7a3790563
commit 4fc808ae2a3dee6a791c2a90b25db9c7a3790563
Author: Andrew Burgess <aburgess@redhat.com>
Date: Tue Feb 28 21:40:17 2023 +0000
opcodes/arm: adjust whitespace in cpsie instruction
While I was working on the disassembler styling for ARM I noticed that
the whitespace in the cpsie instruction was inconsistent with most of
the other ARM disassembly output, the disassembly for cpsie looks like
this:
cpsie if,#10
notice there's no space before the '#10' immediate, most other ARM
instructions have a space before each operand.
This commit updates the disassembler to add the missing space, and
updates the tests I found that tested this instruction.
Diff:
---
gas/testsuite/gas/arm/archv6.d | 4 ++--
gas/testsuite/gas/arm/t16-bad.s | 4 ++--
opcodes/arm-dis.c | 4 ++--
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/gas/testsuite/gas/arm/archv6.d b/gas/testsuite/gas/arm/archv6.d
index bee9909f2af..ec609b51237 100644
--- a/gas/testsuite/gas/arm/archv6.d
+++ b/gas/testsuite/gas/arm/archv6.d
@@ -219,7 +219,7 @@ Disassembly of section .text:
0+34c <[^>]*> e6ef2475 ? uxtb r2, r5, ror #8
0+350 <[^>]*> 16ef2075 ? uxtbne r2, r5
0+354 <[^>]*> 16ef2475 ? uxtbne r2, r5, ror #8
-0+358 <[^>]*> f10a00ca ? cpsie if,#10
-0+35c <[^>]*> f10a00d5 ? cpsie if,#21
+0+358 <[^>]*> f10a00ca ? cpsie if, #10
+0+35c <[^>]*> f10a00d5 ? cpsie if, #21
0+360 <[^>]*> f8cd0510 ? srsia sp, #16
0+364 <[^>]*> f9ed0510 ? srsib sp!, #16
diff --git a/gas/testsuite/gas/arm/t16-bad.s b/gas/testsuite/gas/arm/t16-bad.s
index 9d2ced3ca3d..8b0865da693 100644
--- a/gas/testsuite/gas/arm/t16-bad.s
+++ b/gas/testsuite/gas/arm/t16-bad.s
@@ -131,8 +131,8 @@ l:
@ Miscellaneous
bkpt #257
- cpsie ai,#5
- cpsid ai,#5
+ cpsie ai, #5
+ cpsid ai, #5
@ Conditional suffixes
addeq r0,r1,r2
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index dffbad3e525..b71ab984e19 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -3828,11 +3828,11 @@ static const struct opcode32 arm_opcodes[] =
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0xf1080000, 0xfffffe3f, "cpsie\t%{B:%8'a%7'i%6'f%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0xf10a0000, 0xfffffe20, "cpsie\t%{B:%8'a%7'i%6'f%},%{I:#%0-4d%}"},
+ 0xf10a0000, 0xfffffe20, "cpsie\t%{B:%8'a%7'i%6'f%}, %{I:#%0-4d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0xf10C0000, 0xfffffe3f, "cpsid\t%{B:%8'a%7'i%6'f%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
- 0xf10e0000, 0xfffffe20, "cpsid\t%{B:%8'a%7'i%6'f%},%{I:#%0-4d%}"},
+ 0xf10e0000, 0xfffffe20, "cpsid\t%{B:%8'a%7'i%6'f%}, %{I:#%0-4d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0xf1000000, 0xfff1fe20, "cps\t%{I:#%0-4d%}"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
reply other threads:[~2023-04-03 11:22 UTC|newest]
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