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Subject: [binutils-gdb] LoongArch: gas: Add support for linker relaxation.
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https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D56576f4a722b=
7398d35802ecf7d4185c27d6d69b

commit 56576f4a722b7398d35802ecf7d4185c27d6d69b
Author: mengqinggang <mengqinggang@loongson.cn>
Date:   Thu Dec 1 16:17:46 2022 +0800

    LoongArch: gas: Add support for linker relaxation.
   =20
    Add gas -mrelax and -mno-relax option.
    Add R_LARCH_RELAX reloc for instrction if it can be relaxed.
    ADD R_LARCH_ALIGN reloc for align pseudo instruction because relax.
    Add ADD/SUB reloc pair for debug and exception data to calculate symbol
    substraction because relax.
   =20
    gas/ChangeLog:
   =20
            * config/tc-loongarch.c:
            (struct loongarch_cl_insn): New macro_id member.
            (enum options): New OPTION_RELAX and OPTION_NO_RELAX.
            (struct option): New mrelax and mno-relax.
            (md_parse_option): Likewise.
            (get_internal_label):
            (loongarch_args_parser_can_match_arg_helper): Generate relax re=
loc.
            (move_insn): Set fx_frag and fx_where if exist.
            (append_fixp_and_insn): Call frag_wane and frag_new for linker =
relax
            relocs.
            (loongarch_assemble_INSNs): New loongarch_cl_insn pointer param=
eter.
            (md_assemble): Fix function call.
            (fix_reloc_insn): Likewise.
            (md_apply_fix): Generate ADD/SUB reloc pair for debug and excep=
tion
            data.
            (loongarch_fix_adjustable): Delete.
            (md_convert_frag): Generate new fix.
            (loongarch_pre_output_hook): New function.
            (loongarch_make_nops): Likewise.
            (loongarch_frag_align_code): Likewise.
            (loongarch_insert_uleb128_fixes): Likewise.
            (loongarch_md_finish): Likewise.
            * config/tc-loongarch.h
            (md_allow_local_subtract): New macro define.
            (loongarch_frag_align_code): New declare.
            (md_do_align): Likewise.
            (loongarch_fix_adjustable): Delete.
            (tc_fix_adjustable): New macro define.
            (TC_FORCE_RELOCATION_SUB_SAME): Likewise.
            (TC_LINKRELAX_FIXUP): Likewise.
            (TC_FORCE_RELOCATION_LOCAL): Likewise.
            (DWARF2_USE_FIXED_ADVANCE_PC): Likewise.
            (MD_APPLY_SYM_VALUE): Likewise.
            (tc_symbol_new_hook): New extern.
            (NOP_OPCODE): Delete.
            (loongarch_pre_output_hook): New macro define.
            (md_pre_output_hook): Likewise.
            (md_finish): Likewise.
            (loongarch_md_finish): New extern.
            * testsuite/gas/all/align.d: Mark as unsupported on LoongArch.
            * testsuite/gas/all/gas.exp: Xfail loongarch*-*.
            * testsuite/gas/all/relax.d: Likewise.
            * testsuite/gas/elf/dwarf-5-irp.d: Likewise.
            * testsuite/gas/elf/dwarf-5-loc0.d: Likewise.
            * testsuite/gas/elf/dwarf-5-macro-include.d: Likewise.
            * testsuite/gas/elf/dwarf-5-macro.d: Likewise.
            * testsuite/gas/elf/dwarf2-11.d: Likewise.
            * testsuite/gas/elf/dwarf2-15.d: Likewise.
            * testsuite/gas/elf/dwarf2-16.d: Likewise.
            * testsuite/gas/elf/dwarf2-17.d: Likewise.
            * testsuite/gas/elf/dwarf2-18.d: Likewise.
            * testsuite/gas/elf/dwarf2-19.d: Likewise.
            * testsuite/gas/elf/dwarf2-5.d: Likewise.
            * testsuite/gas/elf/ehopt0.d: Likewise.
            * testsuite/gas/elf/elf.exp: Likewise.
            * testsuite/gas/elf/section11.d: Likewise.
            * testsuite/gas/lns/lns.exp: Likewise.
            * testsuite/gas/loongarch/jmp_op.d: Regenerated.
            * testsuite/gas/loongarch/li.d: Likewise.
            * testsuite/gas/loongarch/macro_op.d: Likewise.
            * testsuite/gas/loongarch/macro_op_32.d: Likewise.
            * testsuite/gas/loongarch/macro_op_large_abs.d: Likewise.
            * testsuite/gas/loongarch/macro_op_large_pc.d: Likewise.
            * testsuite/gas/loongarch/relax_align.d: New test.
            * testsuite/gas/loongarch/relax_align.s: New test.
            * testsuite/gas/loongarch/uleb128.d: New test.
            * testsuite/gas/loongarch/uleb128.s: New test.

Diff:
---
 gas/config/tc-loongarch.c                        | 427 +++++++++++++++++++=
----
 gas/config/tc-loongarch.h                        |  48 ++-
 gas/testsuite/gas/all/align.d                    |   5 +-
 gas/testsuite/gas/all/gas.exp                    |  10 +-
 gas/testsuite/gas/all/relax.d                    |   4 +
 gas/testsuite/gas/elf/dwarf-5-irp.d              |   3 +-
 gas/testsuite/gas/elf/dwarf-5-loc0.d             |   3 +-
 gas/testsuite/gas/elf/dwarf-5-macro-include.d    |   2 +-
 gas/testsuite/gas/elf/dwarf-5-macro.d            |   2 +-
 gas/testsuite/gas/elf/dwarf2-11.d                |   3 +-
 gas/testsuite/gas/elf/dwarf2-15.d                |   3 +-
 gas/testsuite/gas/elf/dwarf2-16.d                |   3 +-
 gas/testsuite/gas/elf/dwarf2-17.d                |   3 +-
 gas/testsuite/gas/elf/dwarf2-18.d                |   3 +-
 gas/testsuite/gas/elf/dwarf2-19.d                |   3 +-
 gas/testsuite/gas/elf/dwarf2-5.d                 |   3 +-
 gas/testsuite/gas/elf/ehopt0.d                   |   3 +
 gas/testsuite/gas/elf/elf.exp                    |   3 +
 gas/testsuite/gas/elf/section11.d                |   4 +-
 gas/testsuite/gas/lns/lns.exp                    |   1 +
 gas/testsuite/gas/loongarch/jmp_op.d             |  65 ++--
 gas/testsuite/gas/loongarch/li.d                 |   8 +-
 gas/testsuite/gas/loongarch/macro_op.d           |  68 ++--
 gas/testsuite/gas/loongarch/macro_op_32.d        |  24 +-
 gas/testsuite/gas/loongarch/macro_op_large_abs.d |  32 +-
 gas/testsuite/gas/loongarch/macro_op_large_pc.d  | 134 +++----
 gas/testsuite/gas/loongarch/relax_align.d        |  26 ++
 gas/testsuite/gas/loongarch/relax_align.s        |   5 +
 gas/testsuite/gas/loongarch/uleb128.d            |  36 ++
 gas/testsuite/gas/loongarch/uleb128.s            |  20 ++
 30 files changed, 725 insertions(+), 229 deletions(-)

diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c
index 7d8749c5951..c55d4ee234a 100644
--- a/gas/config/tc-loongarch.c
+++ b/gas/config/tc-loongarch.c
@@ -20,6 +20,7 @@
    see <http://www.gnu.org/licenses/>.  */
=20
 #include "as.h"
+#include "subsegs.h"
 #include "dw2gencfi.h"
 #include "loongarch-lex.h"
 #include "elf/loongarch.h"
@@ -30,6 +31,7 @@
 #include <string.h>
 #include <stdio.h>
 #include <assert.h>
+#include "libbfd.h"
=20
 /* All information about an instruction during assemble.  */
 struct loongarch_cl_insn
@@ -70,6 +72,7 @@ struct loongarch_cl_insn
   long where;
   /* The relocs associated with the instruction, if any.  */
   fixS *fixp[MAX_RELOC_NUMBER_A_INSN];
+  long macro_id;
 };
=20
 #ifndef DEFAULT_ARCH
@@ -116,6 +119,8 @@ enum options
   OPTION_LA_LOCAL_WITH_ABS,
   OPTION_LA_GLOBAL_WITH_PCREL,
   OPTION_LA_GLOBAL_WITH_ABS,
+  OPTION_RELAX,
+  OPTION_NO_RELAX,
=20
   OPTION_END_OF_ENUM,
 };
@@ -130,6 +135,9 @@ struct option md_longopts[] =3D
   { "mla-global-with-pcrel", no_argument, NULL, OPTION_LA_GLOBAL_WITH_PCRE=
L },
   { "mla-global-with-abs", no_argument, NULL, OPTION_LA_GLOBAL_WITH_ABS },
=20
+  { "mrelax", no_argument, NULL, OPTION_RELAX },
+  { "mno-relax", no_argument, NULL, OPTION_NO_RELAX },
+
   { NULL, no_argument, NULL, 0 }
 };
=20
@@ -195,6 +203,14 @@ md_parse_option (int c, const char *arg)
       LARCH_opts.ase_gabs =3D 1;
       break;
=20
+    case OPTION_RELAX:
+      LARCH_opts.relax =3D 1;
+      break;
+
+    case OPTION_NO_RELAX:
+      LARCH_opts.relax =3D 0;
+      break;
+
     case OPTION_IGNORE:
       break;
=20
@@ -460,7 +476,6 @@ get_internal_label (expressionS *label_expr, unsigned l=
ong label,
 		    int augend /* 0 for previous, 1 for next.  */)
 {
   assert (label < INTERNAL_LABEL_SPECIAL);
-  if (augend =3D=3D 0 && internal_label_count[label] =3D=3D 0)
     as_fatal (_("internal error: we have no internal label yet"));
   label_expr->X_op =3D O_symbol;
   label_expr->X_add_symbol =3D
@@ -617,13 +632,26 @@ loongarch_args_parser_can_match_arg_helper (char esc_=
ch1, char esc_ch2,
 	    as_fatal (
 		      _("not support reloc bit-field\nfmt: %c%c %s\nargs: %s"),
 		      esc_ch1, esc_ch2, bit_field, arg);
+
 	  if (ip->reloc_info[0].type >=3D BFD_RELOC_LARCH_B16
-	      && ip->reloc_info[0].type < BFD_RELOC_LARCH_RELAX)
+	      && ip->reloc_info[0].type < BFD_RELOC_LARCH_SUB_ULEB128)
 	    {
 	      /* As we compact stack-relocs, it is no need for pop operation.
 		 But break out until here in order to check the imm field.
 		 May be reloc_num > 1 if implement relax?  */
 	      ip->reloc_num +=3D reloc_num;
+	      reloc_type =3D ip->reloc_info[0].type;
+
+	      if (LARCH_opts.relax && ip->macro_id
+		    && (BFD_RELOC_LARCH_PCALA_HI20 =3D=3D reloc_type
+			|| BFD_RELOC_LARCH_PCALA_LO12 =3D=3D reloc_type
+			|| BFD_RELOC_LARCH_GOT_PC_HI20 =3D=3D reloc_type
+			|| BFD_RELOC_LARCH_GOT_PC_LO12 =3D=3D reloc_type))
+		{
+		  ip->reloc_info[ip->reloc_num].type =3D BFD_RELOC_LARCH_RELAX;
+		  ip->reloc_info[ip->reloc_num].value =3D const_0;
+		  ip->reloc_num++;
+		}
 	      break;
 	    }
 	  reloc_num++;
@@ -835,8 +863,11 @@ move_insn (struct loongarch_cl_insn *insn, fragS *frag=
, long where)
   insn->where =3D where;
   for (i =3D 0; i < insn->reloc_num; i++)
     {
-      insn->fixp[i]->fx_frag =3D frag;
-      insn->fixp[i]->fx_where =3D where;
+      if (insn->fixp[i])
+	{
+	  insn->fixp[i]->fx_frag =3D frag;
+	  insn->fixp[i]->fx_where =3D where;
+	}
     }
   install_insn (insn);
 }
@@ -875,6 +906,21 @@ append_fixp_and_insn (struct loongarch_cl_insn *ip)
     as_fatal (_("Internal error: not support relax now"));
   else
     append_fixed_insn (ip);
+
+  /* We need to start a new frag after any instruction that can be
+     optimized away or compressed by the linker during relaxation, to prev=
ent
+     the assembler from computing static offsets across such an instructio=
n.
+
+     This is necessary to get correct .eh_frame cfa info. If one cfa's two
+     symbol is not in the same frag, it will generate relocs to calculate
+     symbol subtraction. (gas/dw2gencfi.c:output_cfi_insn:
+     if (symbol_get_frag (to) =3D=3D symbol_get_frag (from)))  */
+  if (BFD_RELOC_LARCH_PCALA_HI20 =3D=3D reloc_info[0].type
+      || BFD_RELOC_LARCH_GOT_PC_HI20 =3D=3D reloc_info[0].type)
+    {
+      frag_wane (frag_now);
+      frag_new (0);
+    }
 }
=20
 /* Ask helper for returning a malloced c_str or NULL.  */
@@ -968,7 +1014,7 @@ assember_macro_helper (const char *const args[], void =
*context_ptr)
  * assuming 'not starting with space and not ending with space' or pass in
  * empty c_str.  */
 static void
-loongarch_assemble_INSNs (char *str)
+loongarch_assemble_INSNs (char *str, struct loongarch_cl_insn *ctx)
 {
   char *rest;
   size_t len_str =3D strlen(str);
@@ -991,6 +1037,7 @@ loongarch_assemble_INSNs (char *str)
=20
       struct loongarch_cl_insn the_one =3D { 0 };
       the_one.name =3D str;
+      the_one.macro_id =3D ctx->macro_id;
=20
       for (; *str && *str !=3D ' '; str++)
 	;
@@ -1014,24 +1061,27 @@ loongarch_assemble_INSNs (char *str)
       append_fixp_and_insn (&the_one);
       if (the_one.insn_length =3D=3D 0 && the_one.insn->macro)
 	{
+	  the_one.macro_id =3D 1;
+
 	  char *c_str =3D loongarch_expand_macro (the_one.insn->macro,
 						the_one.arg_strs,
 						assember_macro_helper,
 						&the_one, len_str);
-	  loongarch_assemble_INSNs (c_str);
+	  loongarch_assemble_INSNs (c_str, &the_one);
 	  free (c_str);
 	}
     }
   while (0);
=20
   if (*rest !=3D '\0')
-    loongarch_assemble_INSNs (rest);
+    loongarch_assemble_INSNs (rest, ctx);
 }
=20
 void
 md_assemble (char *str)
 {
-  loongarch_assemble_INSNs (str);
+  struct loongarch_cl_insn the_one =3D { 0 };
+  loongarch_assemble_INSNs (str, &the_one);
 }
=20
 const char *
@@ -1062,7 +1112,7 @@ static void fix_reloc_insn (fixS *fixP, bfd_vma reloc=
_val, char *buf)
=20
   insn =3D bfd_getl32 (buf);
=20
-  if (!loongarch_adjust_reloc_bitsfield(howto, &reloc_val))
+  if (!loongarch_adjust_reloc_bitsfield (NULL, howto, &reloc_val))
     as_warn_where (fixP->fx_file, fixP->fx_line, "Reloc overflow");
=20
   insn =3D (insn & (insn_t)howto->src_mask)
@@ -1137,6 +1187,23 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATT=
RIBUTE_UNUSED)
       fix_reloc_insn (fixP, (bfd_vma)stack_top, buf);
       break;
=20
+    /* LARCH only has R_LARCH_64/32, not has R_LARCH_24/16/8.
+       For BFD_RELOC_64/32, if fx_addsy and fx_subsy not null, wer need
+       generate BFD_RELOC_LARCH_ADD64/32 and BFD_RELOC_LARCH_SUB64/32 here.
+       Then will parse howto table bfd_reloc_code_real_type to generate
+       R_LARCH_ADD64/32 and R_LARCH_SUB64/32 reloc at tc_gen_reloc functio=
n.
+       If only fx_addsy not null, skip here directly, then generate
+       R_LARCH_64/32.
+
+       For BFD_RELOC_24/16/8, if fx_addsy and fx_subsy not null, wer need
+       generate BFD_RELOC_LARCH_ADD24/16/8 and BFD_RELOC_LARCH_SUB24/16/8 =
here.
+       Then will parse howto table bfd_reloc_code_real_type to generate
+       R_LARCH_ADD24/16/8 and R_LARCH_SUB24/16/8 reloc at tc_gen_reloc
+       function. If only fx_addsy not null, we generate
+       BFD_RELOC_LARCH_ADD24/16/8 only, then generate R_LARCH_24/16/8.
+       To avoid R_LARCH_ADDxx add extra value, we write 0 first
+       (use md_number_to_chars (buf, 0, fixP->fx_size)).
+    */
     case BFD_RELOC_64:
     case BFD_RELOC_32:
       if (fixP->fx_r_type =3D=3D BFD_RELOC_32
@@ -1151,7 +1218,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTR=
IBUTE_UNUSED)
 	  break;
 	}
=20
-      if (fixP->fx_subsy)
+      if (fixP->fx_addsy && fixP->fx_subsy)
 	{
 	  fixP->fx_next =3D xmemdup (fixP, sizeof (*fixP), sizeof (*fixP));
 	  fixP->fx_next->fx_addsy =3D fixP->fx_subsy;
@@ -1186,34 +1253,37 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg AT=
TRIBUTE_UNUSED)
     case BFD_RELOC_24:
     case BFD_RELOC_16:
     case BFD_RELOC_8:
-      fixP->fx_next =3D xmemdup (fixP, sizeof (*fixP), sizeof (*fixP));
-      fixP->fx_next->fx_addsy =3D fixP->fx_subsy;
-      fixP->fx_next->fx_subsy =3D NULL;
-      fixP->fx_next->fx_offset =3D 0;
-      fixP->fx_subsy =3D NULL;
-
-      switch (fixP->fx_r_type)
+      if (fixP->fx_addsy)
 	{
-	case BFD_RELOC_24:
-	  fixP->fx_r_type =3D BFD_RELOC_LARCH_ADD24;
-	  fixP->fx_next->fx_r_type =3D BFD_RELOC_LARCH_SUB24;
-	  break;
-	case BFD_RELOC_16:
-	  fixP->fx_r_type =3D BFD_RELOC_LARCH_ADD16;
-	  fixP->fx_next->fx_r_type =3D BFD_RELOC_LARCH_SUB16;
-	  break;
-	case BFD_RELOC_8:
-	  fixP->fx_r_type =3D BFD_RELOC_LARCH_ADD8;
-	  fixP->fx_next->fx_r_type =3D BFD_RELOC_LARCH_SUB8;
-	  break;
-	default:
-	  break;
-	}
+	  fixP->fx_next =3D xmemdup (fixP, sizeof (*fixP), sizeof (*fixP));
+	  fixP->fx_next->fx_addsy =3D fixP->fx_subsy;
+	  fixP->fx_next->fx_subsy =3D NULL;
+	  fixP->fx_next->fx_offset =3D 0;
+	  fixP->fx_subsy =3D NULL;
=20
-      md_number_to_chars (buf, 0, fixP->fx_size);
+	  switch (fixP->fx_r_type)
+	    {
+	    case BFD_RELOC_24:
+	      fixP->fx_r_type =3D BFD_RELOC_LARCH_ADD24;
+	      fixP->fx_next->fx_r_type =3D BFD_RELOC_LARCH_SUB24;
+	      break;
+	    case BFD_RELOC_16:
+	      fixP->fx_r_type =3D BFD_RELOC_LARCH_ADD16;
+	      fixP->fx_next->fx_r_type =3D BFD_RELOC_LARCH_SUB16;
+	      break;
+	    case BFD_RELOC_8:
+	      fixP->fx_r_type =3D BFD_RELOC_LARCH_ADD8;
+	      fixP->fx_next->fx_r_type =3D BFD_RELOC_LARCH_SUB8;
+	      break;
+	    default:
+	      break;
+	    }
+
+	  md_number_to_chars (buf, 0, fixP->fx_size);
=20
-      if (fixP->fx_next->fx_addsy =3D=3D NULL)
-	fixP->fx_next->fx_done =3D 1;
+	  if (fixP->fx_next->fx_addsy =3D=3D NULL)
+	    fixP->fx_next->fx_done =3D 1;
+	}
=20
       if (fixP->fx_addsy =3D=3D NULL)
 	{
@@ -1222,6 +1292,67 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATT=
RIBUTE_UNUSED)
 	}
       break;
=20
+    case BFD_RELOC_LARCH_CFA:
+      if (fixP->fx_addsy && fixP->fx_subsy)
+	{
+	  fixP->fx_next =3D xmemdup (fixP, sizeof (*fixP), sizeof (*fixP));
+	  fixP->fx_next->fx_addsy =3D fixP->fx_subsy;
+	  fixP->fx_next->fx_subsy =3D NULL;
+	  fixP->fx_next->fx_offset =3D 0;
+	  fixP->fx_subsy =3D NULL;
+
+	  unsigned int subtype;
+	  offsetT loc;
+	  subtype =3D bfd_get_8 (NULL, &((fragS *)
+		      (fixP->fx_frag->fr_opcode))->fr_literal[fixP->fx_where]);
+	  loc =3D fixP->fx_frag->fr_fix - (subtype & 7);
+	  switch (subtype)
+	    {
+	    case DW_CFA_advance_loc1:
+	      fixP->fx_where =3D loc + 1;
+	      fixP->fx_next->fx_where =3D loc + 1;
+	      fixP->fx_r_type =3D BFD_RELOC_LARCH_ADD8;
+	      fixP->fx_next->fx_r_type =3D BFD_RELOC_LARCH_SUB8;
+	      md_number_to_chars (buf+1, 0, fixP->fx_size);
+	      break;
+
+	    case DW_CFA_advance_loc2:
+	      fixP->fx_size =3D 2;
+	      fixP->fx_next->fx_size =3D 2;
+	      fixP->fx_where =3D loc + 1;
+	      fixP->fx_next->fx_where =3D loc + 1;
+	      fixP->fx_r_type =3D BFD_RELOC_LARCH_ADD16;
+	      fixP->fx_next->fx_r_type =3D BFD_RELOC_LARCH_SUB16;
+	      md_number_to_chars (buf+1, 0, fixP->fx_size);
+	      break;
+
+	    case DW_CFA_advance_loc4:
+	      fixP->fx_size =3D 4;
+	      fixP->fx_next->fx_size =3D 4;
+	      fixP->fx_where =3D loc;
+	      fixP->fx_next->fx_where =3D loc;
+	      fixP->fx_r_type =3D BFD_RELOC_LARCH_ADD32;
+	      fixP->fx_next->fx_r_type =3D BFD_RELOC_LARCH_SUB32;
+	      md_number_to_chars (buf+1, 0, fixP->fx_size);
+	      break;
+
+	    default:
+	      if (subtype < 0x80 && (subtype & 0x40))
+		{
+		  /* DW_CFA_advance_loc.  */
+		  fixP->fx_frag =3D (fragS *) fixP->fx_frag->fr_opcode;
+		  fixP->fx_next->fx_frag =3D fixP->fx_frag;
+		  fixP->fx_r_type =3D BFD_RELOC_LARCH_ADD6;
+		  fixP->fx_next->fx_r_type =3D BFD_RELOC_LARCH_SUB6;
+		  md_number_to_chars (buf, 0x40, fixP->fx_size);
+		  }
+	      else
+		as_fatal (_("internal: bad CFA value #%d"), subtype);
+	      break;
+	    }
+	}
+      break;
+
     case BFD_RELOC_LARCH_B16:
     case BFD_RELOC_LARCH_B21:
     case BFD_RELOC_LARCH_B26:
@@ -1236,11 +1367,28 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg AT=
TRIBUTE_UNUSED)
 	  int64_t sym_addend =3D S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset;
 	  int64_t pc =3D fixP->fx_where + fixP->fx_frag->fr_address;
 	  fix_reloc_insn (fixP, sym_addend - pc, buf);
-	  fixP->fx_done =3D 1;
-	}
=20
+	  /* If relax, symbol value may change at link time, so reloc need to
+	     be saved.  */
+	  if (!LARCH_opts.relax)
+	    fixP->fx_done =3D 1;
+	}
       break;
=20
+    /* Because ADD_ULEB128/SUB_ULEB128 always occur in pairs.
+       So just deal with one is ok.
+    case BFD_RELOC_LARCH_ADD_ULEB128:  */
+    case BFD_RELOC_LARCH_SUB_ULEB128:
+      {
+	unsigned int len =3D 0;
+	_bfd_read_unsigned_leb128 (NULL, (bfd_byte *)buf, &len);
+	bfd_byte *endp =3D (bfd_byte*) buf + len -1;
+	/* Clean the uleb128 value to 0. Do not reduce the length.  */
+	memset (buf, 0x80, len - 1);
+	*endp =3D 0;
+	break;
+      }
+
     default:
       break;
     }
@@ -1258,34 +1406,7 @@ int
 md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED,
 			       asection *segtype ATTRIBUTE_UNUSED)
 {
-  return 0;
-}
-
-int
-loongarch_fix_adjustable (fixS *fix)
-{
-  /* Prevent all adjustments to global symbols.  */
-  if (S_IS_EXTERNAL (fix->fx_addsy)
-      || S_IS_WEAK (fix->fx_addsy)
-      || S_FORCE_RELOC (fix->fx_addsy, true))
-    return 0;
-
-  /* Loongarch loads extern symbols by GOT, and if there are embedded
-     asm(".local S"), gcc just output ".local S" to assembly file.
-     For a local symbol with GOT relocations, this adjustments will make
-     GOT relocation's addend not equal to zero. So this adjustments is
-     forbidden for got relocs.  */
-  if(fix->fx_r_type =3D=3D BFD_RELOC_LARCH_GOT_PC_HI20
-      || fix->fx_r_type =3D=3D BFD_RELOC_LARCH_GOT_PC_LO12
-      || fix->fx_r_type =3D=3D BFD_RELOC_LARCH_GOT64_PC_LO20
-      || fix->fx_r_type =3D=3D BFD_RELOC_LARCH_GOT64_PC_HI12
-      || fix->fx_r_type =3D=3D BFD_RELOC_LARCH_GOT_HI20
-      || fix->fx_r_type =3D=3D BFD_RELOC_LARCH_GOT_LO12
-      || fix->fx_r_type =3D=3D BFD_RELOC_LARCH_GOT64_LO20
-      || fix->fx_r_type =3D=3D BFD_RELOC_LARCH_GOT64_HI12)
-    return 0;
-
-  return 1;
+  return (fragp->fr_var =3D 4);
 }
=20
 /* Translate internal representation of relocation info to BFD target
@@ -1315,9 +1436,25 @@ tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fi=
xS *fixp)
 /* Convert a machine dependent frag.  */
 void
 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec ATTRIBUTE_UNUSED,
-		 fragS *fragp ATTRIBUTE_UNUSED)
+		 fragS *fragp)
 {
-  /* fragp->fr_fix +=3D 8; */
+  expressionS exp;
+  exp.X_op =3D O_symbol;
+  exp.X_add_symbol =3D fragp->fr_symbol;
+  exp.X_add_number =3D fragp->fr_offset;
+  bfd_byte *buf =3D (bfd_byte *)fragp->fr_literal + fragp->fr_fix;
+
+  fixS *fixp =3D fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
+				4, &exp, false, fragp->fr_subtype);
+  buf +=3D 4;
+
+  fixp->fx_file =3D fragp->fr_file;
+  fixp->fx_line =3D fragp->fr_line;
+  fragp->fr_fix +=3D fragp->fr_var;
+
+  gas_assert (fragp->fr_next =3D=3D NULL
+	      || (fragp->fr_next->fr_address - fragp->fr_address
+		  =3D=3D fragp->fr_fix));
 }
=20
 /* Standard calling conventions leave the CFA at SP on entry.  */
@@ -1327,6 +1464,48 @@ loongarch_cfi_frame_initial_instructions (void)
   cfi_add_CFA_def_cfa_register (3 /* $sp */);
 }
=20
+void
+loongarch_pre_output_hook (void)
+{
+  const frchainS *frch;
+  segT s;
+
+  /* Save the current segment info.  */
+  segT seg =3D now_seg;
+  subsegT subseg =3D now_subseg;
+
+  for (s =3D stdoutput->sections; s; s =3D s->next)
+    for (frch =3D seg_info (s)->frchainP; frch; frch =3D frch->frch_next)
+      {
+	fragS *frag;
+
+	for (frag =3D frch->frch_root; frag; frag =3D frag->fr_next)
+	  {
+	    if (frag->fr_type =3D=3D rs_cfa)
+	      {
+		expressionS exp;
+		expressionS *symval;
+
+		symval =3D symbol_get_value_expression (frag->fr_symbol);
+		exp.X_op =3D O_subtract;
+		exp.X_add_symbol =3D symval->X_add_symbol;
+		exp.X_add_number =3D 0;
+		exp.X_op_symbol =3D symval->X_op_symbol;
+
+		/* We must set the segment before creating a frag after all
+		   frag chains have been chained together.  */
+		subseg_set (s, frch->frch_subseg);
+
+		fix_new_exp (frag, (int) frag->fr_offset, 1, &exp, 0,
+			     BFD_RELOC_LARCH_CFA);
+	      }
+	  }
+      }
+
+  /* Restore the original segment info.  */
+  subseg_set (seg, subseg);
+}
+
 void
 tc_loongarch_parse_to_dw2regnum (expressionS *exp)
 {
@@ -1340,6 +1519,58 @@ md_show_usage (FILE *stream)
   /* FIXME */
 }
=20
+static void
+loongarch_make_nops (char *buf, bfd_vma bytes)
+{
+  bfd_vma i =3D 0;
+
+  /* Fill with 4-byte NOPs.  */
+  for ( ; i < bytes; i +=3D 4)
+    number_to_chars_littleendian (buf + i, LARCH_NOP, 4);
+}
+
+/* Called from md_do_align.  Used to create an alignment frag in a
+   code section by emitting a worst-case NOP sequence that the linker
+   will later relax to the correct number of NOPs.  We can't compute
+   the correct alignment now because of other linker relaxations.  */
+
+bool
+loongarch_frag_align_code (int n)
+{
+  bfd_vma bytes =3D (bfd_vma) 1 << n;
+  bfd_vma insn_alignment =3D 4;
+  bfd_vma worst_case_bytes =3D bytes - insn_alignment;
+  char *nops;
+  expressionS ex;
+
+  /* If we are moving to a smaller alignment than the instruction size, th=
en no
+     alignment is required.  */
+  if (bytes <=3D insn_alignment)
+    return true;
+
+  /* When not relaxing, loongarch_handle_align handles code alignment.  */
+  if (!LARCH_opts.relax)
+    return false;
+
+  nops =3D frag_more (worst_case_bytes);
+
+  ex.X_op =3D O_constant;
+  ex.X_add_number =3D worst_case_bytes;
+
+  loongarch_make_nops (nops, worst_case_bytes);
+
+  fix_new_exp (frag_now, nops - frag_now->fr_literal, 0,
+	       &ex, false, BFD_RELOC_LARCH_ALIGN);
+
+  /* We need to start a new frag after the alignment which may be removed =
by
+     the linker, to prevent the assembler from computing static offsets.
+     This is necessary to get correct EH info.  */
+  frag_wane (frag_now);
+  frag_new (0);
+
+  return true;
+}
+
 /* Fill in an rs_align_code fragment.  We want to fill 'andi $r0,$r0,0'.  =
*/
 void
 loongarch_handle_align (fragS *fragp)
@@ -1375,6 +1606,68 @@ loongarch_handle_align (fragS *fragp)
   fragp->fr_var =3D size;
 }
=20
+/* Scan uleb128 subtraction expressions and insert fixups for them.
+   e.g., .uleb128 .L1 - .L0
+   Because relaxation may change the value of the subtraction, we
+   must resolve them at link-time.  */
+
+static void
+loongarch_insert_uleb128_fixes (bfd *abfd ATTRIBUTE_UNUSED,
+		      asection *sec, void *xxx ATTRIBUTE_UNUSED)
+{
+  segment_info_type *seginfo =3D seg_info (sec);
+  struct frag *fragP;
+
+  subseg_set (sec, 0);
+
+  for (fragP =3D seginfo->frchainP->frch_root;
+       fragP; fragP =3D fragP->fr_next)
+    {
+      expressionS *exp, *exp_dup;
+
+      if (fragP->fr_type !=3D rs_leb128  || fragP->fr_symbol =3D=3D NULL)
+	continue;
+
+      exp =3D symbol_get_value_expression (fragP->fr_symbol);
+
+      if (exp->X_op !=3D O_subtract)
+	continue;
+
+      /* FIXME: Skip for .sleb128.  */
+      if (fragP->fr_subtype !=3D 0)
+	continue;
+
+      exp_dup =3D xmemdup (exp, sizeof (*exp), sizeof (*exp));
+      exp_dup->X_op =3D O_symbol;
+      exp_dup->X_op_symbol =3D NULL;
+
+      exp_dup->X_add_symbol =3D exp->X_add_symbol;
+      fix_new_exp (fragP, fragP->fr_fix, 0,
+		   exp_dup, 0, BFD_RELOC_LARCH_ADD_ULEB128);
+
+      /* From binutils/testsuite/binutils-all/dw5.S
+	 section .debug_rnglists
+	 .uleb128 .Letext0-.Ltext0    Range length (*.LLRL2)
+    Offset             Info             Type               Symbol's Value =
 Symbol's Name + Addend
+0000000000000015  0000000200000079 R_LARCH_ADD_ULEB128    0000000000000000=
 .text + 2
+0000000000000015  000000020000007a R_LARCH_SUB_ULEB128    0000000000000000=
 .text + 0.  */
+
+      /* Only the ADD_ULEB128 has X_add_number (Addend)?  */
+      exp_dup->X_add_number =3D 0;
+      exp_dup->X_add_symbol =3D exp->X_op_symbol;
+      fix_new_exp (fragP, fragP->fr_fix, 0,
+		   exp_dup, 0, BFD_RELOC_LARCH_SUB_ULEB128);
+    }
+}
+
+void
+loongarch_md_finish (void)
+{
+  /* Insert relocations for uleb128 directives, so the values can be recom=
puted
+     at link time.  */
+  bfd_map_over_sections (stdoutput, loongarch_insert_uleb128_fixes, NULL);
+}
+
 void
 loongarch_elf_final_processing (void)
 {
diff --git a/gas/config/tc-loongarch.h b/gas/config/tc-loongarch.h
index c75a8192cb0..8517bdebf13 100644
--- a/gas/config/tc-loongarch.h
+++ b/gas/config/tc-loongarch.h
@@ -47,16 +47,45 @@ extern int loongarch_relax_frag (asection *, struct fra=
g *, long);
 #define md_undefined_symbol(name) (0)
 #define md_operand(x)
=20
-/* This is called to see whether a reloc against a defined symbol
+extern bool loongarch_frag_align_code (int);
+#define md_do_align(N, FILL, LEN, MAX, LABEL)				\
+  if ((N) !=3D 0 && !(FILL) && !need_pass_2 && subseg_text_p (now_seg))	\
+    {									\
+      if (loongarch_frag_align_code (N))				\
+	goto LABEL;							\
+    }
+
+/* The following two macros let the linker resolve all the relocs
+   due to relaxation.
+   This is called to see whether a reloc against a defined symbol
    should be converted into a reloc against a section.  */
-extern int loongarch_fix_adjustable (struct fix *fix);
-#define tc_fix_adjustable(fixp) loongarch_fix_adjustable(fixp)
+#define tc_fix_adjustable(fixp) 0
+/* The difference between same-section symbols may be affected by linker
+   relaxation, so do not resolve such expressions in the assembler.  */
+#define md_allow_local_subtract(l,r,s) 0
=20
 /* Values passed to md_apply_fix don't include symbol values.  */
 #define TC_FORCE_RELOCATION_SUB_LOCAL(FIX, SEG) 1
 #define TC_VALIDATE_FIX_SUB(FIX, SEG) 1
 #define DIFF_EXPR_OK 1
=20
+#define TC_FORCE_RELOCATION_SUB_SAME(FIX, SEC)	\
+  (GENERIC_FORCE_RELOCATION_SUB_SAME (FIX, SEC)	\
+   || ((SEC)->flags & SEC_CODE) !=3D 0		\
+   || ((SEC)->flags & SEC_DEBUGGING) !=3D 0	\
+   || TC_FORCE_RELOCATION (FIX))
+
+#define TC_LINKRELAX_FIXUP(seg) ((seg->flags & SEC_CODE)  \
+				    || (seg->flags & SEC_DEBUGGING))
+
+#define TC_FORCE_RELOCATION_LOCAL(FIX) 1
+
+/* Adjust debug_line after relaxation.  */
+#define DWARF2_USE_FIXED_ADVANCE_PC 1
+
+/* Values passed to md_apply_fix don't include symbol values.  */
+#define MD_APPLY_SYM_VALUE(FIX) 0
+
 #define TARGET_USE_CFIPOP 1
 #define DWARF2_DEFAULT_RETURN_COLUMN 1 /* $ra.  */
 #define DWARF2_CIE_DATA_ALIGNMENT -4
@@ -65,13 +94,15 @@ extern int loongarch_fix_adjustable (struct fix *fix);
   loongarch_cfi_frame_initial_instructions
 extern void loongarch_cfi_frame_initial_instructions (void);
=20
+#define tc_symbol_new_hook(sym) \
+  if (0 =3D=3D strcmp (sym->bsym->name, FAKE_LABEL_NAME)) \
+    S_SET_OTHER (sym, STV_HIDDEN);
+
 #define tc_parse_to_dw2regnum tc_loongarch_parse_to_dw2regnum
 extern void tc_loongarch_parse_to_dw2regnum (expressionS *);
=20
-/* A enumerated values to specific how to deal with align in '.text'.
-   Now we want to fill 'andi $r0,$r0,0x0'.
-   Here is the type 0, will fill andi insn later.  */
-#define NOP_OPCODE (0x00)
+extern void loongarch_pre_output_hook (void);
+#define md_pre_output_hook loongarch_pre_output_hook ()
=20
 #define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 0
=20
@@ -90,4 +121,7 @@ struct reloc_info
   expressionS value;
 };
=20
+#define md_finish loongarch_md_finish
+extern void loongarch_md_finish (void);
+
 #endif
diff --git a/gas/testsuite/gas/all/align.d b/gas/testsuite/gas/all/align.d
index c701f25bfcc..43c1413de04 100644
--- a/gas/testsuite/gas/all/align.d
+++ b/gas/testsuite/gas/all/align.d
@@ -3,8 +3,9 @@
 # The RX port will always replace zeros in any aligned area with NOPs,
 # even if the user requested that they filled with zeros.
 # RISC-V handles alignment via relaxation and therefor won't have object f=
iles
-# with the expected alignment.
-#notarget: riscv*-* rx-*
+# LoongArch handles alignment via relaxation and therefor won't have object
+# files with the expected alignment.
+#notarget: loongarch*-* riscv*-* rx-*
=20
 # Test the alignment pseudo-op.
=20
diff --git a/gas/testsuite/gas/all/gas.exp b/gas/testsuite/gas/all/gas.exp
index b7f583580e7..bab5a6c7ba5 100644
--- a/gas/testsuite/gas/all/gas.exp
+++ b/gas/testsuite/gas/all/gas.exp
@@ -67,14 +67,14 @@ if {    ![istarget alpha*-*-*vms*]
      && ![istarget ft32-*-*]
      && ![istarget hppa*-*-*]
      && ![istarget microblaze-*-*]
+     && ![istarget loongarch*-*-*]
      && ![istarget mn10300-*-*]
      && ![istarget msp430*-*-*]
      && ![istarget powerpc*-*-aix*]
      && ![istarget riscv*-*-*]
      && ![istarget rl78-*-*]
      && ![istarget rs6000*-*-aix*]
-     && ![istarget rx-*-*]
-     && ![istarget loongarch*-*-*] } then {
+     && ![istarget rx-*-*] } then {
     gas_test_error "diff1.s" "" "difference of two undefined symbols"
 }
=20
@@ -165,11 +165,11 @@ switch -glob $target_triplet {
 	# These targets fail redef2 because they disallow redefined
 	# symbols on relocs.
 	setup_xfail "m68hc1*-*-*" "m6811-*-*" "m6812-*-*" "rl78-*-*"
-	setup_xfail "riscv*-*-*" "rx-*-*" "vax*-*-*" "xgate*-*-*" "z8k-*-*"
+	setup_xfail "loongarch*-*-*" "riscv*-*-*" "rx-*-*" "vax*-*-*" "xgate*-*-*=
" "z8k-*-*"
 	setup_xfail "avr-*-*"
 	run_dump_test redef2
 	setup_xfail "m68hc1*-*-*" "m6811-*-*" "m6812-*-*" "rl78-*-*"
-	setup_xfail "riscv*-*-*" "rx-*-*" "vax*-*-*" "xgate*-*-*" "z8k-*-*"
+	setup_xfail "loongarch*-*-*" "riscv*-*-*" "rx-*-*" "vax*-*-*" "xgate*-*-*=
" "z8k-*-*"
 	setup_xfail "avr-*-*"
 	# rs6000-aix disallows redefinition via .comm.
 	if [is_xcoff_format] {
@@ -279,7 +279,7 @@ if {    ![istarget *c30*-*-*]
      && ![istarget h8300*-*-*]
      && ![istarget hppa*-*-*] } then {
     # msp430, mn10[23]00 and riscv emit two relocs to handle the differenc=
e of two symbols.
-    setup_xfail "am3*-*-*" "mn10200-*-*" "mn10300*-*-*" "msp430*-*-*" "ris=
cv*-*-*"
+    setup_xfail "am3*-*-*" "loongarch*-*-*" "mn10200-*-*" "mn10300*-*-*" "=
msp430*-*-*" "riscv*-*-*"
     do_930509a
 }
=20
diff --git a/gas/testsuite/gas/all/relax.d b/gas/testsuite/gas/all/relax.d
index f394043b017..00fba6d62cd 100644
--- a/gas/testsuite/gas/all/relax.d
+++ b/gas/testsuite/gas/all/relax.d
@@ -4,6 +4,10 @@
 # because symbol values are not known until after linker relaxation has be=
en
 # performed.
 #notarget : riscv*-*-*
+# LoongArch doesn't resolve .uleb operands that are the difference of two
+# symbols because gas write zero to object file and generate add_uleb128 a=
nd
+# sub_uleb128 reloc pair.
+#xfail: loongarch*-*-*
=20
 .*: .*
=20
diff --git a/gas/testsuite/gas/elf/dwarf-5-irp.d b/gas/testsuite/gas/elf/dw=
arf-5-irp.d
index 048a6d5a87a..6bcdc6636a6 100644
--- a/gas/testsuite/gas/elf/dwarf-5-irp.d
+++ b/gas/testsuite/gas/elf/dwarf-5-irp.d
@@ -5,7 +5,8 @@
 # The bfin target does not allow .subsection with an equated symbol as ope=
rand.
 # The d30v target emits sufficiently different debug info, apparently also=
 covering padding it inserts.
 # The riscv targets do not support the subtraction of symbols.
-#xfail: am33*-* bfin-* cr16-* crx-* d30v-* ft32-* mn10*-* msp430-* nds32*-=
* riscv*-* rl78-*
+# The loongarch targets do not support the subtraction of symbols.
+#xfail: am33*-* bfin-* cr16-* crx-* d30v-* ft32-* loongarch*-* mn10*-* msp=
430-* nds32*-* riscv*-* rl78-*
=20
 Raw dump of debug contents .*
 #...
diff --git a/gas/testsuite/gas/elf/dwarf-5-loc0.d b/gas/testsuite/gas/elf/d=
warf-5-loc0.d
index 9439d103b1f..9338271c0eb 100644
--- a/gas/testsuite/gas/elf/dwarf-5-loc0.d
+++ b/gas/testsuite/gas/elf/dwarf-5-loc0.d
@@ -3,7 +3,8 @@
 #name: DWARF5 .loc 0
 # The am33 cr16 crx ft32 mn10 msp430 nds32 and rl78 targets do not evaluat=
e the subtraction of symbols at assembly time.
 # The riscv targets do not support the subtraction of symbols.
-#xfail: am3*-* cr16-* crx-* ft32*-* mn10*-* msp430-* nds32*-* riscv*-* rl7=
8-*
+# The loongarch targets do not support the subtraction of symbols.
+#xfail: am3*-* cr16-* crx-* ft32*-* loongarch*-* mn10*-* msp430-* nds32*-*=
 riscv*-* rl78-*
=20
 Contents of the \.debug_line section:
=20
diff --git a/gas/testsuite/gas/elf/dwarf-5-macro-include.d b/gas/testsuite/=
gas/elf/dwarf-5-macro-include.d
index 32ea6386992..c39425aa8c9 100644
--- a/gas/testsuite/gas/elf/dwarf-5-macro-include.d
+++ b/gas/testsuite/gas/elf/dwarf-5-macro-include.d
@@ -4,7 +4,7 @@
 # The am33 cr16 crx ft32 mn10* msp430 nds32* and rl78 targets do not evalu=
ate the subtraction of symbols at assembly time.
 # The d30v target emits sufficiently different debug info, apparently also=
 covering padding it inserts.
 # The riscv targets do not support the subtraction of symbols.
-#xfail: am33*-* cr16-* crx-* d30v-* ft32-* mn10*-* msp430-* nds32*-* riscv=
*-* rl78-*
+#xfail: am33*-* cr16-* crx-* d30v-* ft32-* loongarch*-* mn10*-* msp430-* n=
ds32*-* riscv*-* rl78-*
=20
 Raw dump of debug contents .*
 #...
diff --git a/gas/testsuite/gas/elf/dwarf-5-macro.d b/gas/testsuite/gas/elf/=
dwarf-5-macro.d
index 794e17a575e..b2613bd1c16 100644
--- a/gas/testsuite/gas/elf/dwarf-5-macro.d
+++ b/gas/testsuite/gas/elf/dwarf-5-macro.d
@@ -4,7 +4,7 @@
 # The am33 cr16 crx ft32 mn10* msp430 nds32* and rl78 targets do not evalu=
ate the subtraction of symbols at assembly time.
 # The d30v target emits sufficiently different debug info, apparently also=
 covering padding it inserts.
 # The riscv targets do not support the subtraction of symbols.
-#xfail: am33*-* cr16-* crx-* d30v-* ft32-* mn10*-* msp430-* nds32*-* riscv=
*-* rl78-*
+#xfail: am33*-* cr16-* crx-* d30v-* ft32-* loongarch*-* mn10*-* msp430-* n=
ds32*-* riscv*-* rl78-*
=20
 Raw dump of debug contents .*
 #...
diff --git a/gas/testsuite/gas/elf/dwarf2-11.d b/gas/testsuite/gas/elf/dwar=
f2-11.d
index 2c30e55c695..44f5cd18ec6 100644
--- a/gas/testsuite/gas/elf/dwarf2-11.d
+++ b/gas/testsuite/gas/elf/dwarf2-11.d
@@ -3,7 +3,8 @@
 #name: DWARF2 11
 # The am33 cr16 crx ft32 mn10 msp430 nds32 and rl78 targets do not evaluat=
e the subtraction of symbols at assembly time.
 # The riscv targets do not support the subtraction of symbols.
-#xfail: am3*-* cr16-* crx-* ft32*-* mn10*-* msp430-* nds32*-* riscv*-* rl7=
8-*
+# The loongarch targets do not support the subtraction of symbols.
+#xfail: am3*-* cr16-* crx-* ft32*-* loongarch*-* mn10*-* msp430-* nds32*-*=
 riscv*-* rl78-*
=20
 Contents of the \.debug_line section:
=20
diff --git a/gas/testsuite/gas/elf/dwarf2-15.d b/gas/testsuite/gas/elf/dwar=
f2-15.d
index 939c61598cb..3ec9f2785a7 100644
--- a/gas/testsuite/gas/elf/dwarf2-15.d
+++ b/gas/testsuite/gas/elf/dwarf2-15.d
@@ -3,7 +3,8 @@
 #name: DWARF2 15
 # The am33 cr16 crx ft32 mn10 msp430 nds32 and rl78 targets do not evaluat=
e the subtraction of symbols at assembly time.
 # The riscv targets do not support the subtraction of symbols.
-#xfail: am3*-* cr16-* crx-* ft32*-* mn10*-* msp430-* nds32*-* riscv*-* rl7=
8-*
+# The loongarch targets do not support the subtraction of symbols.
+#xfail: am3*-* cr16-* crx-* ft32*-* loongarch*-* mn10*-* msp430-* nds32*-*=
 riscv*-* rl78-*
=20
 Hex dump of section '\.rodata':
   0x00000000 01 *.*
diff --git a/gas/testsuite/gas/elf/dwarf2-16.d b/gas/testsuite/gas/elf/dwar=
f2-16.d
index 8e35d493619..32b57763137 100644
--- a/gas/testsuite/gas/elf/dwarf2-16.d
+++ b/gas/testsuite/gas/elf/dwarf2-16.d
@@ -4,7 +4,8 @@
 # The am33 cr16 crx ft32 mn10 msp430 nds32 and rl78 targets do not evaluat=
e the subtraction of symbols at assembly time.
 # The mep target tries to relay code sections which breaks symbolic view c=
omputations.
 # The riscv targets do not support the subtraction of symbols.
-#xfail: am3*-* cr16-* crx-* ft32*-* mep-* mn10*-* msp430-* nds32*-* riscv*=
-* rl78-*
+# The loongarch targets do not support the subtraction of symbols.
+#xfail: am3*-* cr16-* crx-* ft32*-* mep-* loongarch*-* mn10*-* msp430-* nd=
s32*-* riscv*-* rl78-*
=20
 Hex dump of section '\.rodata':
   0x00000000 01 *.*
diff --git a/gas/testsuite/gas/elf/dwarf2-17.d b/gas/testsuite/gas/elf/dwar=
f2-17.d
index 881477cf95b..4c2f2e3999e 100644
--- a/gas/testsuite/gas/elf/dwarf2-17.d
+++ b/gas/testsuite/gas/elf/dwarf2-17.d
@@ -4,7 +4,8 @@
 # The am33 cr16 crx ft32 mn10 msp430 nds32 and rl78 targets do not evaluat=
e the subtraction of symbols at assembly time.
 # The mep target tries to relay code sections which breaks symbolic view c=
omputations.
 # The riscv targets do not support the subtraction of symbols.
-#xfail: am3*-* cr16-* crx-* ft32*-* mep-* mn10*-* msp430-* nds32*-* riscv*=
-* rl78-*
+# The loongarch targets do not support the subtraction of symbols.
+#xfail: am3*-* cr16-* crx-* ft32*-* loongarch*-* mep-* mn10*-* msp430-* nd=
s32*-* riscv*-* rl78-*
=20
 Hex dump of section '\.rodata':
   0x00000000 00 *.*
diff --git a/gas/testsuite/gas/elf/dwarf2-18.d b/gas/testsuite/gas/elf/dwar=
f2-18.d
index fbaebaa9019..18157c634a5 100644
--- a/gas/testsuite/gas/elf/dwarf2-18.d
+++ b/gas/testsuite/gas/elf/dwarf2-18.d
@@ -3,7 +3,8 @@
 #name: DWARF2 18
 # The am33 cr16 crx ft32 mn10 msp430 nds32 and rl78 targets do not evaluat=
e the subtraction of symbols at assembly time.
 # The riscv targets do not support the subtraction of symbols.
-#xfail: am3*-* cr16-* crx-* ft32*-* mn10*-* msp430-* nds32*-* riscv*-* rl7=
8-*
+# The loongarch targets do not support the subtraction of symbols.
+#xfail: am3*-* cr16-* crx-* ft32*-* loongarch*-* mn10*-* msp430-* nds32*-*=
 riscv*-* rl78-*
=20
 Hex dump of section '\.rodata':
   0x00000000 0100 *.*
diff --git a/gas/testsuite/gas/elf/dwarf2-19.d b/gas/testsuite/gas/elf/dwar=
f2-19.d
index 55d0caf4cb1..133294affe7 100644
--- a/gas/testsuite/gas/elf/dwarf2-19.d
+++ b/gas/testsuite/gas/elf/dwarf2-19.d
@@ -4,7 +4,8 @@
 # The am33 cr16 crx ft32 mn10 msp430 nds32 and rl78 targets do not evaluat=
e the subtraction of symbols at assembly time.
 # The mep targets turns some view computations into complex relocations.
 # The riscv targets do not support the subtraction of symbols.
-#xfail: am3*-* cr16-* crx-* ft32*-* mep-* mn10*-* msp430-* nds32*-* riscv*=
-* rl78-*
+# The loongarch targets do not support the subtraction of symbols.
+#xfail: am3*-* cr16-* crx-* ft32*-* mep-* loongarch*-* mn10*-* msp430-* nd=
s32*-* riscv*-* rl78-*
=20
 Hex dump of section '\.rodata':
   0x00000000 01000102 *.*
diff --git a/gas/testsuite/gas/elf/dwarf2-5.d b/gas/testsuite/gas/elf/dwarf=
2-5.d
index ced12e7c0c7..886f1a13389 100644
--- a/gas/testsuite/gas/elf/dwarf2-5.d
+++ b/gas/testsuite/gas/elf/dwarf2-5.d
@@ -4,7 +4,8 @@
 # The am33 cr16 crx ft32 mn10 msp430 nds32 rl78 and rx targets do not eval=
uate the subtraction of symbols at assembly time.
 # The mep target tries to relay code sections which breaks symbolic view c=
omputations.
 # The riscv targets do not support the subtraction of symbols.
-#xfail: am3*-* cr16-* crx-* ft32*-* mep-* mn10*-* msp430-* nds32*-* riscv*=
-* rl78-* rx-*
+# The loongarch targets do not support the subtraction of symbols.
+#xfail: am3*-* cr16-* crx-* ft32*-* loongarch*-* mep-* mn10*-* msp430-* nd=
s32*-* riscv*-* rl78-* rx-*
=20
 Hex dump of section '\.rodata':
   0x00000000 01010201 010203 *.*
diff --git a/gas/testsuite/gas/elf/ehopt0.d b/gas/testsuite/gas/elf/ehopt0.d
index a13c4f26e33..64c5fb5ddc4 100644
--- a/gas/testsuite/gas/elf/ehopt0.d
+++ b/gas/testsuite/gas/elf/ehopt0.d
@@ -1,5 +1,8 @@
 #objdump: -s -j .eh_frame
 #name: elf ehopt0=20
+# The loongarch target do not evaluate .eh_frame fde cfa advance loc at as=
sembly time.
+# Because loongarch use add/sub reloc evaluate cfa advance loc, so gas sho=
uld write 0 to cfa advance loc address.
+#xfail: loongarch*-*
=20
 .*: +file format .*
=20
diff --git a/gas/testsuite/gas/elf/elf.exp b/gas/testsuite/gas/elf/elf.exp
index e2741353c61..4890dd93420 100644
--- a/gas/testsuite/gas/elf/elf.exp
+++ b/gas/testsuite/gas/elf/elf.exp
@@ -72,6 +72,9 @@ if { [is_elf_format] } then {
     if {[istarget "csky*-*-*"]} {
 	set target_machine -csky
     }
+    if {[istarget "loongarch*-*-*"]} then {
+	set dump_opts {{as -mno-relax}}
+    }
     if {[istarget "m32r*-*-*"]} then {
 	set target_machine -m32r
     }
diff --git a/gas/testsuite/gas/elf/section11.d b/gas/testsuite/gas/elf/sect=
ion11.d
index 427aea67032..277fa6df7d6 100644
--- a/gas/testsuite/gas/elf/section11.d
+++ b/gas/testsuite/gas/elf/section11.d
@@ -2,8 +2,8 @@
 #readelf: -S --wide
 #name: Disabling section padding
 # The RX port uses non standard section names.
-#xfail: rx-*-*
-# RISC-V handles alignment via linker relaxation, so object files don't ha=
ve
+#xfail: loongarch*-* rx-*-*
+# LoongArch and RISC-V handles alignment via linker relaxation, so object =
files don't have
 # the expected alignment.
 #xfail: riscv*-*-*
=20
diff --git a/gas/testsuite/gas/lns/lns.exp b/gas/testsuite/gas/lns/lns.exp
index 244b0e26145..26dc253a84c 100644
--- a/gas/testsuite/gas/lns/lns.exp
+++ b/gas/testsuite/gas/lns/lns.exp
@@ -31,6 +31,7 @@ if { ![istarget s390*-*-*] } {
 	 || [istarget cr16-*-*]
 	 || [istarget crx-*-*]
 	 || [istarget ft32*-*]
+	 || [istarget loongarch*-*-*]
 	 || [istarget mn10*-*-*]
 	 || [istarget msp430-*-*]
 	 || [istarget nds32*-*-*]
diff --git a/gas/testsuite/gas/loongarch/jmp_op.d b/gas/testsuite/gas/loong=
arch/jmp_op.d
index 218c13f9398..a4535c297c9 100644
--- a/gas/testsuite/gas/loongarch/jmp_op.d
+++ b/gas/testsuite/gas/loongarch/jmp_op.d
@@ -6,26 +6,45 @@
=20
 Disassembly of section .text:
=20
-00000000.* <.text>:
-[ 	]+0:[ 	]+03400000[ 	]+[ 	]+andi[ 	]+\$zero, \$zero, 0x0
-[ 	]+4:[ 	]+63fffc04[ 	]+[ 	]+blt[ 	]+\$zero, \$a0, -4\(0x3fffc\)[ 	]+# 0x0
-[ 	]+8:[ 	]+67fff880[ 	]+[ 	]+bge[ 	]+\$a0, \$zero, -8\(0x3fff8\)[ 	]+# 0x0
-[ 	]+c:[ 	]+67fff404[ 	]+[ 	]+bge[ 	]+\$zero, \$a0, -12\(0x3fff4\)[ 	]+# 0=
x0
-[ 	]+10:[ 	]+43fff09f[ 	]+[ 	]+beqz[ 	]+\$a0, -16\(0x7ffff0\)[ 	]+# 0x0
-[ 	]+14:[ 	]+47ffec9f[ 	]+[ 	]+bnez[ 	]+\$a0, -20\(0x7fffec\)[ 	]+# 0x0
-[ 	]+18:[ 	]+4bffe81f[ 	]+[ 	]+bceqz[ 	]+\$fcc0, -24\(0x7fffe8\)[ 	]+# 0x0
-[ 	]+1c:[ 	]+4bffe51f[ 	]+[ 	]+bcnez[ 	]+\$fcc0, -28\(0x7fffe4\)[ 	]+# 0x0
-[ 	]+20:[ 	]+4c000080[ 	]+[ 	]+jirl[ 	]+\$zero, \$a0, 0
-[ 	]+24:[ 	]+53ffdfff[ 	]+[ 	]+b[ 	]+-36\(0xfffffdc\)[ 	]+# 0x0
-[ 	]+28:[ 	]+57ffdbff[ 	]+[ 	]+bl[ 	]+-40\(0xfffffd8\)[ 	]+# 0x0
-[ 	]+2c:[ 	]+5bffd485[ 	]+[ 	]+beq[ 	]+\$a0, \$a1, -44\(0x3ffd4\)[ 	]+# 0x0
-[ 	]+30:[ 	]+5fffd085[ 	]+[ 	]+bne[ 	]+\$a0, \$a1, -48\(0x3ffd0\)[ 	]+# 0x0
-[ 	]+34:[ 	]+63ffcc85[ 	]+[ 	]+blt[ 	]+\$a0, \$a1, -52\(0x3ffcc\)[ 	]+# 0x0
-[ 	]+38:[ 	]+63ffc8a4[ 	]+[ 	]+blt[ 	]+\$a1, \$a0, -56\(0x3ffc8\)[ 	]+# 0x0
-[ 	]+3c:[ 	]+67ffc485[ 	]+[ 	]+bge[ 	]+\$a0, \$a1, -60\(0x3ffc4\)[ 	]+# 0x0
-[ 	]+40:[ 	]+67ffc0a4[ 	]+[ 	]+bge[ 	]+\$a1, \$a0, -64\(0x3ffc0\)[ 	]+# 0x0
-[ 	]+44:[ 	]+6bffbc85[ 	]+[ 	]+bltu[ 	]+\$a0, \$a1, -68\(0x3ffbc\)[ 	]+# 0=
x0
-[ 	]+48:[ 	]+6bffb8a4[ 	]+[ 	]+bltu[ 	]+\$a1, \$a0, -72\(0x3ffb8\)[ 	]+# 0=
x0
-[ 	]+4c:[ 	]+6fffb485[ 	]+[ 	]+bgeu[ 	]+\$a0, \$a1, -76\(0x3ffb4\)[ 	]+# 0=
x0
-[ 	]+50:[ 	]+6fffb0a4[ 	]+[ 	]+bgeu[ 	]+\$a1, \$a0, -80\(0x3ffb0\)[ 	]+# 0=
x0
-[ 	]+54:[ 	]+4c000020[ 	]+[ 	]+jirl[ 	]+\$zero, \$ra, 0
+00000000.* <.L1>:
+[ 	]+0:[ 	]+03400000[ 	]+andi[ 	]+\$zero,[ 	]+\$zero,[ 	]+0x0
+[ 	]+4:[ 	]+63fffc04[ 	]+blt[ 	]+\$zero,[ 	]+\$a0,[ 	]+-4\(0x3fffc\)[ 	]+#=
[ 	]+0[ 	]+<\.L1>
+[ 	]+4:[ 	]+R_LARCH_B16[ 	]+\.L1
+[ 	]+8:[ 	]+67fff880[ 	]+bge[ 	]+\$a0,[ 	]+\$zero,[ 	]+-8\(0x3fff8\)[ 	]+#=
[ 	]+0[ 	]+<\.L1>
+[ 	]+8:[ 	]+R_LARCH_B16[ 	]+\.L1
+[ 	]+c:[ 	]+67fff404[ 	]+bge[ 	]+\$zero,[ 	]+\$a0,[ 	]+-12\(0x3fff4\)[ 	]+=
#[ 	]+0[ 	]+<\.L1>
+[ 	]+c:[ 	]+R_LARCH_B16[ 	]+\.L1
+[ 	]+10:[ 	]+43fff09f[ 	]+beqz[ 	]+\$a0,[ 	]+-16\(0x7ffff0\)[ 	]+#[ 	]+0[ =
	]+<\.L1>
+[ 	]+10:[ 	]+R_LARCH_B21[ 	]+\.L1
+[ 	]+14:[ 	]+47ffec9f[ 	]+bnez[ 	]+\$a0,[ 	]+-20\(0x7fffec\)[ 	]+#[ 	]+0[ =
	]+<\.L1>
+[ 	]+14:[ 	]+R_LARCH_B21[ 	]+\.L1
+[ 	]+18:[ 	]+4bffe81f[ 	]+bceqz[ 	]+\$fcc0,[ 	]+-24\(0x7fffe8\)[ 	]+#[ 	]+=
0[ 	]+<\.L1>
+[ 	]+18:[ 	]+R_LARCH_B21[ 	]+\.L1
+[ 	]+1c:[ 	]+4bffe51f[ 	]+bcnez[ 	]+\$fcc0,[ 	]+-28\(0x7fffe4\)[ 	]+#[ 	]+=
0[ 	]+<\.L1>
+[ 	]+1c:[ 	]+R_LARCH_B21[ 	]+\.L1
+[ 	]+20:[ 	]+4c000080[ 	]+jirl[ 	]+\$zero,[ 	]+\$a0,[ 	]+0
+[ 	]+24:[ 	]+53ffdfff[ 	]+b[ 	]+-36\(0xfffffdc\)[ 	]+#[ 	]+0[ 	]+<\.L1>
+[ 	]+24:[ 	]+R_LARCH_B26[ 	]+\.L1
+[ 	]+28:[ 	]+57ffdbff[ 	]+bl[ 	]+-40\(0xfffffd8\)[ 	]+#[ 	]+0[ 	]+<\.L1>
+[ 	]+28:[ 	]+R_LARCH_B26[ 	]+\.L1
+[ 	]+2c:[ 	]+5bffd485[ 	]+beq[ 	]+\$a0,[ 	]+\$a1,[ 	]+-44\(0x3ffd4\)[ 	]+#=
[ 	]+0[ 	]+<\.L1>
+[ 	]+2c:[ 	]+R_LARCH_B16[ 	]+\.L1
+[ 	]+30:[ 	]+5fffd085[ 	]+bne[ 	]+\$a0,[ 	]+\$a1,[ 	]+-48\(0x3ffd0\)[ 	]+#=
[ 	]+0[ 	]+<\.L1>
+[ 	]+30:[ 	]+R_LARCH_B16[ 	]+\.L1
+[ 	]+34:[ 	]+63ffcc85[ 	]+blt[ 	]+\$a0,[ 	]+\$a1,[ 	]+-52\(0x3ffcc\)[ 	]+#=
[ 	]+0[ 	]+<\.L1>
+[ 	]+34:[ 	]+R_LARCH_B16[ 	]+\.L1
+[ 	]+38:[ 	]+63ffc8a4[ 	]+blt[ 	]+\$a1,[ 	]+\$a0,[ 	]+-56\(0x3ffc8\)[ 	]+#=
[ 	]+0[ 	]+<\.L1>
+[ 	]+38:[ 	]+R_LARCH_B16[ 	]+\.L1
+[ 	]+3c:[ 	]+67ffc485[ 	]+bge[ 	]+\$a0,[ 	]+\$a1,[ 	]+-60\(0x3ffc4\)[ 	]+#=
[ 	]+0[ 	]+<\.L1>
+[ 	]+3c:[ 	]+R_LARCH_B16[ 	]+\.L1
+[ 	]+40:[ 	]+67ffc0a4[ 	]+bge[ 	]+\$a1,[ 	]+\$a0,[ 	]+-64\(0x3ffc0\)[ 	]+#=
[ 	]+0[ 	]+<\.L1>
+[ 	]+40:[ 	]+R_LARCH_B16[ 	]+\.L1
+[ 	]+44:[ 	]+6bffbc85[ 	]+bltu[ 	]+\$a0,[ 	]+\$a1,[ 	]+-68\(0x3ffbc\)[ 	]+=
#[ 	]+0[ 	]+<\.L1>
+[ 	]+44:[ 	]+R_LARCH_B16[ 	]+\.L1
+[ 	]+48:[ 	]+6bffb8a4[ 	]+bltu[ 	]+\$a1,[ 	]+\$a0,[ 	]+-72\(0x3ffb8\)[ 	]+=
#[ 	]+0[ 	]+<\.L1>
+[ 	]+48:[ 	]+R_LARCH_B16[ 	]+\.L1
+[ 	]+4c:[ 	]+6fffb485[ 	]+bgeu[ 	]+\$a0,[ 	]+\$a1,[ 	]+-76\(0x3ffb4\)[ 	]+=
#[ 	]+0[ 	]+<\.L1>
+[ 	]+4c:[ 	]+R_LARCH_B16[ 	]+\.L1
+[ 	]+50:[ 	]+6fffb0a4[ 	]+bgeu[ 	]+\$a1,[ 	]+\$a0,[ 	]+-80\(0x3ffb0\)[ 	]+=
#[ 	]+0[ 	]+<\.L1>
+[ 	]+50:[ 	]+R_LARCH_B16[ 	]+\.L1
+[ 	]+54:[ 	]+4c000020[ 	]+jirl[ 	]+\$zero,[ 	]+\$ra,[ 	]+0
diff --git a/gas/testsuite/gas/loongarch/li.d b/gas/testsuite/gas/loongarch=
/li.d
index 850a3f48e30..2b37784f237 100644
--- a/gas/testsuite/gas/loongarch/li.d
+++ b/gas/testsuite/gas/loongarch/li.d
@@ -10,9 +10,11 @@ Disassembly of section .text:
 00000000.* <_start>:
 [ 	]+0:[ 	]+03803c06[ 	]+ori[ 	]+\$a2,[ 	]+\$zero,[ 	]+0xf
 [ 	]+4:[ 	]+1a000005[ 	]+pcalau12i[ 	]+\$a1,[ 	]+0
-[ 	]+4:[ 	]+R_LARCH_PCALA_HI20[ 	]+.rodata
-[ 	]+8:[ 	]+02c000a5[ 	]+addi.d[ 	]+\$a1,[ 	]+\$a1,[ 	]+0
-[ 	]+8:[ 	]+R_LARCH_PCALA_LO12[ 	]+.rodata
+[ 	]+4:[ 	]+R_LARCH_PCALA_HI20[ 	]+msg
+[ 	]+4:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
+[ 	]+8:[ 	]+02c000a5[ 	]+addi\.d[ 	]+\$a1,[ 	]+\$a1,[ 	]+0
+[ 	]+8:[ 	]+R_LARCH_PCALA_LO12[ 	]+msg
+[ 	]+8:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
 [ 	]+c:[ 	]+03800404[ 	]+ori[ 	]+\$a0,[ 	]+\$zero,[ 	]+0x1
 [ 	]+10:[ 	]+0381000b[ 	]+ori[ 	]+\$a7,[ 	]+\$zero,[ 	]+0x40
 [ 	]+14:[ 	]+002b0000[ 	]+syscall[ 	]+0x0
diff --git a/gas/testsuite/gas/loongarch/macro_op.d b/gas/testsuite/gas/loo=
ngarch/macro_op.d
index d264c4f25c5..3465d11d50d 100644
--- a/gas/testsuite/gas/loongarch/macro_op.d
+++ b/gas/testsuite/gas/loongarch/macro_op.d
@@ -9,51 +9,63 @@ Disassembly of section .text:
=20
 00000000.* <.text>:
 [ 	]+0:[ 	]+00150004[ 	]+move[ 	]+\$a0,[ 	]+\$zero
-[ 	]+4:[ 	]+02bffc04[ 	]+addi.w[ 	]+\$a0,[ 	]+\$zero,[ 	]+-1\(0xfff\)
+[ 	]+4:[ 	]+02bffc04[ 	]+addi\.w[ 	]+\$a0,[ 	]+\$zero,[ 	]+-1\(0xfff\)
 [ 	]+8:[ 	]+00150004[ 	]+move[ 	]+\$a0,[ 	]+\$zero
-[ 	]+c:[ 	]+02bffc04[ 	]+addi.w[ 	]+\$a0,[ 	]+\$zero,[ 	]+-1\(0xfff\)
+[ 	]+c:[ 	]+02bffc04[ 	]+addi\.w[ 	]+\$a0,[ 	]+\$zero,[ 	]+-1\(0xfff\)
 [ 	]+10:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
-[ 	]+10:[ 	]+R_LARCH_GOT_PC_HI20[ 	]+.L1
-[ 	]+14:[ 	]+28c00084[ 	]+ld.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+0
-[ 	]+14:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+.L1
+[ 	]+10:[ 	]+R_LARCH_GOT_PC_HI20[ 	]+\.L1
+[ 	]+10:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
+[ 	]+14:[ 	]+28c00084[ 	]+ld\.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+0
+[ 	]+14:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+\.L1
+[ 	]+14:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
 [ 	]+18:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
-[ 	]+18:[ 	]+R_LARCH_GOT_PC_HI20[ 	]+.L1
-[ 	]+1c:[ 	]+28c00084[ 	]+ld.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+0
-[ 	]+1c:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+.L1
+[ 	]+18:[ 	]+R_LARCH_GOT_PC_HI20[ 	]+\.L1
+[ 	]+18:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
+[ 	]+1c:[ 	]+28c00084[ 	]+ld\.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+0
+[ 	]+1c:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+\.L1
+[ 	]+1c:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
 [ 	]+20:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
-[ 	]+20:[ 	]+R_LARCH_PCALA_HI20[ 	]+.L1
-[ 	]+24:[ 	]+02c00084[ 	]+addi.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+0
-[ 	]+24:[ 	]+R_LARCH_PCALA_LO12[ 	]+.L1
-[ 	]+28:[ 	]+14000004[ 	]+lu12i.w[ 	]+\$a0,[ 	]+0
+[ 	]+20:[ 	]+R_LARCH_PCALA_HI20[ 	]+\.L1
+[ 	]+20:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
+[ 	]+24:[ 	]+02c00084[ 	]+addi\.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+0
+[ 	]+24:[ 	]+R_LARCH_PCALA_LO12[ 	]+\.L1
+[ 	]+24:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
+[ 	]+28:[ 	]+14000004[ 	]+lu12i\.w[ 	]+\$a0,[ 	]+0
 [ 	]+28:[ 	]+R_LARCH_MARK_LA[ 	]+\*ABS\*
-[ 	]+28:[ 	]+R_LARCH_ABS_HI20[ 	]+.L1
+[ 	]+28:[ 	]+R_LARCH_ABS_HI20[ 	]+\.L1
 [ 	]+2c:[ 	]+03800084[ 	]+ori[ 	]+\$a0,[ 	]+\$a0,[ 	]+0x0
-[ 	]+2c:[ 	]+R_LARCH_ABS_LO12[ 	]+.L1
-[ 	]+30:[ 	]+16000004[ 	]+lu32i.d[ 	]+\$a0,[ 	]+0
-[ 	]+30:[ 	]+R_LARCH_ABS64_LO20[ 	]+.L1
-[ 	]+34:[ 	]+03000084[ 	]+lu52i.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+0
-[ 	]+34:[ 	]+R_LARCH_ABS64_HI12[ 	]+.L1
+[ 	]+2c:[ 	]+R_LARCH_ABS_LO12[ 	]+\.L1
+[ 	]+30:[ 	]+16000004[ 	]+lu32i\.d[ 	]+\$a0,[ 	]+0
+[ 	]+30:[ 	]+R_LARCH_ABS64_LO20[ 	]+\.L1
+[ 	]+34:[ 	]+03000084[ 	]+lu52i\.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+0
+[ 	]+34:[ 	]+R_LARCH_ABS64_HI12[ 	]+\.L1
 [ 	]+38:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
-[ 	]+38:[ 	]+R_LARCH_PCALA_HI20[ 	]+.L1
-[ 	]+3c:[ 	]+02c00084[ 	]+addi.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+0
-[ 	]+3c:[ 	]+R_LARCH_PCALA_LO12[ 	]+.L1
+[ 	]+38:[ 	]+R_LARCH_PCALA_HI20[ 	]+\.L1
+[ 	]+38:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
+[ 	]+3c:[ 	]+02c00084[ 	]+addi\.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+0
+[ 	]+3c:[ 	]+R_LARCH_PCALA_LO12[ 	]+\.L1
+[ 	]+3c:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
 [ 	]+40:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
-[ 	]+40:[ 	]+R_LARCH_GOT_PC_HI20[ 	]+.L1
-[ 	]+44:[ 	]+28c00084[ 	]+ld.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+0
-[ 	]+44:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+.L1
-[ 	]+48:[ 	]+14000004[ 	]+lu12i.w[ 	]+\$a0,[ 	]+0
+[ 	]+40:[ 	]+R_LARCH_GOT_PC_HI20[ 	]+\.L1
+[ 	]+40:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
+[ 	]+44:[ 	]+28c00084[ 	]+ld\.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+0
+[ 	]+44:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+\.L1
+[ 	]+44:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
+[ 	]+48:[ 	]+14000004[ 	]+lu12i\.w[ 	]+\$a0,[ 	]+0
 [ 	]+48:[ 	]+R_LARCH_TLS_LE_HI20[ 	]+TLS1
 [ 	]+4c:[ 	]+03800084[ 	]+ori[ 	]+\$a0,[ 	]+\$a0,[ 	]+0x0
 [ 	]+4c:[ 	]+R_LARCH_TLS_LE_LO12[ 	]+TLS1
 [ 	]+50:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
 [ 	]+50:[ 	]+R_LARCH_TLS_IE_PC_HI20[ 	]+TLS1
-[ 	]+54:[ 	]+28c00084[ 	]+ld.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+0
+[ 	]+54:[ 	]+28c00084[ 	]+ld\.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+0
 [ 	]+54:[ 	]+R_LARCH_TLS_IE_PC_LO12[ 	]+TLS1
 [ 	]+58:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
 [ 	]+58:[ 	]+R_LARCH_TLS_LD_PC_HI20[ 	]+TLS1
-[ 	]+5c:[ 	]+02c00084[ 	]+addi.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+0
+[ 	]+5c:[ 	]+02c00084[ 	]+addi\.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+0
 [ 	]+5c:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+TLS1
+[ 	]+5c:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
 [ 	]+60:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
 [ 	]+60:[ 	]+R_LARCH_TLS_GD_PC_HI20[ 	]+TLS1
-[ 	]+64:[ 	]+02c00084[ 	]+addi.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+0
+[ 	]+64:[ 	]+02c00084[ 	]+addi\.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+0
 [ 	]+64:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+TLS1
+[ 	]+64:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
diff --git a/gas/testsuite/gas/loongarch/macro_op_32.d b/gas/testsuite/gas/=
loongarch/macro_op_32.d
index a78c4579ee9..f5a2b54dd9b 100644
--- a/gas/testsuite/gas/loongarch/macro_op_32.d
+++ b/gas/testsuite/gas/loongarch/macro_op_32.d
@@ -14,29 +14,39 @@ Disassembly of section .text:
 [ 	]+c:[ 	]+02bffc04[ 	]+addi.w[ 	]+\$a0,[ 	]+\$zero,[ 	]+-1\(0xfff\)
 [ 	]+10:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
 [ 	]+10:[ 	]+R_LARCH_GOT_PC_HI20[ 	]+.L1
+[ 	]+10:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
 [ 	]+14:[ 	]+28800084[ 	]+ld.w[ 	]+\$a0,[ 	]+\$a0,[ 	]+0
 [ 	]+14:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+.L1
+[ 	]+14:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
 [ 	]+18:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
 [ 	]+18:[ 	]+R_LARCH_GOT_PC_HI20[ 	]+.L1
+[ 	]+18:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
 [ 	]+1c:[ 	]+28800084[ 	]+ld.w[ 	]+\$a0,[ 	]+\$a0,[ 	]+0
 [ 	]+1c:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+.L1
+[ 	]+1c:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
 [ 	]+20:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
-[ 	]+20:[ 	]+R_LARCH_PCALA_HI20[ 	]+.text
+[ 	]+20:[ 	]+R_LARCH_PCALA_HI20[ 	]+.L1
+[ 	]+20:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
 [ 	]+24:[ 	]+02800084[ 	]+addi.w[ 	]+\$a0,[ 	]+\$a0,[ 	]+0
-[ 	]+24:[ 	]+R_LARCH_PCALA_LO12[ 	]+.text
+[ 	]+24:[ 	]+R_LARCH_PCALA_LO12[ 	]+.L1
+[ 	]+24:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
 [ 	]+28:[ 	]+14000004[ 	]+lu12i.w[ 	]+\$a0,[ 	]+0
 [ 	]+28:[ 	]+R_LARCH_MARK_LA[ 	]+\*ABS\*
-[ 	]+28:[ 	]+R_LARCH_ABS_HI20[ 	]+.text
+[ 	]+28:[ 	]+R_LARCH_ABS_HI20[ 	]+.L1
 [ 	]+2c:[ 	]+03800084[ 	]+ori[ 	]+\$a0,[ 	]+\$a0,[ 	]+0x0
-[ 	]+2c:[ 	]+R_LARCH_ABS_LO12[ 	]+.text
+[ 	]+2c:[ 	]+R_LARCH_ABS_LO12[ 	]+.L1
 [ 	]+30:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
-[ 	]+30:[ 	]+R_LARCH_PCALA_HI20[ 	]+.text
+[ 	]+30:[ 	]+R_LARCH_PCALA_HI20[ 	]+.L1
+[ 	]+30:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
 [ 	]+34:[ 	]+02800084[ 	]+addi.w[ 	]+\$a0,[ 	]+\$a0,[ 	]+0
-[ 	]+34:[ 	]+R_LARCH_PCALA_LO12[ 	]+.text
+[ 	]+34:[ 	]+R_LARCH_PCALA_LO12[ 	]+.L1
+[ 	]+34:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
 [ 	]+38:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
 [ 	]+38:[ 	]+R_LARCH_GOT_PC_HI20[ 	]+.L1
+[ 	]+38:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
 [ 	]+3c:[ 	]+28800084[ 	]+ld.w[ 	]+\$a0,[ 	]+\$a0,[ 	]+0
 [ 	]+3c:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+.L1
+[ 	]+3c:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
 [ 	]+40:[ 	]+14000004[ 	]+lu12i.w[ 	]+\$a0,[ 	]+0
 [ 	]+40:[ 	]+R_LARCH_TLS_LE_HI20[ 	]+TLS1
 [ 	]+44:[ 	]+03800084[ 	]+ori[ 	]+\$a0,[ 	]+\$a0,[ 	]+0x0
@@ -49,7 +59,9 @@ Disassembly of section .text:
 [ 	]+50:[ 	]+R_LARCH_TLS_LD_PC_HI20[ 	]+TLS1
 [ 	]+54:[ 	]+02800084[ 	]+addi.w[ 	]+\$a0,[ 	]+\$a0,[ 	]+0
 [ 	]+54:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+TLS1
+[ 	]+54:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
 [ 	]+58:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
 [ 	]+58:[ 	]+R_LARCH_TLS_GD_PC_HI20[ 	]+TLS1
 [ 	]+5c:[ 	]+02800084[ 	]+addi.w[ 	]+\$a0,[ 	]+\$a0,[ 	]+0
 [ 	]+5c:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+TLS1
+[ 	]+5c:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
diff --git a/gas/testsuite/gas/loongarch/macro_op_large_abs.d b/gas/testsui=
te/gas/loongarch/macro_op_large_abs.d
index c0b98dbbea2..f3a3a4845b9 100644
--- a/gas/testsuite/gas/loongarch/macro_op_large_abs.d
+++ b/gas/testsuite/gas/loongarch/macro_op_large_abs.d
@@ -9,36 +9,42 @@ Disassembly of section .text:
=20
 00000000.* <.L1>:
 [ 	]+0:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
-[ 	]+0:[ 	]+R_LARCH_PCALA_HI20[ 	]+.text
+[ 	]+0:[ 	]+R_LARCH_PCALA_HI20[ 	]+.L1
+[ 	]+0:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
 [ 	]+4:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
-[ 	]+4:[ 	]+R_LARCH_PCALA_LO12[ 	]+.text
+[ 	]+4:[ 	]+R_LARCH_PCALA_LO12[ 	]+.L1
+[ 	]+4:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
 [ 	]+8:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
-[ 	]+8:[ 	]+R_LARCH_PCALA64_LO20[ 	]+.text
+[ 	]+8:[ 	]+R_LARCH_PCALA64_LO20[ 	]+.L1
 [ 	]+c:[ 	]+030000a5[ 	]+lu52i.d[ 	]+\$a1,[ 	]+\$a1,[ 	]+0
-[ 	]+c:[ 	]+R_LARCH_PCALA64_HI12[ 	]+.text
+[ 	]+c:[ 	]+R_LARCH_PCALA64_HI12[ 	]+.L1
 [ 	]+10:[ 	]+00109484[ 	]+add.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+\$a1
 [ 	]+14:[ 	]+14000004[ 	]+lu12i.w[ 	]+\$a0,[ 	]+0
 [ 	]+14:[ 	]+R_LARCH_MARK_LA[ 	]+\*ABS\*
-[ 	]+14:[ 	]+R_LARCH_ABS_HI20[ 	]+.text
+[ 	]+14:[ 	]+R_LARCH_ABS_HI20[ 	]+.L1
 [ 	]+18:[ 	]+03800084[ 	]+ori[ 	]+\$a0,[ 	]+\$a0,[ 	]+0x0
-[ 	]+18:[ 	]+R_LARCH_ABS_LO12[ 	]+.text
+[ 	]+18:[ 	]+R_LARCH_ABS_LO12[ 	]+.L1
 [ 	]+1c:[ 	]+16000004[ 	]+lu32i.d[ 	]+\$a0,[ 	]+0
-[ 	]+1c:[ 	]+R_LARCH_ABS64_LO20[ 	]+.text
+[ 	]+1c:[ 	]+R_LARCH_ABS64_LO20[ 	]+.L1
 [ 	]+20:[ 	]+03000084[ 	]+lu52i.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+0
-[ 	]+20:[ 	]+R_LARCH_ABS64_HI12[ 	]+.text
+[ 	]+20:[ 	]+R_LARCH_ABS64_HI12[ 	]+.L1
 [ 	]+24:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
-[ 	]+24:[ 	]+R_LARCH_PCALA_HI20[ 	]+.text
+[ 	]+24:[ 	]+R_LARCH_PCALA_HI20[ 	]+.L1
+[ 	]+24:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
 [ 	]+28:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
-[ 	]+28:[ 	]+R_LARCH_PCALA_LO12[ 	]+.text
+[ 	]+28:[ 	]+R_LARCH_PCALA_LO12[ 	]+.L1
+[ 	]+28:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
 [ 	]+2c:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
-[ 	]+2c:[ 	]+R_LARCH_PCALA64_LO20[ 	]+.text
+[ 	]+2c:[ 	]+R_LARCH_PCALA64_LO20[ 	]+.L1
 [ 	]+30:[ 	]+030000a5[ 	]+lu52i.d[ 	]+\$a1,[ 	]+\$a1,[ 	]+0
-[ 	]+30:[ 	]+R_LARCH_PCALA64_HI12[ 	]+.text
+[ 	]+30:[ 	]+R_LARCH_PCALA64_HI12[ 	]+.L1
 [ 	]+34:[ 	]+00109484[ 	]+add.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+\$a1
 [ 	]+38:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
 [ 	]+38:[ 	]+R_LARCH_GOT_PC_HI20[ 	]+.L1
+[ 	]+38:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
 [ 	]+3c:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
 [ 	]+3c:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+.L1
+[ 	]+3c:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
 [ 	]+40:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
 [ 	]+40:[ 	]+R_LARCH_GOT64_PC_LO20[ 	]+.L1
 [ 	]+44:[ 	]+030000a5[ 	]+lu52i.d[ 	]+\$a1,[ 	]+\$a1,[ 	]+0
@@ -61,6 +67,7 @@ Disassembly of section .text:
 [ 	]+68:[ 	]+R_LARCH_TLS_LD_PC_HI20[ 	]+TLS1
 [ 	]+6c:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
 [ 	]+6c:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+TLS1
+[ 	]+6c:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
 [ 	]+70:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
 [ 	]+70:[ 	]+R_LARCH_GOT64_PC_LO20[ 	]+TLS1
 [ 	]+74:[ 	]+030000a5[ 	]+lu52i.d[ 	]+\$a1,[ 	]+\$a1,[ 	]+0
@@ -70,6 +77,7 @@ Disassembly of section .text:
 [ 	]+7c:[ 	]+R_LARCH_TLS_GD_PC_HI20[ 	]+TLS1
 [ 	]+80:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
 [ 	]+80:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+TLS1
+[ 	]+80:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
 [ 	]+84:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
 [ 	]+84:[ 	]+R_LARCH_GOT64_PC_LO20[ 	]+TLS1
 [ 	]+88:[ 	]+030000a5[ 	]+lu52i.d[ 	]+\$a1,[ 	]+\$a1,[ 	]+0
diff --git a/gas/testsuite/gas/loongarch/macro_op_large_pc.d b/gas/testsuit=
e/gas/loongarch/macro_op_large_pc.d
index 3b532755b6c..f3a3a4845b9 100644
--- a/gas/testsuite/gas/loongarch/macro_op_large_pc.d
+++ b/gas/testsuite/gas/loongarch/macro_op_large_pc.d
@@ -1,4 +1,4 @@
-#as:
+#as: -mla-global-with-abs
 #objdump: -dr
 #skip: loongarch32-*-*
=20
@@ -9,69 +9,77 @@ Disassembly of section .text:
=20
 00000000.* <.L1>:
 [ 	]+0:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
-[ 	]+0:[ 	]+R_LARCH_PCALA_HI20[ 	]+.text
+[ 	]+0:[ 	]+R_LARCH_PCALA_HI20[ 	]+.L1
+[ 	]+0:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
 [ 	]+4:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
-[ 	]+4:[ 	]+R_LARCH_PCALA_LO12[ 	]+.text
+[ 	]+4:[ 	]+R_LARCH_PCALA_LO12[ 	]+.L1
+[ 	]+4:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
 [ 	]+8:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
-[ 	]+8:[ 	]+R_LARCH_PCALA64_LO20[ 	]+.text
+[ 	]+8:[ 	]+R_LARCH_PCALA64_LO20[ 	]+.L1
 [ 	]+c:[ 	]+030000a5[ 	]+lu52i.d[ 	]+\$a1,[ 	]+\$a1,[ 	]+0
-[ 	]+c:[ 	]+R_LARCH_PCALA64_HI12[ 	]+.text
+[ 	]+c:[ 	]+R_LARCH_PCALA64_HI12[ 	]+.L1
 [ 	]+10:[ 	]+00109484[ 	]+add.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+\$a1
-[ 	]+14:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
-[ 	]+14:[ 	]+R_LARCH_GOT_PC_HI20[ 	]+.L1
-[ 	]+18:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
-[ 	]+18:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+.L1
-[ 	]+1c:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
-[ 	]+1c:[ 	]+R_LARCH_GOT64_PC_LO20[ 	]+.L1
-[ 	]+20:[ 	]+030000a5[ 	]+lu52i.d[ 	]+\$a1,[ 	]+\$a1,[ 	]+0
-[ 	]+20:[ 	]+R_LARCH_GOT64_PC_HI12[ 	]+.L1
-[ 	]+24:[ 	]+380c1484[ 	]+ldx.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+\$a1
-[ 	]+28:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
-[ 	]+28:[ 	]+R_LARCH_PCALA_HI20[ 	]+.text
-[ 	]+2c:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
-[ 	]+2c:[ 	]+R_LARCH_PCALA_LO12[ 	]+.text
-[ 	]+30:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
-[ 	]+30:[ 	]+R_LARCH_PCALA64_LO20[ 	]+.text
-[ 	]+34:[ 	]+030000a5[ 	]+lu52i.d[ 	]+\$a1,[ 	]+\$a1,[ 	]+0
-[ 	]+34:[ 	]+R_LARCH_PCALA64_HI12[ 	]+.text
-[ 	]+38:[ 	]+00109484[ 	]+add.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+\$a1
-[ 	]+3c:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
-[ 	]+3c:[ 	]+R_LARCH_GOT_PC_HI20[ 	]+.L1
-[ 	]+40:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
-[ 	]+40:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+.L1
-[ 	]+44:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
-[ 	]+44:[ 	]+R_LARCH_GOT64_PC_LO20[ 	]+.L1
-[ 	]+48:[ 	]+030000a5[ 	]+lu52i.d[ 	]+\$a1,[ 	]+\$a1,[ 	]+0
-[ 	]+48:[ 	]+R_LARCH_GOT64_PC_HI12[ 	]+.L1
-[ 	]+4c:[ 	]+380c1484[ 	]+ldx.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+\$a1
-[ 	]+50:[ 	]+14000004[ 	]+lu12i.w[ 	]+\$a0,[ 	]+0
-[ 	]+50:[ 	]+R_LARCH_TLS_LE_HI20[ 	]+TLS1
-[ 	]+54:[ 	]+03800084[ 	]+ori[ 	]+\$a0,[ 	]+\$a0,[ 	]+0x0
-[ 	]+54:[ 	]+R_LARCH_TLS_LE_LO12[ 	]+TLS1
-[ 	]+58:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
-[ 	]+58:[ 	]+R_LARCH_TLS_IE_PC_HI20[ 	]+TLS1
-[ 	]+5c:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
-[ 	]+5c:[ 	]+R_LARCH_TLS_IE_PC_LO12[ 	]+TLS1
-[ 	]+60:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
-[ 	]+60:[ 	]+R_LARCH_TLS_IE64_PC_LO20[ 	]+TLS1
-[ 	]+64:[ 	]+030000a5[ 	]+lu52i.d[ 	]+\$a1,[ 	]+\$a1,[ 	]+0
-[ 	]+64:[ 	]+R_LARCH_TLS_IE64_PC_HI12[ 	]+TLS1
-[ 	]+68:[ 	]+380c1484[ 	]+ldx.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+\$a1
-[ 	]+6c:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
-[ 	]+6c:[ 	]+R_LARCH_TLS_LD_PC_HI20[ 	]+TLS1
-[ 	]+70:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
-[ 	]+70:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+TLS1
-[ 	]+74:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
-[ 	]+74:[ 	]+R_LARCH_GOT64_PC_LO20[ 	]+TLS1
-[ 	]+78:[ 	]+030000a5[ 	]+lu52i.d[ 	]+\$a1,[ 	]+\$a1,[ 	]+0
-[ 	]+78:[ 	]+R_LARCH_GOT64_PC_HI12[ 	]+TLS1
-[ 	]+7c:[ 	]+00109484[ 	]+add.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+\$a1
-[ 	]+80:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
-[ 	]+80:[ 	]+R_LARCH_TLS_GD_PC_HI20[ 	]+TLS1
-[ 	]+84:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
-[ 	]+84:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+TLS1
-[ 	]+88:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
-[ 	]+88:[ 	]+R_LARCH_GOT64_PC_LO20[ 	]+TLS1
-[ 	]+8c:[ 	]+030000a5[ 	]+lu52i.d[ 	]+\$a1,[ 	]+\$a1,[ 	]+0
-[ 	]+8c:[ 	]+R_LARCH_GOT64_PC_HI12[ 	]+TLS1
-[ 	]+90:[ 	]+00109484[ 	]+add.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+\$a1
+[ 	]+14:[ 	]+14000004[ 	]+lu12i.w[ 	]+\$a0,[ 	]+0
+[ 	]+14:[ 	]+R_LARCH_MARK_LA[ 	]+\*ABS\*
+[ 	]+14:[ 	]+R_LARCH_ABS_HI20[ 	]+.L1
+[ 	]+18:[ 	]+03800084[ 	]+ori[ 	]+\$a0,[ 	]+\$a0,[ 	]+0x0
+[ 	]+18:[ 	]+R_LARCH_ABS_LO12[ 	]+.L1
+[ 	]+1c:[ 	]+16000004[ 	]+lu32i.d[ 	]+\$a0,[ 	]+0
+[ 	]+1c:[ 	]+R_LARCH_ABS64_LO20[ 	]+.L1
+[ 	]+20:[ 	]+03000084[ 	]+lu52i.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+0
+[ 	]+20:[ 	]+R_LARCH_ABS64_HI12[ 	]+.L1
+[ 	]+24:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
+[ 	]+24:[ 	]+R_LARCH_PCALA_HI20[ 	]+.L1
+[ 	]+24:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
+[ 	]+28:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
+[ 	]+28:[ 	]+R_LARCH_PCALA_LO12[ 	]+.L1
+[ 	]+28:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
+[ 	]+2c:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
+[ 	]+2c:[ 	]+R_LARCH_PCALA64_LO20[ 	]+.L1
+[ 	]+30:[ 	]+030000a5[ 	]+lu52i.d[ 	]+\$a1,[ 	]+\$a1,[ 	]+0
+[ 	]+30:[ 	]+R_LARCH_PCALA64_HI12[ 	]+.L1
+[ 	]+34:[ 	]+00109484[ 	]+add.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+\$a1
+[ 	]+38:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
+[ 	]+38:[ 	]+R_LARCH_GOT_PC_HI20[ 	]+.L1
+[ 	]+38:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
+[ 	]+3c:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
+[ 	]+3c:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+.L1
+[ 	]+3c:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
+[ 	]+40:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
+[ 	]+40:[ 	]+R_LARCH_GOT64_PC_LO20[ 	]+.L1
+[ 	]+44:[ 	]+030000a5[ 	]+lu52i.d[ 	]+\$a1,[ 	]+\$a1,[ 	]+0
+[ 	]+44:[ 	]+R_LARCH_GOT64_PC_HI12[ 	]+.L1
+[ 	]+48:[ 	]+380c1484[ 	]+ldx.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+\$a1
+[ 	]+4c:[ 	]+14000004[ 	]+lu12i.w[ 	]+\$a0,[ 	]+0
+[ 	]+4c:[ 	]+R_LARCH_TLS_LE_HI20[ 	]+TLS1
+[ 	]+50:[ 	]+03800084[ 	]+ori[ 	]+\$a0,[ 	]+\$a0,[ 	]+0x0
+[ 	]+50:[ 	]+R_LARCH_TLS_LE_LO12[ 	]+TLS1
+[ 	]+54:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
+[ 	]+54:[ 	]+R_LARCH_TLS_IE_PC_HI20[ 	]+TLS1
+[ 	]+58:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
+[ 	]+58:[ 	]+R_LARCH_TLS_IE_PC_LO12[ 	]+TLS1
+[ 	]+5c:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
+[ 	]+5c:[ 	]+R_LARCH_TLS_IE64_PC_LO20[ 	]+TLS1
+[ 	]+60:[ 	]+030000a5[ 	]+lu52i.d[ 	]+\$a1,[ 	]+\$a1,[ 	]+0
+[ 	]+60:[ 	]+R_LARCH_TLS_IE64_PC_HI12[ 	]+TLS1
+[ 	]+64:[ 	]+380c1484[ 	]+ldx.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+\$a1
+[ 	]+68:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
+[ 	]+68:[ 	]+R_LARCH_TLS_LD_PC_HI20[ 	]+TLS1
+[ 	]+6c:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
+[ 	]+6c:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+TLS1
+[ 	]+6c:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
+[ 	]+70:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
+[ 	]+70:[ 	]+R_LARCH_GOT64_PC_LO20[ 	]+TLS1
+[ 	]+74:[ 	]+030000a5[ 	]+lu52i.d[ 	]+\$a1,[ 	]+\$a1,[ 	]+0
+[ 	]+74:[ 	]+R_LARCH_GOT64_PC_HI12[ 	]+TLS1
+[ 	]+78:[ 	]+00109484[ 	]+add.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+\$a1
+[ 	]+7c:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
+[ 	]+7c:[ 	]+R_LARCH_TLS_GD_PC_HI20[ 	]+TLS1
+[ 	]+80:[ 	]+02c00005[ 	]+addi.d[ 	]+\$a1,[ 	]+\$zero,[ 	]+0
+[ 	]+80:[ 	]+R_LARCH_GOT_PC_LO12[ 	]+TLS1
+[ 	]+80:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
+[ 	]+84:[ 	]+16000005[ 	]+lu32i.d[ 	]+\$a1,[ 	]+0
+[ 	]+84:[ 	]+R_LARCH_GOT64_PC_LO20[ 	]+TLS1
+[ 	]+88:[ 	]+030000a5[ 	]+lu52i.d[ 	]+\$a1,[ 	]+\$a1,[ 	]+0
+[ 	]+88:[ 	]+R_LARCH_GOT64_PC_HI12[ 	]+TLS1
+[ 	]+8c:[ 	]+00109484[ 	]+add.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+\$a1
diff --git a/gas/testsuite/gas/loongarch/relax_align.d b/gas/testsuite/gas/=
loongarch/relax_align.d
new file mode 100644
index 00000000000..8a44573d406
--- /dev/null
+++ b/gas/testsuite/gas/loongarch/relax_align.d
@@ -0,0 +1,26 @@
+#as:
+#objdump: -dr
+#skip: loongarch32-*-*
+
+.*:[    ]+file format .*
+
+
+Disassembly of section .text:
+
+00000000.* <L1>:
+[ 	]+0:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
+[ 	]+0:[ 	]+R_LARCH_PCALA_HI20[ 	]+L1
+[ 	]+0:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
+[ 	]+4:[ 	]+02c00084[ 	]+addi\.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+0
+[ 	]+4:[ 	]+R_LARCH_PCALA_LO12[ 	]+L1
+[ 	]+4:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
+[ 	]+8:[ 	]+03400000[ 	]+andi[ 	]+\$zero,[ 	]+\$zero,[ 	]+0x0
+[ 	]+8:[ 	]+R_LARCH_ALIGN[ 	]+\*ABS\*\+0xc
+[ 	]+c:[ 	]+03400000[ 	]+andi[ 	]+\$zero,[ 	]+\$zero,[ 	]+0x0
+[ 	]+10:[ 	]+03400000[ 	]+andi[ 	]+\$zero,[ 	]+\$zero,[ 	]+0x0
+[ 	]+14:[ 	]+1a000004[ 	]+pcalau12i[ 	]+\$a0,[ 	]+0
+[ 	]+14:[ 	]+R_LARCH_PCALA_HI20[ 	]+L1
+[ 	]+14:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
+[ 	]+18:[ 	]+02c00084[ 	]+addi\.d[ 	]+\$a0,[ 	]+\$a0,[ 	]+0
+[ 	]+18:[ 	]+R_LARCH_PCALA_LO12[ 	]+L1
+[ 	]+18:[ 	]+R_LARCH_RELAX[ 	]+\*ABS\*
diff --git a/gas/testsuite/gas/loongarch/relax_align.s b/gas/testsuite/gas/=
loongarch/relax_align.s
new file mode 100644
index 00000000000..3880d783e79
--- /dev/null
+++ b/gas/testsuite/gas/loongarch/relax_align.s
@@ -0,0 +1,5 @@
+  .text
+L1:
+  la.local $a0, L1
+  .align 4
+  la.local $a0, L1
diff --git a/gas/testsuite/gas/loongarch/uleb128.d b/gas/testsuite/gas/loon=
garch/uleb128.d
new file mode 100644
index 00000000000..41ed8ff870f
--- /dev/null
+++ b/gas/testsuite/gas/loongarch/uleb128.d
@@ -0,0 +1,36 @@
+#as:
+#objdump: -Dr
+#skip: loongarch32-*-*
+
+.*:[    ]+file format .*
+
+
+Disassembly of section .data:
+
+00000000.* <L1-0x5>:
+[ 	]+0:[ 	]+80030201[ 	]+0x80030201
+[ 	]+3:[ 	]+R_LARCH_ADD_ULEB128[ 	]+L2
+[ 	]+3:[ 	]+R_LARCH_SUB_ULEB128[ 	]+L1
+[ 	]+\.\.\.
+
+0000000000000005[ 	]+<L1>:
+[ 	]+\.\.\.
+[ 	]+81:[ 	]+ff040000[ 	]+0xff040000
+[ 	]+85:[ 	]+cacop[ 	]+0x1f,[ 	]+\$t3,[ 	]+1\(0x1\)
+
+0000000000000086[ 	]+<L2>:
+[ 	]+86:[ 	]+07060005[ 	]+0x07060005
+[ 	]+8a:[ 	]+0x00008080
+[ 	]+8a:[ 	]+R_LARCH_ADD_ULEB128[ 	]+L4
+[ 	]+8a:[ 	]+R_LARCH_SUB_ULEB128[ 	]+L3
+
+000000000000008d[ 	]+<L3>:
+[ 	]+\.\.\.
+[ 	]+4089:[ 	]+ff080000[ 	]+0xff080000
+[ 	]+408d:[ 	]+0x09ffffff
+
+0000000000004090[ 	]+<L4>:
+[ 	]+4090:[ 	]+09090909[ 	]+0x09090909
+[ 	]+4094:[ 	]+09090909[ 	]+0x09090909
+[ 	]+4098:[ 	]+09090909[ 	]+0x09090909
+[ 	]+409c:[ 	]+09090909[ 	]+0x09090909
diff --git a/gas/testsuite/gas/loongarch/uleb128.s b/gas/testsuite/gas/loon=
garch/uleb128.s
new file mode 100644
index 00000000000..104a8956bd6
--- /dev/null
+++ b/gas/testsuite/gas/loongarch/uleb128.s
@@ -0,0 +1,20 @@
+ .data
+ .byte 1, 2, 3
+ .uleb128 L2 - L1
+L1:
+ .space 128 - 2
+ .byte 4
+ .p2align 1, 0xff
+L2:
+ .byte 5
+
+ .p2align 2
+ .byte 6, 7
+ .uleb128 L4 - L3
+L3:
+ .space 128*128 - 2
+ .byte 8
+ .p2align 2, 0xff
+L4:
+ .byte 9
+ .p2align 4, 9