From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1256) id 9434B3858438; Thu, 15 Jun 2023 03:49:18 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9434B3858438 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Maciej W. Rozycki To: bfd-cvs@sourceware.org Subject: [binutils-gdb] Add rotation instructions to MIPS Allegrex CPU X-Act-Checkin: binutils-gdb X-Git-Author: David Guillen Fandos X-Git-Refname: refs/heads/master X-Git-Oldrev: df18f71b565c29f6f1ebd385cb1aed97d00e9660 X-Git-Newrev: d29b94fc9f365de8002a9566df5bd8a45c7c8f1d Message-Id: <20230615034918.9434B3858438@sourceware.org> Date: Thu, 15 Jun 2023 03:49:18 +0000 (GMT) X-BeenThere: binutils-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 15 Jun 2023 03:49:18 -0000 https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3Dd29b94fc9f36= 5de8002a9566df5bd8a45c7c8f1d commit d29b94fc9f365de8002a9566df5bd8a45c7c8f1d Author: David Guillen Fandos Date: Thu Jun 15 04:45:03 2023 +0100 Add rotation instructions to MIPS Allegrex CPU =20 The Allegrex CPU supports bit rotation instructions as described in the MIPS32 release 2 CPU (even though it is a MIPS-2 based CPU). =20 Signed-off-by: David Guillen Fandos Diff: --- gas/config/tc-mips.c | 2 +- gas/testsuite/gas/mips/mips.exp | 2 +- opcodes/mips-opc.c | 14 +++++++------- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index 0439a3e8890..d6aae660abf 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -526,7 +526,7 @@ static int mips_32bitmode =3D 0; #define CPU_HAS_DROR(CPU) ((CPU) =3D=3D CPU_VR5400 || (CPU) =3D=3D CPU_VR5= 500) =20 /* True if CPU has a ror instruction. */ -#define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) +#define CPU_HAS_ROR(CPU) (CPU_HAS_DROR (CPU) || (CPU) =3D=3D CPU_ALLEGREX) =20 /* True if CPU is in the Octeon family. */ #define CPU_IS_OCTEON(CPU) ((CPU) =3D=3D CPU_OCTEON || (CPU) =3D=3D CPU_OC= TEONP \ diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.= exp index 773e5b7e2c7..92cc3866d41 100644 --- a/gas/testsuite/gas/mips/mips.exp +++ b/gas/testsuite/gas/mips/mips.exp @@ -509,7 +509,7 @@ mips_arch_create r3000 32 mips1 {} \ mips_arch_create r3900 32 mips1 { gpr_ilocks } \ { -march=3Dr3900 -mtune=3Dr3900 } { -mmips:3900 } \ { mipstx39-*-* mipstx39el-*-* } -mips_arch_create allegrex 32 mips2 { singlefloat oddspreg } \ +mips_arch_create allegrex 32 mips2 { ror singlefloat oddspreg } \ { -march=3Dallegrex -mtune=3Dallegrex } \ { -mmips:allegrex } mips_arch_create r4000 64 mips3 {} \ diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 3c48c0c0cfd..8eecae9ba12 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -1802,13 +1802,13 @@ const struct mips_opcode mips_builtin_opcodes[] =3D {"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1, 0, 0 }, {"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1, 0, 0 }, {"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I1, 0, 0 }, -{"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_1|RD_2, 0, N5|I33, SMT, 0= }, -{"rorv", "d,t,s", 0x00000046, 0xfc0007ff, WR_1|RD_2|RD_3, 0, N5|I33, S= MT, 0 }, -{"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33, SMT, 0 }, -{"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33, SMT, 0 }, -{"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33, SMT, 0 }, -{"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33, SMT, 0 }, -{"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I33, SMT= , 0 }, +{"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_1|RD_2, 0, N5|I33|AL, SMT,= 0 }, +{"rorv", "d,t,s", 0x00000046, 0xfc0007ff, WR_1|RD_2|RD_3, 0, N5|I33|AL,= SMT, 0 }, +{"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33|AL, SMT, 0 }, +{"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33|AL, SMT, 0 }, +{"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33|AL, SMT, 0 }, +{"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33|AL, SMT, 0 }, +{"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I33|AL, = SMT, 0 }, {"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_1|RD_2|FP_D, 0, I3_33,= 0, 0 }, {"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I3= _33, 0, 0 }, {"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I2= , 0, SF },