From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1386) id 40E6B385701B; Fri, 16 Jun 2023 07:23:42 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 40E6B385701B Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Jan Beulich To: bfd-cvs@sourceware.org Subject: [binutils-gdb] x86: shrink Masking insn attribute to a single bit (boolean) X-Act-Checkin: binutils-gdb X-Git-Author: Jan Beulich X-Git-Refname: refs/heads/master X-Git-Oldrev: 2a4da0730829376aeaee4dd8eab345fb6a8ddf03 X-Git-Newrev: b1c792568662d7e00158d19e0439b64f98b78e47 Message-Id: <20230616072342.40E6B385701B@sourceware.org> Date: Fri, 16 Jun 2023 07:23:42 +0000 (GMT) X-BeenThere: binutils-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 16 Jun 2023 07:23:42 -0000 https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3Db1c792568662= d7e00158d19e0439b64f98b78e47 commit b1c792568662d7e00158d19e0439b64f98b78e47 Author: Jan Beulich Date: Fri Jun 16 09:23:26 2023 +0200 x86: shrink Masking insn attribute to a single bit (boolean) =20 The logic can actually be expressed with less code that way, utilizing that there are common patterns of when which form of masking is permitted. This then also eliminates the large set of open-codings of BOTH_MASKING in the opcode table. Diff: --- gas/config/tc-i386.c | 47 +- opcodes/i386-opc.h | 11 +- opcodes/i386-opc.tbl | 1137 ++++++++++++++------------- opcodes/i386-tbl.h | 2114 +++++++++++++++++++++++++---------------------= ---- 4 files changed, 1645 insertions(+), 1664 deletions(-) diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 690f6ee060d..de35ee2a2c6 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -6530,36 +6530,25 @@ check_VecOperands (const insn_template *t) /* Check if requested masking is supported. */ if (i.mask.reg) { - switch (t->opcode_modifier.masking) + if (!t->opcode_modifier.masking) { - case BOTH_MASKING: - break; - case MERGING_MASKING: - if (i.mask.zeroing) - { - case 0: - i.error =3D unsupported_masking; - return 1; - } - break; - case DYNAMIC_MASKING: - /* Memory destinations allow only merging masking. */ - if (i.mask.zeroing && i.mem_operands) - { - /* Find memory operand. */ - for (op =3D 0; op < i.operands; op++) - if (i.flags[op] & Operand_Mem) - break; - gas_assert (op < i.operands); - if (op =3D=3D i.operands - 1) - { - i.error =3D unsupported_masking; - return 1; - } - } - break; - default: - abort (); + i.error =3D unsupported_masking; + return 1; + } + + /* Common rules for masking: + - mask register destinations permit only zeroing-masking, without + that actually being expressed by a {z} operand suffix or EVEX.z, + - memory destinations allow only merging-masking, + - scatter/gather insns (i.e. ones using vSIB) only allow merging- + masking. */ + if (i.mask.zeroing + && (t->operand_types[t->operands - 1].bitfield.class =3D=3D RegMask + || (i.flags[t->operands - 1] & Operand_Mem) + || t->opcode_modifier.sib)) + { + i.error =3D unsupported_masking; + return 1; } } =20 diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index d65392aca8d..3318bcfec33 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -647,14 +647,7 @@ enum #define EVEX_L3 6 EVex, =20 - /* AVX512 masking support: - 1: Zeroing or merging masking depending on operands. - 2: Merging-masking. - 3: Both zeroing and merging masking. - */ -#define DYNAMIC_MASKING 1 -#define MERGING_MASKING 2 -#define BOTH_MASKING 3 + /* AVX512 masking support */ Masking, =20 /* AVX512 broadcast support. The number of bytes to broadcast is @@ -735,7 +728,7 @@ typedef struct i386_opcode_modifier unsigned int sib:3; unsigned int sse2avx:1; unsigned int evex:3; - unsigned int masking:2; + unsigned int masking:1; unsigned int broadcast:3; unsigned int staticrounding:1; unsigned int sae:1; diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index c1d323310e5..26fee21d10d 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -2056,7 +2056,6 @@ vpclmulhqhqdq, 0x6644/0x11, VPCLMULQDQ, Modrm|Vex256|= Space0F3A|VexWIG|VexVVVV|No // AVX512F instructions. =20 #define Disp8ShiftVL Disp8MemShift=3DDISP8_SHIFT_VL -#define MaskingMorZ Masking=3DDYNAMIC_MASKING =20 , 0x6630, , Modrm|Vex128|Space0= F3A||NoSuf, { Imm8, =20 kunpckbw, 0x664B, AVX512F, Modrm|Vex=3D2|Space0F|VexVVVV|VexW0|NoSuf, { Re= gMask, RegMask, RegMask } =20 -vaddp, 0x58, , Modrm|Masking=3D3||VexVVV= V||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|S= AE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|= RegZMM, RegXMM|RegYMM|RegZMM } -vdivp, 0x5e, , Modrm|Masking=3D3||VexVVV= V||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|S= AE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|= RegZMM, RegXMM|RegYMM|RegZMM } -vmulp, 0x59, , Modrm|Masking=3D3||VexVVV= V||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|S= AE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|= RegZMM, RegXMM|RegYMM|RegZMM } -vsqrtp, 0x51, , Modrm|Masking=3D3|||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { R= egXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vsubp, 0x5c, , Modrm|Masking=3D3||VexVVV= V||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|S= AE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|= RegZMM, RegXMM|RegYMM|RegZMM } - -vadds, 0x58, , Modrm|EVexLIG|Masking=3D3||VexVVVV||Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vdivs, 0x5e, , Modrm|EVexLIG|Masking=3D3||VexVVVV||Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vmuls, 0x59, , Modrm|EVexLIG|Masking=3D3||VexVVVV||Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vsqrts, 0x51, , Modrm|EVexLIG|Masking=3D3||VexVVVV||Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vsubs, 0x5C, , Modrm|EVexLIG|Masking=3D3||VexVVVV||Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } - -valign, 0x6603, AVX512F, Modrm|Masking=3D3|Space0F3A|VexVVVV|= |Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZM= M||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZ= MM } -vblendmp, 0x6665, AVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpblendm, 0x6664, AVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpermi2, 0x6676, AVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpermi2p, 0x6677, AVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpermt2, 0x667E, AVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpermt2p, 0x667F, AVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmaxs, 0x663D, AVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV|= |Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmaxu, 0x663F, AVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV|= |Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmins, 0x6639, AVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV|= |Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpminu, 0x663B, AVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV|= |Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmuldq, 0x6628, AVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV|VexW=3D2|Bro= adcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Un= specified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmulld, 0x6640, AVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV|VexW=3D1|Bro= adcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Un= specified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vprolv, 0x6615, AVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV|= |Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vprorv, 0x6614, AVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV|= |Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsllv, 0x6647, AVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV|= |Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsrav, 0x6646, AVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV|= |Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsrlv, 0x6645, AVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV|= |Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpternlog, 0x6625, AVX512F, Modrm|Masking=3D3|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|Reg= YMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|Re= gYMM|RegZMM } - -vbroadcastf32x4, 0x661A, AVX512F, Modrm|Masking=3D3|Space0F38|VexW=3D1|Dis= p8MemShift=3D4|NoSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } -vbroadcasti32x4, 0x665A, AVX512F, Modrm|Masking=3D3|Space0F38|VexW=3D1|Dis= p8MemShift=3D4|NoSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } - -vbroadcastf64x4, 0x661B, AVX512F, Modrm|EVex=3D1|Masking=3D3|Space0F38|Vex= W=3D2|Disp8MemShift=3D5|NoSuf, { YMMword|Unspecified|BaseIndex, RegZMM } -vbroadcasti64x4, 0x665B, AVX512F, Modrm|EVex=3D1|Masking=3D3|Space0F38|Vex= W=3D2|Disp8MemShift=3D5|NoSuf, { YMMword|Unspecified|BaseIndex, RegZMM } - -vbroadcastss, 0x6618, AVX512F, Modrm|Masking=3D3|Space0F38|VexW0|Disp8MemS= hift=3D2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vbroadcastsd, 0x6619, AVX512F, Modrm|Masking=3D3|Space0F38|VexW1|Disp8MemS= hift=3D3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } - -vpbroadcast, 0x6658 | , AVX512F, Modrm|Masking=3D3|Space0F38|<= dq:vexw>|Disp8MemShift|NoSuf, { RegXMM||Unspecified|BaseIndex, Reg= XMM|RegYMM|RegZMM } -vpbroadcast, 0x667c, AVX512F, Modrm|Masking=3D3|Space0F38||= NoSuf, { , RegXMM|RegYMM|RegZMM } - -vcmpp, 0xC2/0x, AVX512F, Modrm|Masking=3D2|Sp= ace0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|ImmEx= t|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYM= M|RegZMM, RegMask } -vcmpp, 0xC2, AVX512F, Modrm|Masking=3D2|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { Imm8, RegXMM|RegY= MM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } - -vcmps, 0xC2/0x, AVX512F, Modrm|EVexLIG|Maskin= g=3D2|Space0F|VexVVVV||Disp8MemShift|NoSuf|SAE|ImmExt, { RegXMM||Unspecified|BaseIndex, RegXMM, RegMask } -vcmps, 0xC2, AVX512F, Modrm|EVexLIG|Masking=3D2|Space0F|VexVV= VV||Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM||Unspecified|= BaseIndex, RegXMM, RegMask } +vaddp, 0x58, , Modrm|Masking||VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, = { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZ= MM, RegXMM|RegYMM|RegZMM } +vdivp, 0x5e, , Modrm|Masking||VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, = { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZ= MM, RegXMM|RegYMM|RegZMM } +vmulp, 0x59, , Modrm|Masking||VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, = { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZ= MM, RegXMM|RegYMM|RegZMM } +vsqrtp, 0x51, , Modrm|Masking|||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXM= M|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vsubp, 0x5c, , Modrm|Masking||VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, = { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZ= MM, RegXMM|RegYMM|RegZMM } + +vadds, 0x58, , Modrm|EVexLIG|Masking||Ve= xVVVV||Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vdivs, 0x5e, , Modrm|EVexLIG|Masking||Ve= xVVVV||Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vmuls, 0x59, , Modrm|EVexLIG|Masking||Ve= xVVVV||Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vsqrts, 0x51, , Modrm|EVexLIG|Masking||V= exVVVV||Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vsubs, 0x5C, , Modrm|EVexLIG|Masking||Ve= xVVVV||Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } + +valign, 0x6603, AVX512F, Modrm|Masking|Space0F3A|VexVVVV||Bro= adcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vblendmp, 0x6665, AVX512F, Modrm|Masking|Space0F38|VexVVVV||B= roadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpblendm, 0x6664, AVX512F, Modrm|Masking|Space0F38|VexVVVV||B= roadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpermi2, 0x6676, AVX512F, Modrm|Masking|Space0F38|VexVVVV||Br= oadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpermi2p, 0x6677, AVX512F, Modrm|Masking|Space0F38|VexVVVV||B= roadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpermt2, 0x667E, AVX512F, Modrm|Masking|Space0F38|VexVVVV||Br= oadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpermt2p, 0x667F, AVX512F, Modrm|Masking|Space0F38|VexVVVV||B= roadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmaxs, 0x663D, AVX512F, Modrm|Masking|Space0F38|VexVVVV||Bro= adcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmaxu, 0x663F, AVX512F, Modrm|Masking|Space0F38|VexVVVV||Bro= adcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmins, 0x6639, AVX512F, Modrm|Masking|Space0F38|VexVVVV||Bro= adcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpminu, 0x663B, AVX512F, Modrm|Masking|Space0F38|VexVVVV||Bro= adcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmuldq, 0x6628, AVX512F, Modrm|Masking|Space0F38|VexVVVV|VexW=3D2|Broadca= st|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspec= ified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmulld, 0x6640, AVX512F, Modrm|Masking|Space0F38|VexVVVV|VexW=3D1|Broadca= st|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspec= ified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vprolv, 0x6615, AVX512F, Modrm|Masking|Space0F38|VexVVVV||Bro= adcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vprorv, 0x6614, AVX512F, Modrm|Masking|Space0F38|VexVVVV||Bro= adcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsllv, 0x6647, AVX512F, Modrm|Masking|Space0F38|VexVVVV||Bro= adcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsrav, 0x6646, AVX512F, Modrm|Masking|Space0F38|VexVVVV||Bro= adcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsrlv, 0x6645, AVX512F, Modrm|Masking|Space0F38|VexVVVV||Bro= adcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpternlog, 0x6625, AVX512F, Modrm|Masking|Space0F3A|VexVVVV||= Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|RegYMM|= RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM= |RegZMM } + +vbroadcastf32x4, 0x661A, AVX512F, Modrm|Masking|Space0F38|VexW=3D1|Disp8Me= mShift=3D4|NoSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } +vbroadcasti32x4, 0x665A, AVX512F, Modrm|Masking|Space0F38|VexW=3D1|Disp8Me= mShift=3D4|NoSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } + +vbroadcastf64x4, 0x661B, AVX512F, Modrm|EVex=3D1|Masking|Space0F38|VexW=3D= 2|Disp8MemShift=3D5|NoSuf, { YMMword|Unspecified|BaseIndex, RegZMM } +vbroadcasti64x4, 0x665B, AVX512F, Modrm|EVex=3D1|Masking|Space0F38|VexW=3D= 2|Disp8MemShift=3D5|NoSuf, { YMMword|Unspecified|BaseIndex, RegZMM } + +vbroadcastss, 0x6618, AVX512F, Modrm|Masking|Space0F38|VexW0|Disp8MemShift= =3D2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vbroadcastsd, 0x6619, AVX512F, Modrm|Masking|Space0F38|VexW1|Disp8MemShift= =3D3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } + +vpbroadcast, 0x6658 | , AVX512F, Modrm|Masking|Space0F38||Disp8MemShift|NoSuf, { RegXMM||Unspecified|BaseIndex, RegXMM|= RegYMM|RegZMM } +vpbroadcast, 0x667c, AVX512F, Modrm|Masking|Space0F38||NoSu= f, { , RegXMM|RegYMM|RegZMM } + +vcmpp, 0xC2/0x, AVX512F, Modrm|Masking|Space0= F|VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|ImmExt|SA= E, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|Re= gZMM, RegMask } +vcmpp, 0xC2, AVX512F, Modrm|Masking|Space0F|VexVVVV|= |Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM|R= egZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } + +vcmps, 0xC2/0x, AVX512F, Modrm|EVexLIG|Maskin= g|Space0F|VexVVVV||Disp8MemShift|NoSuf|SAE|ImmExt, { RegXMM||Unspecified|BaseIndex, RegXMM, RegMask } +vcmps, 0xC2, AVX512F, Modrm|EVexLIG|Masking|Space0F|VexVVVV|<= sd:vexw>|Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM||Unspecified|Base= Index, RegXMM, RegMask } =20 vcomis, 0x2f, , Modrm|EVexLIG|||Disp8MemShift|NoSuf|SAE, { RegXMM||Unspecified|BaseIndex, RegXM= M } vucomis, 0x2e, , Modrm|EVexLIG|||Disp8MemShift|NoSuf|SAE, { RegXMM||Unspecified|BaseIndex, RegX= MM } =20 -vcompresspd, 0x668A, AVX512F, Modrm|MaskingMorZ|Space0F38|VexW=3D2|Disp8Me= mShift=3D3|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|Re= gZMM|Unspecified|BaseIndex } -vcompressps, 0x668A, AVX512F, Modrm|MaskingMorZ|Space0F38|VexW=3D1|Disp8Me= mShift=3D2|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|Re= gZMM|Unspecified|BaseIndex } -vpcompressq, 0x668B, AVX512F, Modrm|MaskingMorZ|Space0F38|VexW=3D2|Disp8Me= mShift=3D3|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|Re= gZMM|Unspecified|BaseIndex } -vpcompressd, 0x668B, AVX512F, Modrm|MaskingMorZ|Space0F38|VexW=3D1|Disp8Me= mShift=3D2|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|Re= gZMM|Unspecified|BaseIndex } +vcompresspd, 0x668A, AVX512F, Modrm|Masking|Space0F38|VexW=3D2|Disp8MemShi= ft=3D3|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM= |Unspecified|BaseIndex } +vcompressps, 0x668A, AVX512F, Modrm|Masking|Space0F38|VexW=3D1|Disp8MemShi= ft=3D2|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM= |Unspecified|BaseIndex } +vpcompressq, 0x668B, AVX512F, Modrm|Masking|Space0F38|VexW=3D2|Disp8MemShi= ft=3D3|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM= |Unspecified|BaseIndex } +vpcompressd, 0x668B, AVX512F, Modrm|Masking|Space0F38|VexW=3D1|Disp8MemShi= ft=3D2|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM= |Unspecified|BaseIndex } =20 -vpscatterdd, 0x66A0, AVX512F, Modrm|EVex512|Masking=3D2|NoDefMask|Space0F3= 8|VexW0|Disp8MemShift=3D2|VecSIB512|NoSuf, { RegZMM, Dword|Unspecified|Base= Index } -vpscatterdq, 0x66A0, AVX512F, Modrm|EVex=3D1|Masking=3D2|NoDefMask|Space0F= 38|VexW1|Disp8MemShift=3D3|VecSIB256|NoSuf, { RegZMM, Qword|Unspecified|Bas= eIndex } -vpscatterqd, 0x66A1, AVX512F, Modrm|EVex512|Masking=3D2|NoDefMask|Space0F3= 8|VexW0|Disp8MemShift=3D2|VecSIB512|NoSuf, { RegYMM, Dword|Unspecified|Base= Index } -vpscatterqq, 0x66A1, AVX512F, Modrm|EVex=3D1|Masking=3D2|NoDefMask|Space0F= 38|VexW1|Disp8MemShift=3D3|VecSIB512|NoSuf, { RegZMM, Qword|Unspecified|Bas= eIndex } -vscatterdpd, 0x66A2, AVX512F, Modrm|EVex=3D1|Masking=3D2|NoDefMask|Space0F= 38|VexW1|Disp8MemShift=3D3|VecSIB256|NoSuf, { RegZMM, Qword|Unspecified|Bas= eIndex } -vscatterdps, 0x66A2, AVX512F, Modrm|EVex=3D1|Masking=3D2|NoDefMask|Space0F= 38|VexW0|Disp8MemShift=3D2|VecSIB512|NoSuf, { RegZMM, Dword|Unspecified|Bas= eIndex } -vscatterqpd, 0x66A3, AVX512F, Modrm|EVex512|Masking=3D2|NoDefMask|Space0F3= 8|VexW1|Disp8MemShift=3D3|VecSIB512|NoSuf, { RegZMM, Qword|Unspecified|Base= Index } -vscatterqps, 0x66A3, AVX512F, Modrm|EVex512|Masking=3D2|NoDefMask|Space0F3= 8|VexW0|Disp8MemShift=3D2|VecSIB512|NoSuf, { RegYMM, Dword|Unspecified|Base= Index } +vpscatterdd, 0x66A0, AVX512F, Modrm|EVex512|Masking|NoDefMask|Space0F38|Ve= xW0|Disp8MemShift=3D2|VecSIB512|NoSuf, { RegZMM, Dword|Unspecified|BaseInde= x } +vpscatterdq, 0x66A0, AVX512F, Modrm|EVex=3D1|Masking|NoDefMask|Space0F38|V= exW1|Disp8MemShift=3D3|VecSIB256|NoSuf, { RegZMM, Qword|Unspecified|BaseInd= ex } +vpscatterqd, 0x66A1, AVX512F, Modrm|EVex512|Masking|NoDefMask|Space0F38|Ve= xW0|Disp8MemShift=3D2|VecSIB512|NoSuf, { RegYMM, Dword|Unspecified|BaseInde= x } +vpscatterqq, 0x66A1, AVX512F, Modrm|EVex=3D1|Masking|NoDefMask|Space0F38|V= exW1|Disp8MemShift=3D3|VecSIB512|NoSuf, { RegZMM, Qword|Unspecified|BaseInd= ex } +vscatterdpd, 0x66A2, AVX512F, Modrm|EVex=3D1|Masking|NoDefMask|Space0F38|V= exW1|Disp8MemShift=3D3|VecSIB256|NoSuf, { RegZMM, Qword|Unspecified|BaseInd= ex } +vscatterdps, 0x66A2, AVX512F, Modrm|EVex=3D1|Masking|NoDefMask|Space0F38|V= exW0|Disp8MemShift=3D2|VecSIB512|NoSuf, { RegZMM, Dword|Unspecified|BaseInd= ex } +vscatterqpd, 0x66A3, AVX512F, Modrm|EVex512|Masking|NoDefMask|Space0F38|Ve= xW1|Disp8MemShift=3D3|VecSIB512|NoSuf, { RegZMM, Qword|Unspecified|BaseInde= x } +vscatterqps, 0x66A3, AVX512F, Modrm|EVex512|Masking|NoDefMask|Space0F38|Ve= xW0|Disp8MemShift=3D2|VecSIB512|NoSuf, { RegYMM, Dword|Unspecified|BaseInde= x } =20 -vcvtdq2pd, 0xF3E6, AVX512F, Modrm|EVex=3D1|Masking=3D3|Space0F|VexW=3D1|Br= oadcast|Disp8MemShift=3D5|NoSuf, { RegYMM|Dword|Unspecified|BaseIndex, RegZ= MM } -vcvtudq2pd, 0xF37A, AVX512F, Modrm|EVex=3D1|Masking=3D3|Space0F|VexW=3D1|B= roadcast|Disp8MemShift=3D5|NoSuf, { RegYMM|Dword|Unspecified|BaseIndex, Reg= ZMM } +vcvtdq2pd, 0xF3E6, AVX512F, Modrm|EVex=3D1|Masking|Space0F|VexW=3D1|Broadc= ast|Disp8MemShift=3D5|NoSuf, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } +vcvtudq2pd, 0xF37A, AVX512F, Modrm|EVex=3D1|Masking|Space0F|VexW=3D1|Broad= cast|Disp8MemShift=3D5|NoSuf, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } =20 -vcvtdq2ps, 0x5B, AVX512F, Modrm|Masking=3D3|Space0F|VexW0|Broadcast|Disp8S= hiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dw= ord|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtps2udq, 0x79, AVX512F, Modrm|Masking=3D3|Space0F|VexW0|Broadcast|Disp8= ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|D= word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtdq2ps, 0x5B, AVX512F, Modrm|Masking|Space0F|VexW0|Broadcast|Disp8Shift= VL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|= Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtps2udq, 0x79, AVX512F, Modrm|Masking|Space0F|VexW0|Broadcast|Disp8Shif= tVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword= |Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } =20 -vcvtpd2dq, 0xf2e6, AVX512F|, Modrm||Masking=3D3|Spa= ce0F|VexW1|Broadcast|NoSuf|, { |Qword, } +vcvtpd2dq, 0xf2e6, AVX512F|, Modrm||Masking|Space0F= |VexW1|Broadcast|NoSuf|, { |Qword, } =20 -vcvtpd2ps, 0x665a, AVX512F|, Modrm||Masking=3D3|Spa= ce0F|VexW1|Broadcast|NoSuf|, { |Qword, } +vcvtpd2ps, 0x665a, AVX512F|, Modrm||Masking|Space0F= |VexW1|Broadcast|NoSuf|, { |Qword, } =20 -vcvtpd2udq, 0x79, AVX512F|, Modrm||Masking=3D3|Spac= e0F|VexW1|Broadcast|NoSuf|, { |Qword, } +vcvtpd2udq, 0x79, AVX512F|, Modrm||Masking|Space0F|= VexW1|Broadcast|NoSuf|, { |Qword, } =20 -vcvtph2ps, 0x6613, AVX512F, Modrm|EVex512|Masking=3D3|Space0F38|VexW0|Disp= 8MemShift=3D5|NoSuf|SAE, { RegYMM|Unspecified|BaseIndex, RegZMM } +vcvtph2ps, 0x6613, AVX512F, Modrm|EVex512|Masking|Space0F38|VexW0|Disp8Mem= Shift=3D5|NoSuf|SAE, { RegYMM|Unspecified|BaseIndex, RegZMM } =20 -vcvtps2dq, 0x665B, AVX512F, Modrm|Masking=3D3|Space0F|VexW0|Broadcast|Disp= 8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|= Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtps2dq, 0x665B, AVX512F, Modrm|Masking|Space0F|VexW0|Broadcast|Disp8Shi= ftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dwor= d|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } =20 -vcvtps2pd, 0x5A, AVX512F, Modrm|EVex512|Masking=3D3|Space0F|VexW0|Broadcas= t|Disp8MemShift=3D5|NoSuf|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM= } +vcvtps2pd, 0x5A, AVX512F, Modrm|EVex512|Masking|Space0F|VexW0|Broadcast|Di= sp8MemShift=3D5|NoSuf|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } =20 -vcvtps2ph, 0x661D, AVX512F, Modrm|EVex512|MaskingMorZ|Space0F3A|VexW0|Disp= 8MemShift=3D5|NoSuf|SAE, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } +vcvtps2ph, 0x661D, AVX512F, Modrm|EVex512|Masking|Space0F3A|VexW0|Disp8Mem= Shift=3D5|NoSuf|SAE, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } =20 vcvts2si, 0x2d, AVX512F, Modrm|EVexLIG|Space0F|Disp8MemShift|= No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE, { RegXMM||Unspecified|= BaseIndex, Reg32|Reg64 } vcvts2usi, 0x79, , Modrm|EVexLIG||Disp8M= emShift|NoSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex= , Reg32|Reg64 } =20 -vcvtsd2ss, 0xF25A, AVX512F, Modrm|EVexLIG|Masking=3D3|Space0F|VexVVVV|VexW= 1|Disp8MemShift=3D3|NoSuf|StaticRounding|SAE, { RegXMM|Qword|Unspecified|Ba= seIndex, RegXMM, RegXMM } +vcvtsd2ss, 0xF25A, AVX512F, Modrm|EVexLIG|Masking|Space0F|VexVVVV|VexW1|Di= sp8MemShift=3D3|NoSuf|StaticRounding|SAE, { RegXMM|Qword|Unspecified|BaseIn= dex, RegXMM, RegXMM } =20 vcvtsi2sd, 0xF22A, AVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|Ign= oreSize|No_bSuf|No_wSuf|No_sSuf|ATTSyntax, { Reg32|Unspecified|BaseIndex, R= egXMM, RegXMM } vcvtsi2sd, 0xF22A, AVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|Ign= oreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg64|Unspe= cified|BaseIndex, RegXMM, RegXMM } @@ -2195,98 +2194,98 @@ vcvtsi2ss, 0xF32A, AVX512F, Modrm|EVexLIG|Space0F|V= exVVVV|Disp8ShiftVL|No_bSuf|N vcvtusi2ss, 0xF37B, AVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|Ig= noreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg32|Reg6= 4|Unspecified|BaseIndex, RegXMM, RegXMM } vcvtusi2ss, 0xF37B, AVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|No= _bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg32|Reg64|Unspeci= fied|BaseIndex, RegXMM, RegXMM } =20 -vcvtss2sd, 0xF35A, AVX512F, Modrm|EVexLIG|Masking=3D3|Space0F|VexVVVV|VexW= 0|Disp8MemShift=3D2|NoSuf|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM= , RegXMM } +vcvtss2sd, 0xF35A, AVX512F, Modrm|EVexLIG|Masking|Space0F|VexVVVV|VexW0|Di= sp8MemShift=3D2|NoSuf|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, Re= gXMM } =20 -vcvttpd2dq, 0x66e6, AVX512F|, Modrm||Masking=3D3|Sp= ace0F|VexW1|Broadcast|NoSuf|, { |Qword, } -vcvttpd2udq, 0x78, AVX512F|, Modrm||Masking=3D3|Spa= ce0F|VexW1|Broadcast|NoSuf|, { |Qword, } +vcvttpd2dq, 0x66e6, AVX512F|, Modrm||Masking|Space0= F|VexW1|Broadcast|NoSuf|, { |Qword, } +vcvttpd2udq, 0x78, AVX512F|, Modrm||Masking|Space0F= |VexW1|Broadcast|NoSuf|, { |Qword, } =20 -vcvttps2dq, 0xF35B, AVX512F, Modrm|Masking=3D3|Space0F|VexW0|Broadcast|Dis= p8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecif= ied|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvttps2udq, 0x78, AVX512F, Modrm|Masking=3D3|Space0F|VexW0|Broadcast|Disp= 8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecifi= ed|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvttps2dq, 0xF35B, AVX512F, Modrm|Masking|Space0F|VexW0|Broadcast|Disp8Sh= iftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|= BaseIndex, RegXMM|RegYMM|RegZMM } +vcvttps2udq, 0x78, AVX512F, Modrm|Masking|Space0F|VexW0|Broadcast|Disp8Shi= ftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|B= aseIndex, RegXMM|RegYMM|RegZMM } =20 vcvtts2si, 0x2c, AVX512F, Modrm|EVexLIG|Space0F|Disp8MemShift= |No_bSuf|No_wSuf|No_sSuf|SAE, { RegXMM||Unspecified|BaseIndex, Reg= 32|Reg64 } vcvtts2usi, 0x78, , Modrm|EVexLIG||Disp8= MemShift|NoSuf|SAE, { RegXMM||Unspecified|BaseIndex, Reg32|Reg64 } =20 -vcvtudq2ps, 0xF27A, AVX512F, Modrm|Masking=3D3|Space0F|VexW0|Broadcast|Dis= p8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM= |Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtudq2ps, 0xF27A, AVX512F, Modrm|Masking|Space0F|VexW0|Broadcast|Disp8Sh= iftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dwo= rd|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } =20 -vexpandpd, 0x6688, AVX512F, Modrm|Masking=3D3|Space0F38|VexW=3D2|Disp8MemS= hift=3D3|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseInd= ex, RegXMM|RegYMM|RegZMM } -vpexpandq, 0x6689, AVX512F, Modrm|Masking=3D3|Space0F38|VexW=3D2|Disp8MemS= hift=3D3|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseInd= ex, RegXMM|RegYMM|RegZMM } +vexpandpd, 0x6688, AVX512F, Modrm|Masking|Space0F38|VexW=3D2|Disp8MemShift= =3D3|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, = RegXMM|RegYMM|RegZMM } +vpexpandq, 0x6689, AVX512F, Modrm|Masking|Space0F38|VexW=3D2|Disp8MemShift= =3D3|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, = RegXMM|RegYMM|RegZMM } =20 -vexpandps, 0x6688, AVX512F, Modrm|Masking=3D3|Space0F38|VexW=3D1|Disp8MemS= hift=3D2|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseInd= ex, RegXMM|RegYMM|RegZMM } -vpexpandd, 0x6689, AVX512F, Modrm|Masking=3D3|Space0F38|VexW=3D1|Disp8MemS= hift=3D2|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseInd= ex, RegXMM|RegYMM|RegZMM } +vexpandps, 0x6688, AVX512F, Modrm|Masking|Space0F38|VexW=3D1|Disp8MemShift= =3D2|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, = RegXMM|RegYMM|RegZMM } +vpexpandd, 0x6689, AVX512F, Modrm|Masking|Space0F38|VexW=3D1|Disp8MemShift= =3D2|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, = RegXMM|RegYMM|RegZMM } =20 -vextractf32x4, 0x6619, AVX512F, Modrm|MaskingMorZ|Space0F3A|VexW=3D1|Disp8= MemShift=3D4|NoSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } -vextracti32x4, 0x6639, AVX512F, Modrm|MaskingMorZ|Space0F3A|VexW=3D1|Disp8= MemShift=3D4|NoSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } +vextractf32x4, 0x6619, AVX512F, Modrm|Masking|Space0F3A|VexW=3D1|Disp8MemS= hift=3D4|NoSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } +vextracti32x4, 0x6639, AVX512F, Modrm|Masking|Space0F3A|VexW=3D1|Disp8MemS= hift=3D4|NoSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } =20 -vextractf64x4, 0x661B, AVX512F, Modrm|EVex=3D1|MaskingMorZ|Space0F3A|VexW= =3D2|Disp8MemShift=3D5|NoSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } -vextracti64x4, 0x663B, AVX512F, Modrm|EVex=3D1|MaskingMorZ|Space0F3A|VexW= =3D2|Disp8MemShift=3D5|NoSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } +vextractf64x4, 0x661B, AVX512F, Modrm|EVex=3D1|Masking|Space0F3A|VexW=3D2|= Disp8MemShift=3D5|NoSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } +vextracti64x4, 0x663B, AVX512F, Modrm|EVex=3D1|Masking|Space0F3A|VexW=3D2|= Disp8MemShift=3D5|NoSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } =20 vextractps, 0x6617, AVX512F, Modrm|EVex128|Space0F3A|VexWIG|Disp8MemShift= =3D2|NoSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex } vextractps, 0x6617, AVX512F|x64, RegMem|EVex128|Space0F3A|VexWIG|NoSuf, { = Imm8, RegXMM, Reg64 } =20 -vfixupimmp, 0x6654, AVX512F, Modrm|Masking=3D3|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { Imm8|Imm8S, RegXM= M|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegX= MM|RegYMM|RegZMM } -vfixupimms, 0x6655, AVX512F, Modrm|EVexLIG|Masking=3D3|Space0F3A|VexVV= VV||Disp8MemShift|NoSuf|SAE, { Imm8|Imm8S, RegXMM||Unspec= ified|BaseIndex, RegXMM, RegXMM } - -vgetmantp, 0x26, , Modrm|Masking=3D3|Space0F3A||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { Imm8, RegXMM|Re= gYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vgetmants, 0x27, , Modrm|EVexLIG|Masking=3D3|Space0= F3A|VexVVVV||Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM||U= nspecified|BaseIndex, RegXMM, RegXMM } - -vrndscalep, 0x08 | , , Modrm|Masking=3D3|S= pace0F3A||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { Im= m8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|Re= gZMM } -vrndscales, 0x0a | , , Modrm|EVexLIG|Maski= ng=3D3|Space0F3A|VexVVVV||Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM= ||Unspecified|BaseIndex, RegXMM, RegXMM } - -vfmaddp, 0x6688 | 0x, , Modrm|Masking=3D3||VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|Sta= ticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, R= egXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfmadds, 0x6689 | 0x, , Modrm|EVexLIG|Masking= =3D3||VexVVVV||Disp8MemShift|NoSuf|StaticRounding|SAE, = { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vfmaddsubp, 0x6686 | 0x, , Modrm|Masking=3D3|<= sdh:spc2>|VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|= StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfmsubp, 0x668a | 0x, , Modrm|Masking=3D3||VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|Sta= ticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, R= egXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfmsubs, 0x668b | 0x, , Modrm|EVexLIG|Masking= =3D3||VexVVVV||Disp8MemShift|NoSuf|StaticRounding|SAE, = { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vfmsubaddp, 0x6687 | 0x, , Modrm|Masking=3D3|<= sdh:spc2>|VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|= StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex= , RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfnmaddp, 0x668c | 0x, , Modrm|Masking=3D3||VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|St= aticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, = RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfnmadds, 0x668d | 0x, , Modrm|EVexLIG|Masking= =3D3||VexVVVV||Disp8MemShift|NoSuf|StaticRounding|SAE, = { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vfnmsubp, 0x668e | 0x, , Modrm|Masking=3D3||VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|St= aticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, = RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfnmsubs, 0x668f | 0x, , Modrm|EVexLIG|Masking= =3D3||VexVVVV||Disp8MemShift|NoSuf|StaticRounding|SAE, = { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } - -vscalefp, 0x662c, , Modrm|Masking=3D3||VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, {= RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZM= M, RegXMM|RegYMM|RegZMM } -vscalefs, 0x662d, , Modrm|EVexLIG|Masking=3D3||Vex= VVVV||Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM|= |Unspecified|BaseIndex, RegXMM, RegXMM } - -vgatherdpd, 0x6692, AVX512F, Modrm|EVex=3D1|Masking=3D2|NoDefMask|Space0F3= 8|VexW1|Disp8MemShift=3D3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex, R= egZMM } -vgatherdps, 0x6692, AVX512F, Modrm|EVex512|Masking=3D2|NoDefMask|Space0F38= |VexW0|Disp8MemShift=3D2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex, Re= gZMM } -vgatherqpd, 0x6693, AVX512F, Modrm|EVex=3D1|Masking=3D2|NoDefMask|Space0F3= 8|VexW1|Disp8MemShift=3D3|VecSIB512|NoSuf, { Qword|Unspecified|BaseIndex, R= egZMM } -vgatherqps, 0x6693, AVX512F, Modrm|EVex512|Masking=3D2|NoDefMask|Space0F38= |VexW0|Disp8MemShift=3D2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex, Re= gYMM } -vpgatherdd, 0x6690, AVX512F, Modrm|EVex512|Masking=3D2|NoDefMask|Space0F38= |VexW0|Disp8MemShift=3D2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex, Re= gZMM } -vpgatherdq, 0x6690, AVX512F, Modrm|EVex=3D1|Masking=3D2|NoDefMask|Space0F3= 8|VexW1|Disp8MemShift=3D3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex, R= egZMM } -vpgatherqd, 0x6691, AVX512F, Modrm|EVex512|Masking=3D2|NoDefMask|Space0F38= |VexW0|Disp8MemShift=3D2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex, Re= gYMM } -vpgatherqq, 0x6691, AVX512F, Modrm|EVex=3D1|Masking=3D2|NoDefMask|Space0F3= 8|VexW1|Disp8MemShift=3D3|VecSIB512|NoSuf, { Qword|Unspecified|BaseIndex, R= egZMM } +vfixupimmp, 0x6654, AVX512F, Modrm|Masking|Space0F3A|VexVVVV|= |Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { Imm8|Imm8S, RegXMM|Re= gYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|R= egYMM|RegZMM } +vfixupimms, 0x6655, AVX512F, Modrm|EVexLIG|Masking|Space0F3A|VexVVVV|<= sd:vexw>|Disp8MemShift|NoSuf|SAE, { Imm8|Imm8S, RegXMM||Unspecifie= d|BaseIndex, RegXMM, RegXMM } + +vgetmantp, 0x26, , Modrm|Masking|Space0F3A||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { Imm8, RegXMM|RegYMM= |RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vgetmants, 0x27, , Modrm|EVexLIG|Masking|Space0F3A|= VexVVVV||Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM||Unspe= cified|BaseIndex, RegXMM, RegXMM } + +vrndscalep, 0x08 | , , Modrm|Masking|Space= 0F3A||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { Imm8, = RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM= } +vrndscales, 0x0a | , , Modrm|EVexLIG|Maski= ng|Space0F3A|VexVVVV||Disp8MemShift|NoSuf|SAE, { Imm8, RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } + +vfmaddp, 0x6688 | 0x, , Modrm|Masking||VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticR= ounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXM= M|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vfmadds, 0x6689 | 0x, , Modrm|EVexLIG|Masking|= |VexVVVV||Disp8MemShift|NoSuf|StaticRounding|SAE, { Reg= XMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vfmaddsubp, 0x6686 | 0x, , Modrm|Masking||VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|Stat= icRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, Re= gXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vfmsubp, 0x668a | 0x, , Modrm|Masking||VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticR= ounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXM= M|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vfmsubs, 0x668b | 0x, , Modrm|EVexLIG|Masking|= |VexVVVV||Disp8MemShift|NoSuf|StaticRounding|SAE, { Reg= XMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vfmsubaddp, 0x6687 | 0x, , Modrm|Masking||VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|Stat= icRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, Re= gXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vfnmaddp, 0x668c | 0x, , Modrm|Masking||VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|Static= Rounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegX= MM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vfnmadds, 0x668d | 0x, , Modrm|EVexLIG|Masking= ||VexVVVV||Disp8MemShift|NoSuf|StaticRounding|SAE, { Re= gXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vfnmsubp, 0x668e | 0x, , Modrm|Masking||VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|Static= Rounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegX= MM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vfnmsubs, 0x668f | 0x, , Modrm|EVexLIG|Masking= ||VexVVVV||Disp8MemShift|NoSuf|StaticRounding|SAE, { Re= gXMM||Unspecified|BaseIndex, RegXMM, RegXMM } + +vscalefp, 0x662c, , Modrm|Masking||VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|StaticRounding|SAE, { Reg= XMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, R= egXMM|RegYMM|RegZMM } +vscalefs, 0x662d, , Modrm|EVexLIG|Masking||VexVVVV= ||Disp8MemShift|NoSuf|StaticRounding|SAE, { RegXMM||Uns= pecified|BaseIndex, RegXMM, RegXMM } + +vgatherdpd, 0x6692, AVX512F, Modrm|EVex=3D1|Masking|NoDefMask|Space0F38|Ve= xW1|Disp8MemShift=3D3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex, RegZM= M } +vgatherdps, 0x6692, AVX512F, Modrm|EVex512|Masking|NoDefMask|Space0F38|Vex= W0|Disp8MemShift=3D2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex, RegZMM= } +vgatherqpd, 0x6693, AVX512F, Modrm|EVex=3D1|Masking|NoDefMask|Space0F38|Ve= xW1|Disp8MemShift=3D3|VecSIB512|NoSuf, { Qword|Unspecified|BaseIndex, RegZM= M } +vgatherqps, 0x6693, AVX512F, Modrm|EVex512|Masking|NoDefMask|Space0F38|Vex= W0|Disp8MemShift=3D2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex, RegYMM= } +vpgatherdd, 0x6690, AVX512F, Modrm|EVex512|Masking|NoDefMask|Space0F38|Vex= W0|Disp8MemShift=3D2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex, RegZMM= } +vpgatherdq, 0x6690, AVX512F, Modrm|EVex=3D1|Masking|NoDefMask|Space0F38|Ve= xW1|Disp8MemShift=3D3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex, RegZM= M } +vpgatherqd, 0x6691, AVX512F, Modrm|EVex512|Masking|NoDefMask|Space0F38|Vex= W0|Disp8MemShift=3D2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex, RegYMM= } +vpgatherqq, 0x6691, AVX512F, Modrm|EVex=3D1|Masking|NoDefMask|Space0F38|Ve= xW1|Disp8MemShift=3D3|VecSIB512|NoSuf, { Qword|Unspecified|BaseIndex, RegZM= M } =20 vmovntdqa, 0x662A, AVX512F, Modrm|Space0F38|VexW=3D1|Disp8ShiftVL|CheckOpe= randSize|NoSuf, { XMMword|YMMword|ZMMword|Unspecified|BaseIndex, RegXMM|Reg= YMM|RegZMM } =20 -vgetexpp, 0x6642, , Modrm|Masking=3D3|||= Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM|<= sdh:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vgetexps, 0x6643, , Modrm|EVexLIG|Masking=3D3||Vex= VVVV||Disp8MemShift|NoSuf|SAE, { RegXMM||Unspecified|Ba= seIndex, RegXMM, RegXMM } +vgetexpp, 0x6642, , Modrm|Masking|||Broa= dcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vgetexps, 0x6643, , Modrm|EVexLIG|Masking||VexVVVV= ||Disp8MemShift|NoSuf|SAE, { RegXMM||Unspecified|BaseIn= dex, RegXMM, RegXMM } =20 -vinsertf32x4, 0x6618, AVX512F, Modrm|Masking=3D3|Space0F3A|VexVVVV|VexW0|D= isp8MemShift=3D4|CheckOperandSize|NoSuf, { Imm8, RegXMM|XMMword|Unspecified= |BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vinserti32x4, 0x6638, AVX512F, Modrm|Masking=3D3|Space0F3A|VexVVVV|VexW0|D= isp8MemShift=3D4|CheckOperandSize|NoSuf, { Imm8, RegXMM|XMMword|Unspecified= |BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vinsertf32x4, 0x6618, AVX512F, Modrm|Masking|Space0F3A|VexVVVV|VexW0|Disp8= MemShift=3D4|CheckOperandSize|NoSuf, { Imm8, RegXMM|XMMword|Unspecified|Bas= eIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vinserti32x4, 0x6638, AVX512F, Modrm|Masking|Space0F3A|VexVVVV|VexW0|Disp8= MemShift=3D4|CheckOperandSize|NoSuf, { Imm8, RegXMM|XMMword|Unspecified|Bas= eIndex, RegYMM|RegZMM, RegYMM|RegZMM } =20 -vinsertf64x4, 0x661A, AVX512F, Modrm|EVex=3D1|Masking=3D3|Space0F3A|VexVVV= V|VexW1|Disp8MemShift=3D5|NoSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZ= MM, RegZMM } -vinserti64x4, 0x663A, AVX512F, Modrm|EVex=3D1|Masking=3D3|Space0F3A|VexVVV= V|VexW1|Disp8MemShift=3D5|NoSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZ= MM, RegZMM } +vinsertf64x4, 0x661A, AVX512F, Modrm|EVex=3D1|Masking|Space0F3A|VexVVVV|Ve= xW1|Disp8MemShift=3D5|NoSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, = RegZMM } +vinserti64x4, 0x663A, AVX512F, Modrm|EVex=3D1|Masking|Space0F3A|VexVVVV|Ve= xW1|Disp8MemShift=3D5|NoSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, = RegZMM } =20 vinsertps, 0x6621, AVX512F, Modrm|EVex128|Space0F3A|VexVVVV|VexW0|Disp8Mem= Shift=3D2|NoSuf, { Imm8, RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM= } =20 -vmaxp, 0x5f, , Modrm|Masking=3D3||VexVVV= V||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|Re= gYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|= RegYMM|RegZMM } -vmaxs, 0x5f, , Modrm|EVexLIG|Masking=3D3||VexVVVV||Disp8MemShift|NoSuf|SAE, { RegXMM||Unspecifi= ed|BaseIndex, RegXMM, RegXMM } +vmaxp, 0x5f, , Modrm|Masking||VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM= |RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegY= MM|RegZMM } +vmaxs, 0x5f, , Modrm|EVexLIG|Masking||Ve= xVVVV||Disp8MemShift|NoSuf|SAE, { RegXMM||Unspecified|B= aseIndex, RegXMM, RegXMM } =20 -vminp, 0x5d, , Modrm|Masking=3D3||VexVVV= V||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|Re= gYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|= RegYMM|RegZMM } -vmins, 0x5d, , Modrm|EVexLIG|Masking=3D3||VexVVVV||Disp8MemShift|NoSuf|SAE, { RegXMM||Unspecifi= ed|BaseIndex, RegXMM, RegXMM } +vminp, 0x5d, , Modrm|Masking||VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { RegXMM|RegYMM= |RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegY= MM|RegZMM } +vmins, 0x5d, , Modrm|EVexLIG|Masking||Ve= xVVVV||Disp8MemShift|NoSuf|SAE, { RegXMM||Unspecified|B= aseIndex, RegXMM, RegXMM } =20 -vmovap, 0x28, AVX512F, D|Modrm|MaskingMorZ|Space0F||= Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|Bas= eIndex, RegXMM|RegYMM|RegZMM } +vmovap, 0x28, AVX512F, D|Modrm|Masking|Space0F||Disp= 8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseInd= ex, RegXMM|RegYMM|RegZMM } vmovntp, 0x2B, AVX512F, Modrm|Space0F||Disp8ShiftVL|= CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM, XMMword|YMMword|ZMMword|Uns= pecified|BaseIndex } -vmovup, 0x10, AVX512F, D|Modrm|MaskingMorZ|Space0F||= Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|Bas= eIndex, RegXMM|RegYMM|RegZMM } +vmovup, 0x10, AVX512F, D|Modrm|Masking|Space0F||Disp= 8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseInd= ex, RegXMM|RegYMM|RegZMM } =20 vmovd, 0x666E, AVX512F, D|Modrm|EVex=3D2|Space0F|Disp8MemShift=3D2|NoSuf, = { Reg32|Unspecified|BaseIndex, RegXMM } =20 -vmovddup, 0xF212, AVX512F, Modrm|Masking=3D3|Space0F|VexW=3D2|Disp8ShiftVL= |CheckOperandSize|NoSuf, { RegYMM|RegZMM|Unspecified|BaseIndex, RegYMM|RegZ= MM } +vmovddup, 0xF212, AVX512F, Modrm|Masking|Space0F|VexW=3D2|Disp8ShiftVL|Che= ckOperandSize|NoSuf, { RegYMM|RegZMM|Unspecified|BaseIndex, RegYMM|RegZMM } =20 -vmovdqa64, 0x666F, AVX512F, D|Modrm|MaskingMorZ|Space0F|VexW=3D2|Disp8Shif= tVL|CheckOperandSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|Bas= eIndex, RegXMM|RegYMM|RegZMM } -vmovdqa32, 0x666F, AVX512F, D|Modrm|MaskingMorZ|Space0F|VexW=3D1|Disp8Shif= tVL|CheckOperandSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|Bas= eIndex, RegXMM|RegYMM|RegZMM } +vmovdqa64, 0x666F, AVX512F, D|Modrm|Masking|Space0F|VexW=3D2|Disp8ShiftVL|= CheckOperandSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseInd= ex, RegXMM|RegYMM|RegZMM } +vmovdqa32, 0x666F, AVX512F, D|Modrm|Masking|Space0F|VexW=3D1|Disp8ShiftVL|= CheckOperandSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseInd= ex, RegXMM|RegYMM|RegZMM } vmovntdq, 0x66E7, AVX512F, Modrm|Space0F|VexW=3D1|Disp8ShiftVL|CheckOperan= dSize|NoSuf, { RegXMM|RegYMM|RegZMM, XMMword|YMMword|ZMMword|Unspecified|Ba= seIndex } -vmovdqu32, 0xF36F, AVX512F, D|Modrm|MaskingMorZ|Space0F|VexW=3D1|Disp8Shif= tVL|CheckOperandSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|Bas= eIndex, RegXMM|RegYMM|RegZMM } -vmovdqu64, 0xF36F, AVX512F, D|Modrm|MaskingMorZ|Space0F|VexW=3D2|Disp8Shif= tVL|CheckOperandSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|Bas= eIndex, RegXMM|RegYMM|RegZMM } +vmovdqu32, 0xF36F, AVX512F, D|Modrm|Masking|Space0F|VexW=3D1|Disp8ShiftVL|= CheckOperandSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseInd= ex, RegXMM|RegYMM|RegZMM } +vmovdqu64, 0xF36F, AVX512F, D|Modrm|Masking|Space0F|VexW=3D2|Disp8ShiftVL|= CheckOperandSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseInd= ex, RegXMM|RegYMM|RegZMM } =20 vmovhlps, 0x12, AVX512F, Modrm|EVex=3D4|Space0F|VexVVVV|VexW0|NoSuf, { Reg= XMM, RegXMM, RegXMM } vmovlhps, 0x16, AVX512F, Modrm|EVex=3D4|Space0F|VexVVVV|VexW0|NoSuf, { Reg= XMM, RegXMM, RegXMM } @@ -2300,114 +2299,114 @@ vmovq, 0x666E, AVX512F|x64, D|Modrm|EVex128|Space= 0F|VexW1|Disp8MemShift=3D3|NoSuf, vmovq, 0xF37E, AVX512F, Load|Modrm|EVex=3D2|Space0F|VexW1|Disp8MemShift=3D= 3|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } vmovq, 0x66D6, AVX512F, Modrm|EVex=3D2|Space0F|VexW1|Disp8MemShift=3D3|NoS= uf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM } =20 -vmovs, 0x10, , D|Modrm|EVexLIG|MaskingMorZ|||Disp8MemShift|NoSuf, { |Unspecified|BaseIndex, Reg= XMM } -vmovs, 0x10, , D|Modrm|EVexLIG|Masking=3D3||VexVVVV||NoSuf, { RegXMM, RegXMM, RegXMM } - -vmovshdup, 0xF316, AVX512F, Modrm|Masking=3D3|Space0F|VexW=3D1|Disp8ShiftV= L|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, Reg= XMM|RegYMM|RegZMM } -vmovsldup, 0xF312, AVX512F, Modrm|Masking=3D3|Space0F|VexW=3D1|Disp8ShiftV= L|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, Reg= XMM|RegYMM|RegZMM } - -vpabs, 0x661e | , AVX512F, Modrm|Masking=3D3|Space0F38||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpaddd, 0x66FE, AVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|VexW0|Broadcast= |Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecif= ied|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpaddq, 0x66d4, AVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|VexW1|Broadcast= |Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecif= ied|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpand, 0x66db, AVX512F, Modrm|Masking=3D3|Space0F|VexVVVV||Br= oadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZM= M||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZ= MM } -vpandn, 0x66df, AVX512F, Modrm|Masking=3D3|Space0F|VexVVVV||B= roadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZ= MM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|Reg= ZMM } -vpmuludq, 0x66f4, AVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|VexW1|Broadca= st|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspec= ified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpor, 0x66eb, AVX512F, Modrm|Masking=3D3|Space0F|VexVVVV||Bro= adcast|Disp8ShiftVL|CheckOperandSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM= ||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZM= M } -vpsub, 0x66fa | , AVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|<= dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|Optimize, { RegXMM|R= egYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|= RegYMM|RegZMM } -vpunpckhdq, 0x666A, AVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|VexW0|Broad= cast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unsp= ecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpunpckhqdq, 0x666d, AVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|VexW1|Broa= dcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Uns= pecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpunpckldq, 0x6662, AVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|VexW0|Broad= cast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unsp= ecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpunpcklqdq, 0x666c, AVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|VexW1|Broa= dcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Uns= pecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpxor, 0x66ef, AVX512F, Modrm|Masking=3D3|Space0F|VexVVVV||Br= oadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZM= M||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZ= MM } +vmovs, 0x10, , D|Modrm|EVexLIG|Masking||= |Disp8MemShift|NoSuf, { |Unspecified|BaseIndex, RegXMM } +vmovs, 0x10, , D|Modrm|EVexLIG|Masking||= VexVVVV||NoSuf, { RegXMM, RegXMM, RegXMM } + +vmovshdup, 0xF316, AVX512F, Modrm|Masking|Space0F|VexW=3D1|Disp8ShiftVL|Ch= eckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|= RegYMM|RegZMM } +vmovsldup, 0xF312, AVX512F, Modrm|Masking|Space0F|VexW=3D1|Disp8ShiftVL|Ch= eckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|= RegYMM|RegZMM } + +vpabs, 0x661e | , AVX512F, Modrm|Masking|Space0F38||B= roadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpaddd, 0x66FE, AVX512F, Modrm|Masking|Space0F|VexVVVV|VexW0|Broadcast|Dis= p8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|= BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpaddq, 0x66d4, AVX512F, Modrm|Masking|Space0F|VexVVVV|VexW1|Broadcast|Dis= p8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|= BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpand, 0x66db, AVX512F, Modrm|Masking|Space0F|VexVVVV||Broadc= ast|Disp8ShiftVL|CheckOperandSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpandn, 0x66df, AVX512F, Modrm|Masking|Space0F|VexVVVV||Broad= cast|Disp8ShiftVL|CheckOperandSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|<= dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmuludq, 0x66f4, AVX512F, Modrm|Masking|Space0F|VexVVVV|VexW1|Broadcast|D= isp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecifie= d|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpor, 0x66eb, AVX512F, Modrm|Masking|Space0F|VexVVVV||Broadca= st|Disp8ShiftVL|CheckOperandSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsub, 0x66fa | , AVX512F, Modrm|Masking|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|Optimize, { RegXMM|RegYM= M|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegY= MM|RegZMM } +vpunpckhdq, 0x666A, AVX512F, Modrm|Masking|Space0F|VexVVVV|VexW0|Broadcast= |Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecif= ied|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpunpckhqdq, 0x666d, AVX512F, Modrm|Masking|Space0F|VexVVVV|VexW1|Broadcas= t|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspeci= fied|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpunpckldq, 0x6662, AVX512F, Modrm|Masking|Space0F|VexVVVV|VexW0|Broadcast= |Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecif= ied|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpunpcklqdq, 0x666c, AVX512F, Modrm|Masking|Space0F|VexVVVV|VexW1|Broadcas= t|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspeci= fied|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpxor, 0x66ef, AVX512F, Modrm|Masking|Space0F|VexVVVV||Broadc= ast|Disp8ShiftVL|CheckOperandSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } =20 =20 -vpcmpeqd, 0x6676, AVX512F, Modrm|Masking=3D2|Space0F|VexVVVV|VexW0|Broadca= st|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspec= ified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmpeqq, 0x6629, AVX512F, Modrm|Masking=3D2|Space0F38|VexVVVV|VexW1|Broad= cast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unsp= ecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmpgtd, 0x6666, AVX512F, Modrm|Masking=3D2|Space0F|VexVVVV|VexW0|Broadca= st|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspec= ified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmpgtq, 0x6637, AVX512F, Modrm|Masking=3D2|Space0F38|VexVVVV|VexW1|Broad= cast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unsp= ecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmp, 0x661f, AVX512F, Modrm|Masking=3D2|Space0F3A|VexVVVV||= Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM= ||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmpu, 0x661e, AVX512F, Modrm|Masking=3D2|Space0F3A|VexVVVV|= |Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZM= M||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmp, 0x661f/, AVX512F, Modrm|Masking=3D2|Space0F3A|V= exVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|ImmExt, { Re= gXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, R= egMask } -vpcmpu, 0x661e/, AVX512F, Modrm|Masking=3D2|Space0F3A|= VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|ImmExt, { R= egXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, = RegMask } +vpcmpeqd, 0x6676, AVX512F, Modrm|Masking|Space0F|VexVVVV|VexW0|Broadcast|D= isp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecifie= d|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmpeqq, 0x6629, AVX512F, Modrm|Masking|Space0F38|VexVVVV|VexW1|Broadcast= |Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecif= ied|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmpgtd, 0x6666, AVX512F, Modrm|Masking|Space0F|VexVVVV|VexW0|Broadcast|D= isp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecifie= d|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmpgtq, 0x6637, AVX512F, Modrm|Masking|Space0F38|VexVVVV|VexW1|Broadcast= |Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecif= ied|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmp, 0x661f, AVX512F, Modrm|Masking|Space0F3A|VexVVVV||Broa= dcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmpu, 0x661e, AVX512F, Modrm|Masking|Space0F3A|VexVVVV||Bro= adcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmp, 0x661f/, AVX512F, Modrm|Masking|Space0F3A|VexVV= VV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|ImmExt, { RegXMM= |RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMa= sk } +vpcmpu, 0x661e/, AVX512F, Modrm|Masking|Space0F3A|VexV= VVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|ImmExt, { RegXM= M|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegM= ask } =20 -vptestm, 0x6627, AVX512F, Modrm|Masking=3D2|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vptestnm, 0xf327, AVX512F, Modrm|Masking=3D2|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vptestm, 0x6627, AVX512F, Modrm|Masking|Space0F38|VexVVVV||Br= oadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vptestnm, 0xf327, AVX512F, Modrm|Masking|Space0F38|VexVVVV||B= roadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } =20 -vpermd, 0x6636, AVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV|VexW0|Broadca= st|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegYMM|RegZMM|Dword|Unspecified|B= aseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vpermps, 0x6616, AVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV|VexW0|Broadc= ast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegYMM|RegZMM|Dword|Unspecified|= BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vpermd, 0x6636, AVX512F, Modrm|Masking|Space0F38|VexVVVV|VexW0|Broadcast|D= isp8ShiftVL|CheckOperandSize|NoSuf, { RegYMM|RegZMM|Dword|Unspecified|BaseI= ndex, RegYMM|RegZMM, RegYMM|RegZMM } +vpermps, 0x6616, AVX512F, Modrm|Masking|Space0F38|VexVVVV|VexW0|Broadcast|= Disp8ShiftVL|CheckOperandSize|NoSuf, { RegYMM|RegZMM|Dword|Unspecified|Base= Index, RegYMM|RegZMM, RegYMM|RegZMM } =20 -vpermilp, 0x6604 | , AVX512F, Modrm|Masking=3D3|Space0F3A||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|R= egYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpermilp, 0x660C | , AVX512F, Modrm|Masking=3D3|Space0F38|VexV= VVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYM= M|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegY= MM|RegZMM } +vpermilp, 0x6604 | , AVX512F, Modrm|Masking|Space0F3A||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|RegYM= M|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpermilp, 0x660C | , AVX512F, Modrm|Masking|Space0F38|VexVVVV|= |Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Re= gZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|R= egZMM } =20 -vpermpd, 0x6601, AVX512F, Modrm|Masking=3D3|Space0F3A|VexW=3D2|Broadcast|D= isp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegYMM|RegZMM|Qword|Unspe= cified|BaseIndex, RegYMM|RegZMM } -vpermpd, 0x6616, AVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV|VexW1|Broadc= ast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegYMM|RegZMM|Qword|Unspecified|= BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vpermq, 0x6600, AVX512F, Modrm|Masking=3D3|Space0F3A|VexW=3D2|Broadcast|Di= sp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegYMM|RegZMM|Qword|Unspec= ified|BaseIndex, RegYMM|RegZMM } -vpermq, 0x6636, AVX512F, Modrm|Masking=3D3|Space0F38|VexVVVV|VexW1|Broadca= st|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegYMM|RegZMM|Qword|Unspecified|B= aseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vpermpd, 0x6601, AVX512F, Modrm|Masking|Space0F3A|VexW=3D2|Broadcast|Disp8= ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegYMM|RegZMM|Qword|Unspecifi= ed|BaseIndex, RegYMM|RegZMM } +vpermpd, 0x6616, AVX512F, Modrm|Masking|Space0F38|VexVVVV|VexW1|Broadcast|= Disp8ShiftVL|CheckOperandSize|NoSuf, { RegYMM|RegZMM|Qword|Unspecified|Base= Index, RegYMM|RegZMM, RegYMM|RegZMM } +vpermq, 0x6600, AVX512F, Modrm|Masking|Space0F3A|VexW=3D2|Broadcast|Disp8S= hiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegYMM|RegZMM|Qword|Unspecifie= d|BaseIndex, RegYMM|RegZMM } +vpermq, 0x6636, AVX512F, Modrm|Masking|Space0F38|VexVVVV|VexW1|Broadcast|D= isp8ShiftVL|CheckOperandSize|NoSuf, { RegYMM|RegZMM|Qword|Unspecified|BaseI= ndex, RegYMM|RegZMM, RegYMM|RegZMM } =20 -vpmovdb, 0xF331, AVX512F, Modrm|EVex=3D1|MaskingMorZ|Space0F38|VexW=3D1|Di= sp8MemShift=3D4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } -vpmovsdb, 0xF321, AVX512F, Modrm|EVex=3D1|MaskingMorZ|Space0F38|VexW=3D1|D= isp8MemShift=3D4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } -vpmovusdb, 0xF311, AVX512F, Modrm|EVex=3D1|MaskingMorZ|Space0F38|VexW=3D1|= Disp8MemShift=3D4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } +vpmovdb, 0xF331, AVX512F, Modrm|EVex=3D1|Masking|Space0F38|VexW=3D1|Disp8M= emShift=3D4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } +vpmovsdb, 0xF321, AVX512F, Modrm|EVex=3D1|Masking|Space0F38|VexW=3D1|Disp8= MemShift=3D4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } +vpmovusdb, 0xF311, AVX512F, Modrm|EVex=3D1|Masking|Space0F38|VexW=3D1|Disp= 8MemShift=3D4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } =20 -vpmovdw, 0xF333, AVX512F, Modrm|EVex=3D1|MaskingMorZ|Space0F38|VexW=3D1|Di= sp8MemShift=3D5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } -vpmovsdw, 0xF323, AVX512F, Modrm|EVex=3D1|MaskingMorZ|Space0F38|VexW=3D1|D= isp8MemShift=3D5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } -vpmovusdw, 0xF313, AVX512F, Modrm|EVex=3D1|MaskingMorZ|Space0F38|VexW=3D1|= Disp8MemShift=3D5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } +vpmovdw, 0xF333, AVX512F, Modrm|EVex=3D1|Masking|Space0F38|VexW=3D1|Disp8M= emShift=3D5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } +vpmovsdw, 0xF323, AVX512F, Modrm|EVex=3D1|Masking|Space0F38|VexW=3D1|Disp8= MemShift=3D5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } +vpmovusdw, 0xF313, AVX512F, Modrm|EVex=3D1|Masking|Space0F38|VexW=3D1|Disp= 8MemShift=3D5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } =20 -vpmovqb, 0xF332, AVX512F, Modrm|EVex=3D1|MaskingMorZ|Space0F38|VexW0|Disp8= MemShift=3D3|NoSuf, { RegZMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovsqb, 0xF322, AVX512F, Modrm|EVex=3D1|MaskingMorZ|Space0F38|VexW0|Disp= 8MemShift=3D3|NoSuf, { RegZMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovusqb, 0xF312, AVX512F, Modrm|EVex=3D1|MaskingMorZ|Space0F38|VexW0|Dis= p8MemShift=3D3|NoSuf, { RegZMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovqb, 0xF332, AVX512F, Modrm|EVex=3D1|Masking|Space0F38|VexW0|Disp8MemS= hift=3D3|NoSuf, { RegZMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovsqb, 0xF322, AVX512F, Modrm|EVex=3D1|Masking|Space0F38|VexW0|Disp8Mem= Shift=3D3|NoSuf, { RegZMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovusqb, 0xF312, AVX512F, Modrm|EVex=3D1|Masking|Space0F38|VexW0|Disp8Me= mShift=3D3|NoSuf, { RegZMM, RegXMM|Qword|Unspecified|BaseIndex } =20 -vpmovqd, 0xF335, AVX512F, Modrm|EVex=3D1|MaskingMorZ|Space0F38|VexW=3D1|Di= sp8MemShift=3D5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } -vpmovsqd, 0xF325, AVX512F, Modrm|EVex=3D1|MaskingMorZ|Space0F38|VexW=3D1|D= isp8MemShift=3D5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } -vpmovusqd, 0xF315, AVX512F, Modrm|EVex=3D1|MaskingMorZ|Space0F38|VexW=3D1|= Disp8MemShift=3D5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } +vpmovqd, 0xF335, AVX512F, Modrm|EVex=3D1|Masking|Space0F38|VexW=3D1|Disp8M= emShift=3D5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } +vpmovsqd, 0xF325, AVX512F, Modrm|EVex=3D1|Masking|Space0F38|VexW=3D1|Disp8= MemShift=3D5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } +vpmovusqd, 0xF315, AVX512F, Modrm|EVex=3D1|Masking|Space0F38|VexW=3D1|Disp= 8MemShift=3D5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } =20 -vpmovqw, 0xF334, AVX512F, Modrm|EVex=3D1|MaskingMorZ|Space0F38|VexW=3D1|Di= sp8MemShift=3D4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } -vpmovsqw, 0xF324, AVX512F, Modrm|EVex=3D1|MaskingMorZ|Space0F38|VexW=3D1|D= isp8MemShift=3D4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } -vpmovusqw, 0xF314, AVX512F, Modrm|EVex=3D1|MaskingMorZ|Space0F38|VexW=3D1|= Disp8MemShift=3D4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } +vpmovqw, 0xF334, AVX512F, Modrm|EVex=3D1|Masking|Space0F38|VexW=3D1|Disp8M= emShift=3D4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } +vpmovsqw, 0xF324, AVX512F, Modrm|EVex=3D1|Masking|Space0F38|VexW=3D1|Disp8= MemShift=3D4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } +vpmovusqw, 0xF314, AVX512F, Modrm|EVex=3D1|Masking|Space0F38|VexW=3D1|Disp= 8MemShift=3D4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } =20 -vpmovsxbd, 0x6621, AVX512F, Modrm|EVex=3D1|Masking=3D3|Space0F38|VexWIG|Di= sp8MemShift=3D4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegZMM } -vpmovzxbd, 0x6631, AVX512F, Modrm|EVex=3D1|Masking=3D3|Space0F38|VexWIG|Di= sp8MemShift=3D4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegZMM } +vpmovsxbd, 0x6621, AVX512F, Modrm|EVex=3D1|Masking|Space0F38|VexWIG|Disp8M= emShift=3D4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegZMM } +vpmovzxbd, 0x6631, AVX512F, Modrm|EVex=3D1|Masking|Space0F38|VexWIG|Disp8M= emShift=3D4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegZMM } =20 -vpmovsxbq, 0x6622, AVX512F, Modrm|EVex=3D1|Masking=3D3|Space0F38|VexWIG|Di= sp8MemShift=3D3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegZMM } -vpmovzxbq, 0x6632, AVX512F, Modrm|EVex=3D1|Masking=3D3|Space0F38|VexWIG|Di= sp8MemShift=3D3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegZMM } +vpmovsxbq, 0x6622, AVX512F, Modrm|EVex=3D1|Masking|Space0F38|VexWIG|Disp8M= emShift=3D3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegZMM } +vpmovzxbq, 0x6632, AVX512F, Modrm|EVex=3D1|Masking|Space0F38|VexWIG|Disp8M= emShift=3D3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegZMM } =20 -vpmovsxdq, 0x6625, AVX512F, Modrm|EVex=3D1|Masking=3D3|Space0F38|VexW=3D1|= Disp8MemShift=3D5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } -vpmovzxdq, 0x6635, AVX512F, Modrm|EVex=3D1|Masking=3D3|Space0F38|VexW=3D1|= Disp8MemShift=3D5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } +vpmovsxdq, 0x6625, AVX512F, Modrm|EVex=3D1|Masking|Space0F38|VexW=3D1|Disp= 8MemShift=3D5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } +vpmovzxdq, 0x6635, AVX512F, Modrm|EVex=3D1|Masking|Space0F38|VexW=3D1|Disp= 8MemShift=3D5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } =20 -vpmovsxwd, 0x6623, AVX512F, Modrm|EVex=3D1|Masking=3D3|Space0F38|VexWIG|Di= sp8MemShift=3D5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } -vpmovzxwd, 0x6633, AVX512F, Modrm|EVex=3D1|Masking=3D3|Space0F38|VexWIG|Di= sp8MemShift=3D5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } +vpmovsxwd, 0x6623, AVX512F, Modrm|EVex=3D1|Masking|Space0F38|VexWIG|Disp8M= emShift=3D5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } +vpmovzxwd, 0x6633, AVX512F, Modrm|EVex=3D1|Masking|Space0F38|VexWIG|Disp8M= emShift=3D5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } =20 -vpmovsxwq, 0x6624, AVX512F, Modrm|EVex=3D1|Masking=3D3|Space0F38|VexWIG|Di= sp8MemShift=3D4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegZMM } -vpmovzxwq, 0x6634, AVX512F, Modrm|EVex=3D1|Masking=3D3|Space0F38|VexWIG|Di= sp8MemShift=3D4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegZMM } +vpmovsxwq, 0x6624, AVX512F, Modrm|EVex=3D1|Masking|Space0F38|VexWIG|Disp8M= emShift=3D4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegZMM } +vpmovzxwq, 0x6634, AVX512F, Modrm|EVex=3D1|Masking|Space0F38|VexWIG|Disp8M= emShift=3D4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegZMM } =20 -vprol, 0x6672/1, AVX512F, Modrm|Masking=3D3|Space0F|VexVVVV||= Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|RegYMM|= RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpror, 0x6672/0, AVX512F, Modrm|Masking=3D3|Space0F|VexVVVV||= Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|RegYMM|= RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vprol, 0x6672/1, AVX512F, Modrm|Masking|Space0F|VexVVVV||Broa= dcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|RegYMM|RegZ= MM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpror, 0x6672/0, AVX512F, Modrm|Masking|Space0F|VexVVVV||Broa= dcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|RegYMM|RegZ= MM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } =20 -vpshufd, 0x6670, AVX512F, Modrm|Masking=3D3|Space0F|VexW=3D1|Broadcast|Dis= p8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM|Dword|= Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpshufd, 0x6670, AVX512F, Modrm|Masking|Space0F|VexW=3D1|Broadcast|Disp8Sh= iftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM|Dword|Unsp= ecified|BaseIndex, RegXMM|RegYMM|RegZMM } =20 -vpsll, 0x66f2 | , AVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|<= dq:vexw>|Disp8MemShift=3D4|CheckOperandSize|NoSuf, { RegXMM|Unspecified|Bas= eIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsll, 0x6672 | /6, AVX512F, Modrm|Masking=3D3|Space0F|VexVVVV= ||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|Re= gYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpsra, 0x66e2, AVX512F, Modrm|Masking=3D3|Space0F|VexVVVV||Di= sp8MemShift=3D4|CheckOperandSize|NoSuf, { RegXMM|Unspecified|BaseIndex, Reg= XMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsra, 0x6672/4, AVX512F, Modrm|Masking=3D3|Space0F|VexVVVV||= Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM= ||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpsrl, 0x66d2 | , AVX512F, Modrm|Masking=3D3|Space0F|VexVVVV|<= dq:vexw>|Disp8MemShift=3D4|CheckOperandSize|NoSuf, { RegXMM|Unspecified|Bas= eIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsrl, 0x6672 | /2, AVX512F, Modrm|Masking=3D3|Space0F|VexVVVV= ||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|Re= gYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpsll, 0x66f2 | , AVX512F, Modrm|Masking|Space0F|VexVVVV||Disp8MemShift=3D4|CheckOperandSize|NoSuf, { RegXMM|Unspecified|BaseInd= ex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsll, 0x6672 | /6, AVX512F, Modrm|Masking|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM= |RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpsra, 0x66e2, AVX512F, Modrm|Masking|Space0F|VexVVVV||Disp8M= emShift=3D4|CheckOperandSize|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|= RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsra, 0x6672/4, AVX512F, Modrm|Masking|Space0F|VexVVVV||Broa= dcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpsrl, 0x66d2 | , AVX512F, Modrm|Masking|Space0F|VexVVVV||Disp8MemShift=3D4|CheckOperandSize|NoSuf, { RegXMM|Unspecified|BaseInd= ex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsrl, 0x6672 | /2, AVX512F, Modrm|Masking|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM= |RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } =20 -vrcp14p, 0x664C, AVX512F, Modrm|Masking=3D3|Space0F38||Broadc= ast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||U= nspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vrcp14s, 0x664D, AVX512F, Modrm|EVexLIG|Masking=3D3|Space0F38|VexVVVV|= |Disp8MemShift|NoSuf, { RegXMM||Unspecified|BaseIndex, Re= gXMM, RegXMM } +vrcp14p, 0x664C, AVX512F, Modrm|Masking|Space0F38||Broadcast|= Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspe= cified|BaseIndex, RegXMM|RegYMM|RegZMM } +vrcp14s, 0x664D, AVX512F, Modrm|EVexLIG|Masking|Space0F38|VexVVVV||Disp8MemShift|NoSuf, { RegXMM||Unspecified|BaseIndex, RegXMM= , RegXMM } =20 -vrsqrt14p, 0x664E, AVX512F, Modrm|Masking=3D3|Space0F38||Broa= dcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|= |Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vrsqrt14s, 0x664F, AVX512F, Modrm|EVexLIG|Masking=3D3|Space0F38|VexVVV= V||Disp8MemShift|NoSuf, { RegXMM||Unspecified|BaseIndex, = RegXMM, RegXMM } +vrsqrt14p, 0x664E, AVX512F, Modrm|Masking|Space0F38||Broadcas= t|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Uns= pecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vrsqrt14s, 0x664F, AVX512F, Modrm|EVexLIG|Masking|Space0F38|VexVVVV||Disp8MemShift|NoSuf, { RegXMM||Unspecified|BaseIndex, RegX= MM, RegXMM } =20 -vshuff32x4, 0x6623, AVX512F, Modrm|Masking=3D3|Space0F3A|VexVVVV|VexW0|Bro= adcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegYMM|RegZMM|Dwo= rd|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vshufi32x4, 0x6643, AVX512F, Modrm|Masking=3D3|Space0F3A|VexVVVV|VexW0|Bro= adcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegYMM|RegZMM|Dwo= rd|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vshuff32x4, 0x6623, AVX512F, Modrm|Masking|Space0F3A|VexVVVV|VexW0|Broadca= st|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegYMM|RegZMM|Dword|U= nspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vshufi32x4, 0x6643, AVX512F, Modrm|Masking|Space0F3A|VexVVVV|VexW0|Broadca= st|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegYMM|RegZMM|Dword|U= nspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } =20 -vshuff64x2, 0x6623, AVX512F, Modrm|Masking=3D3|Space0F3A|VexVVVV|VexW1|Bro= adcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegYMM|RegZMM|Qwo= rd|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vshufi64x2, 0x6643, AVX512F, Modrm|Masking=3D3|Space0F3A|VexVVVV|VexW1|Bro= adcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegYMM|RegZMM|Qwo= rd|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vshuff64x2, 0x6623, AVX512F, Modrm|Masking|Space0F3A|VexVVVV|VexW1|Broadca= st|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegYMM|RegZMM|Qword|U= nspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vshufi64x2, 0x6643, AVX512F, Modrm|Masking|Space0F3A|VexVVVV|VexW1|Broadca= st|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegYMM|RegZMM|Qword|U= nspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } =20 -vshufp, 0xC6, AVX512F, Modrm|Masking=3D3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|R= egYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|= RegYMM|RegZMM } +vshufp, 0xC6, AVX512F, Modrm|Masking|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|RegYM= M|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegY= MM|RegZMM } =20 -vunpckhp, 0x15, AVX512F, Modrm|Masking=3D3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZ= MM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|Reg= ZMM } -vunpcklp, 0x14, AVX512F, Modrm|Masking=3D3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZ= MM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|Reg= ZMM } +vunpckhp, 0x15, AVX512F, Modrm|Masking|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<= sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vunpcklp, 0x14, AVX512F, Modrm|Masking|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<= sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } =20 // AVX512F instructions end. =20 @@ -2416,39 +2415,39 @@ vunpcklp, 0x14, AVX512F, Modrm|Masking= =3D3|Space0F|VexVVVV|| vpbroadcastmb2q, 0xF32A, AVX512CD, Modrm|Space0F38|EVex=3D5|VexW=3D2|NoSuf= , { RegMask, RegXMM|RegYMM|RegZMM } vpbroadcastmw2d, 0xF33A, AVX512CD, Modrm|Space0F38|EVex=3D5|VexW=3D1|NoSuf= , { RegMask, RegXMM|RegYMM|RegZMM } =20 -vpconflict, 0x66c4, AVX512CD, Modrm|Masking=3D3|Space0F38||Br= oadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpconflict, 0x66c4, AVX512CD, Modrm|Masking|Space0F38||Broadc= ast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||U= nspecified|BaseIndex, RegXMM|RegYMM|RegZMM } =20 -vplzcnt, 0x6644, AVX512CD, Modrm|Masking=3D3|Space0F38||Broad= cast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||= Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vplzcnt, 0x6644, AVX512CD, Modrm|Masking|Space0F38||Broadcast= |Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM||Unsp= ecified|BaseIndex, RegXMM|RegYMM|RegZMM } =20 // AVX512CD instructions end. =20 // AVX512ER instructions. =20 -vexp2p, 0x66C8, AVX512ER, Modrm|EVex512|Masking=3D3|Space0F38||Broadcast|Disp8MemShift=3D6|NoSuf|SAE, { RegZMM||Unspecified|Bas= eIndex, RegZMM } +vexp2p, 0x66C8, AVX512ER, Modrm|EVex512|Masking|Space0F38||Br= oadcast|Disp8MemShift=3D6|NoSuf|SAE, { RegZMM||Unspecified|BaseInd= ex, RegZMM } =20 -vrcp28p, 0x66CA, AVX512ER, Modrm|EVex512|Masking=3D3|Space0F38||Broadcast|Disp8MemShift=3D6|NoSuf|SAE, { RegZMM||Unspecified|Ba= seIndex, RegZMM } -vrcp28s, 0x66CB, AVX512ER, Modrm|EVexLIG|Masking=3D3|Space0F38|VexVVVV= ||Disp8MemShift|NoSuf|SAE, { RegXMM||Unspecified|BaseInde= x, RegXMM, RegXMM } +vrcp28p, 0x66CA, AVX512ER, Modrm|EVex512|Masking|Space0F38||B= roadcast|Disp8MemShift=3D6|NoSuf|SAE, { RegZMM||Unspecified|BaseIn= dex, RegZMM } +vrcp28s, 0x66CB, AVX512ER, Modrm|EVexLIG|Masking|Space0F38|VexVVVV||Disp8MemShift|NoSuf|SAE, { RegXMM||Unspecified|BaseIndex, R= egXMM, RegXMM } =20 -vrsqrt28p, 0x66CC, AVX512ER, Modrm|EVex512|Masking=3D3|Space0F38||Broadcast|Disp8MemShift=3D6|NoSuf|SAE, { RegZMM||Unspecified|= BaseIndex, RegZMM } -vrsqrt28s, 0x66CD, AVX512ER, Modrm|EVexLIG|Masking=3D3|Space0F38|VexVV= VV||Disp8MemShift|NoSuf|SAE, { RegXMM||Unspecified|BaseIn= dex, RegXMM, RegXMM } +vrsqrt28p, 0x66CC, AVX512ER, Modrm|EVex512|Masking|Space0F38|= |Broadcast|Disp8MemShift=3D6|NoSuf|SAE, { RegZMM||Unspecified|Base= Index, RegZMM } +vrsqrt28s, 0x66CD, AVX512ER, Modrm|EVexLIG|Masking|Space0F38|VexVVVV|<= sd:vexw>|Disp8MemShift|NoSuf|SAE, { RegXMM||Unspecified|BaseIndex,= RegXMM, RegXMM } =20 // AVX512ER instructions end. =20 // AVX512PF instructions. =20 -vgatherpf0dpd, 0x66C6/1, AVX512PF, Modrm|EVex=3D1|Masking=3D2|NoDefMask|Sp= ace0F38|VexW1|Disp8MemShift=3D3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIn= dex } -vgatherpf0dps, 0x66C6/1, AVX512PF, Modrm|EVex512|Masking=3D2|NoDefMask|Spa= ce0F38|VexW0|Disp8MemShift=3D2|VecSIB512|NoSuf, { Dword|Unspecified|BaseInd= ex } -vgatherpf0qp, 0x66C7/1, AVX512PF, Modrm|EVex512|Masking=3D2|NoDefMask|= Space0F38||Disp8MemShift|VecSIB512|NoSuf, { |Unspecified|= BaseIndex } -vgatherpf1dpd, 0x66C6/2, AVX512PF, Modrm|EVex=3D1|Masking=3D2|NoDefMask|Sp= ace0F38|VexW1|Disp8MemShift=3D3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIn= dex } -vgatherpf1dps, 0x66C6/2, AVX512PF, Modrm|EVex512|Masking=3D2|NoDefMask|Spa= ce0F38|VexW0|Disp8MemShift=3D2|VecSIB512|NoSuf, { Dword|Unspecified|BaseInd= ex } -vgatherpf1qp, 0x66C7/2, AVX512PF, Modrm|EVex512|Masking=3D2|NoDefMask|= Space0F38||Disp8MemShift|VecSIB512|NoSuf, { |Unspecified|= BaseIndex } +vgatherpf0dpd, 0x66C6/1, AVX512PF, Modrm|EVex=3D1|Masking|NoDefMask|Space0= F38|VexW1|Disp8MemShift=3D3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex } +vgatherpf0dps, 0x66C6/1, AVX512PF, Modrm|EVex512|Masking|NoDefMask|Space0F= 38|VexW0|Disp8MemShift=3D2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex } +vgatherpf0qp, 0x66C7/1, AVX512PF, Modrm|EVex512|Masking|NoDefMask|Spac= e0F38||Disp8MemShift|VecSIB512|NoSuf, { |Unspecified|Base= Index } +vgatherpf1dpd, 0x66C6/2, AVX512PF, Modrm|EVex=3D1|Masking|NoDefMask|Space0= F38|VexW1|Disp8MemShift=3D3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex } +vgatherpf1dps, 0x66C6/2, AVX512PF, Modrm|EVex512|Masking|NoDefMask|Space0F= 38|VexW0|Disp8MemShift=3D2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex } +vgatherpf1qp, 0x66C7/2, AVX512PF, Modrm|EVex512|Masking|NoDefMask|Spac= e0F38||Disp8MemShift|VecSIB512|NoSuf, { |Unspecified|Base= Index } =20 -vscatterpf0dpd, 0x66C6/5, AVX512PF, Modrm|EVex=3D1|Masking=3D2|NoDefMask|S= pace0F38|VexW1|Disp8MemShift=3D3|VecSIB256|NoSuf, { Qword|Unspecified|BaseI= ndex } -vscatterpf0dps, 0x66C6/5, AVX512PF, Modrm|EVex512|Masking=3D2|NoDefMask|Sp= ace0F38|VexW0|Disp8MemShift=3D2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIn= dex } -vscatterpf0qp, 0x66C7/5, AVX512PF, Modrm|EVex512|Masking=3D2|NoDefMask= |Space0F38||Disp8MemShift|VecSIB512|NoSuf, { |Unspecified= |BaseIndex } -vscatterpf1dpd, 0x66C6/6, AVX512PF, Modrm|EVex=3D1|Masking=3D2|NoDefMask|S= pace0F38|VexW1|Disp8MemShift=3D3|VecSIB256|NoSuf, { Qword|Unspecified|BaseI= ndex } -vscatterpf1dps, 0x66C6/6, AVX512PF, Modrm|EVex=3D1|Masking=3D2|NoDefMask|S= pace0F38|VexW0|Disp8MemShift=3D2|VecSIB512|NoSuf, { Dword|Unspecified|BaseI= ndex } -vscatterpf1qp, 0x66C7/6, AVX512PF, Modrm|EVex512|Masking=3D2|NoDefMask= |Space0F38||Disp8MemShift|VecSIB512|NoSuf, { |Unspecified= |BaseIndex } +vscatterpf0dpd, 0x66C6/5, AVX512PF, Modrm|EVex=3D1|Masking|NoDefMask|Space= 0F38|VexW1|Disp8MemShift=3D3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex= } +vscatterpf0dps, 0x66C6/5, AVX512PF, Modrm|EVex512|Masking|NoDefMask|Space0= F38|VexW0|Disp8MemShift=3D2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex } +vscatterpf0qp, 0x66C7/5, AVX512PF, Modrm|EVex512|Masking|NoDefMask|Spa= ce0F38||Disp8MemShift|VecSIB512|NoSuf, { |Unspecified|Bas= eIndex } +vscatterpf1dpd, 0x66C6/6, AVX512PF, Modrm|EVex=3D1|Masking|NoDefMask|Space= 0F38|VexW1|Disp8MemShift=3D3|VecSIB256|NoSuf, { Qword|Unspecified|BaseIndex= } +vscatterpf1dps, 0x66C6/6, AVX512PF, Modrm|EVex=3D1|Masking|NoDefMask|Space= 0F38|VexW0|Disp8MemShift=3D2|VecSIB512|NoSuf, { Dword|Unspecified|BaseIndex= } +vscatterpf1qp, 0x66C7/6, AVX512PF, Modrm|EVex512|Masking|NoDefMask|Spa= ce0F38||Disp8MemShift|VecSIB512|NoSuf, { |Unspecified|Bas= eIndex } =20 // AVX512PF instructions end. =20 @@ -2490,107 +2489,107 @@ enclv, 0xf01c0, SE1, NoSuf, {} =20 // AVX512VL instructions. =20 -vgatherdpd, 0x6692, AVX512F|AVX512VL, Modrm|Masking=3D2|NoDefMask|Space0F3= 8|VexW1|Disp8MemShift=3D3|VecSIB128|NoSuf, { Qword|Unspecified|BaseIndex, R= egXMM|RegYMM } -vgatherdps, 0x6692, AVX512F|AVX512VL, Modrm|EVex=3D2|Masking=3D2|NoDefMask= |Space0F38|VexW0|Disp8MemShift=3D2|VecSIB128|NoSuf, { Dword|Unspecified|Bas= eIndex, RegXMM } -vgatherdps, 0x6692, AVX512F|AVX512VL, Modrm|EVex=3D3|Masking=3D2|NoDefMask= |Space0F38|VexW0|Disp8MemShift=3D2|VecSIB256|NoSuf, { Dword|Unspecified|Bas= eIndex, RegYMM } -vgatherqp, 0x6693, AVX512F|AVX512VL, Modrm|EVex128|Masking=3D2|NoDefMa= sk|Space0F38||Disp8MemShift|VecSIB128|NoSuf, { |Unspecifi= ed|BaseIndex, RegXMM } -vgatherqpd, 0x6693, AVX512F|AVX512VL, Modrm|EVex256|Masking=3D2|NoDefMask|= Space0F38|VexW1|Disp8MemShift=3D3|VecSIB256|NoSuf, { Qword|Unspecified|Base= Index, RegYMM } -vgatherqps, 0x6693, AVX512F|AVX512VL, Modrm|EVex=3D3|Masking=3D2|NoDefMask= |Space0F38|VexW0|Disp8MemShift=3D2|VecSIB256|NoSuf, { Dword|Unspecified|Bas= eIndex, RegXMM } -vpgatherdd, 0x6690, AVX512F|AVX512VL, Modrm|EVex=3D2|Masking=3D2|NoDefMask= |Space0F38|VexW0|Disp8MemShift=3D2|VecSIB128|NoSuf, { Dword|Unspecified|Bas= eIndex, RegXMM } -vpgatherdd, 0x6690, AVX512F|AVX512VL, Modrm|EVex=3D3|Masking=3D2|NoDefMask= |Space0F38|VexW0|Disp8MemShift=3D2|VecSIB256|NoSuf, { Dword|Unspecified|Bas= eIndex, RegYMM } -vpgatherdq, 0x6690, AVX512F|AVX512VL, Modrm|Masking=3D2|NoDefMask|Space0F3= 8|VexW1|Disp8MemShift=3D3|VecSIB128|NoSuf, { Qword|Unspecified|BaseIndex, R= egXMM|RegYMM } -vpgatherq, 0x6691, AVX512F|AVX512VL, Modrm|EVex128|Masking=3D2|NoDefMa= sk|Space0F38||Disp8MemShift|VecSIB128|NoSuf, { |Unspecifi= ed|BaseIndex, RegXMM } -vpgatherqd, 0x6691, AVX512F|AVX512VL, Modrm|EVex=3D3|Masking=3D2|NoDefMask= |Space0F38|VexW0|Disp8MemShift=3D2|VecSIB256|NoSuf, { Dword|Unspecified|Bas= eIndex, RegXMM } -vpgatherqq, 0x6691, AVX512F|AVX512VL, Modrm|EVex256|Masking=3D2|NoDefMask|= Space0F38|VexW1|Disp8MemShift=3D3|VecSIB256|NoSuf, { Qword|Unspecified|Base= Index, RegYMM } - -vpscatterdd, 0x66A0, AVX512F|AVX512VL, Modrm|EVex=3D2|Masking=3D2|NoDefMas= k|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB128|NoSuf, { RegXMM, Dword|Unspec= ified|BaseIndex } -vpscatterdd, 0x66A0, AVX512F|AVX512VL, Modrm|EVex=3D3|Masking=3D2|NoDefMas= k|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB256|NoSuf, { RegYMM, Dword|Unspec= ified|BaseIndex } -vpscatterdq, 0x66A0, AVX512F|AVX512VL, Modrm|Masking=3D2|NoDefMask|Space0F= 38|VexW1|Disp8MemShift=3D3|VecSIB128|NoSuf, { RegXMM|RegYMM, Qword|Unspecif= ied|BaseIndex } -vpscatterq, 0x66A1, AVX512F|AVX512VL, Modrm|EVex128|Masking=3D2|NoDefM= ask|Space0F38||Disp8MemShift|VecSIB128|NoSuf, { RegXMM, |= Unspecified|BaseIndex } -vpscatterqd, 0x66A1, AVX512F|AVX512VL, Modrm|EVex=3D3|Masking=3D2|NoDefMas= k|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB256|NoSuf, { RegXMM, Dword|Unspec= ified|BaseIndex } -vpscatterqq, 0x66A1, AVX512F|AVX512VL, Modrm|EVex256|Masking=3D2|NoDefMask= |Space0F38|VexW1|Disp8MemShift=3D3|VecSIB256|NoSuf, { RegYMM, Qword|Unspeci= fied|BaseIndex } -vscatterdpd, 0x66A2, AVX512F|AVX512VL, Modrm|Masking=3D2|NoDefMask|Space0F= 38|VexW1|Disp8MemShift=3D3|VecSIB128|NoSuf, { RegXMM|RegYMM, Qword|Unspecif= ied|BaseIndex } -vscatterdps, 0x66A2, AVX512F|AVX512VL, Modrm|EVex=3D2|Masking=3D2|NoDefMas= k|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB128|NoSuf, { RegXMM, Dword|Unspec= ified|BaseIndex } -vscatterdps, 0x66A2, AVX512F|AVX512VL, Modrm|EVex=3D3|Masking=3D2|NoDefMas= k|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB256|NoSuf, { RegYMM, Dword|Unspec= ified|BaseIndex } -vscatterqp, 0x66A3, AVX512F|AVX512VL, Modrm|EVex128|Masking=3D2|NoDefM= ask|Space0F38||Disp8MemShift|VecSIB128|NoSuf, { RegXMM, |= Unspecified|BaseIndex } -vscatterqpd, 0x66A3, AVX512F|AVX512VL, Modrm|EVex256|Masking=3D2|NoDefMask= |Space0F38|VexW1|Disp8MemShift=3D3|VecSIB256|NoSuf, { RegYMM, Qword|Unspeci= fied|BaseIndex } -vscatterqps, 0x66A3, AVX512F|AVX512VL, Modrm|EVex=3D3|Masking=3D2|NoDefMas= k|Space0F38|VexW0|Disp8MemShift=3D2|VecSIB256|NoSuf, { RegXMM, Dword|Unspec= ified|BaseIndex } - -vcvtdq2pd, 0xF3E6, AVX512F|AVX512VL, Modrm|EVex128|Masking=3D3|Space0F|Vex= W0|Broadcast|Disp8MemShift=3D3|NoSuf, { RegXMM|Dword|Qword|Unspecified|Base= Index, RegXMM } -vcvtdq2pd, 0xF3E6, AVX512F|AVX512VL, Modrm|EVex256|Masking=3D3|Space0F|Vex= W0|Broadcast|Disp8MemShift=3D4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex,= RegYMM } -vcvtudq2pd, 0xF37A, AVX512F|AVX512VL, Modrm|EVex128|Masking=3D3|Space0F|Ve= xW0|Broadcast|Disp8MemShift=3D3|NoSuf, { RegXMM|Dword|Qword|Unspecified|Bas= eIndex, RegXMM } -vcvtudq2pd, 0xF37A, AVX512F|AVX512VL, Modrm|EVex256|Masking=3D3|Space0F|Ve= xW0|Broadcast|Disp8MemShift=3D4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex= , RegYMM } - -vcvtph2ps, 0x6613, AVX512F|AVX512VL, Modrm|EVex=3D2|Masking=3D3|Space0F38|= VexW0|Disp8MemShift=3D3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM= } -vcvtph2ps, 0x6613, AVX512F|AVX512VL, Modrm|EVex=3D3|Masking=3D3|Space0F38|= VexW=3D1|Disp8MemShift=3D4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } - -vcvtps2pd, 0x5A, AVX512F|AVX512VL, Modrm|EVex128|Masking=3D3|Space0F|VexW0= |Broadcast|Disp8MemShift=3D3|NoSuf, { RegXMM|Dword|Qword|Unspecified|BaseIn= dex, RegXMM } -vcvtps2pd, 0x5A, AVX512F|AVX512VL, Modrm|EVex256|Masking=3D3|Space0F|VexW0= |Broadcast|Disp8MemShift=3D4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, R= egYMM } - -vcvtps2ph, 0x661D, AVX512F|AVX512VL, Modrm|EVex128|MaskingMorZ|Space0F3A|V= exW0|Disp8MemShift=3D3|NoSuf, { Imm8, RegXMM, RegXMM|Qword|Unspecified|Base= Index } -vcvtps2ph, 0x661D, AVX512F|AVX512VL, Modrm|EVex256|MaskingMorZ|Space0F3A|V= exW0|Disp8MemShift=3D4|NoSuf, { Imm8, RegYMM, RegXMM|Unspecified|BaseIndex } - -vmovddup, 0xF212, AVX512F|AVX512VL, Modrm|EVex=3D2|Masking=3D3|Space0F|Vex= W1|Disp8MemShift=3D3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } - -vpmovdb, 0xF331, AVX512F|AVX512VL, Modrm|EVex=3D2|MaskingMorZ|Space0F38|Ve= xW0|Disp8MemShift=3D2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } -vpmovdb, 0xF331, AVX512F|AVX512VL, Modrm|EVex=3D3|MaskingMorZ|Space0F38|Ve= xW0|Disp8MemShift=3D3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovsdb, 0xF321, AVX512F|AVX512VL, Modrm|EVex=3D2|MaskingMorZ|Space0F38|V= exW0|Disp8MemShift=3D2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } -vpmovsdb, 0xF321, AVX512F|AVX512VL, Modrm|EVex=3D3|MaskingMorZ|Space0F38|V= exW0|Disp8MemShift=3D3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovusdb, 0xF311, AVX512F|AVX512VL, Modrm|EVex=3D2|MaskingMorZ|Space0F38|= VexW0|Disp8MemShift=3D2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex= } -vpmovusdb, 0xF311, AVX512F|AVX512VL, Modrm|EVex=3D3|MaskingMorZ|Space0F38|= VexW0|Disp8MemShift=3D3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex= } - -vpmovdw, 0xF333, AVX512F|AVX512VL, Modrm|EVex=3D2|MaskingMorZ|Space0F38|Ve= xW0|Disp8MemShift=3D3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovdw, 0xF333, AVX512F|AVX512VL, Modrm|EVex=3D3|MaskingMorZ|Space0F38|Ve= xW=3D1|Disp8MemShift=3D4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } -vpmovsdw, 0xF323, AVX512F|AVX512VL, Modrm|EVex=3D2|MaskingMorZ|Space0F38|V= exW0|Disp8MemShift=3D3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovsdw, 0xF323, AVX512F|AVX512VL, Modrm|EVex=3D3|MaskingMorZ|Space0F38|V= exW=3D1|Disp8MemShift=3D4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } -vpmovusdw, 0xF313, AVX512F|AVX512VL, Modrm|EVex=3D2|MaskingMorZ|Space0F38|= VexW0|Disp8MemShift=3D3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex= } -vpmovusdw, 0xF313, AVX512F|AVX512VL, Modrm|EVex=3D3|MaskingMorZ|Space0F38|= VexW=3D1|Disp8MemShift=3D4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } - -vpmovqb, 0xF332, AVX512F|AVX512VL, Modrm|EVex=3D2|MaskingMorZ|Space0F38|Ve= xW0|Disp8MemShift=3D1|NoSuf, { RegXMM, RegXMM|Word|Unspecified|BaseIndex } -vpmovqb, 0xF332, AVX512F|AVX512VL, Modrm|EVex=3D3|MaskingMorZ|Space0F38|Ve= xW0|Disp8MemShift=3D2|NoSuf, { RegYMM, RegXMM|Dword|Unspecified|BaseIndex } -vpmovsqb, 0xF322, AVX512F|AVX512VL, Modrm|EVex=3D2|MaskingMorZ|Space0F38|V= exW0|Disp8MemShift=3D1|NoSuf, { RegXMM, RegXMM|Word|Unspecified|BaseIndex } -vpmovsqb, 0xF322, AVX512F|AVX512VL, Modrm|EVex=3D3|MaskingMorZ|Space0F38|V= exW0|Disp8MemShift=3D2|NoSuf, { RegYMM, RegXMM|Dword|Unspecified|BaseIndex } -vpmovusqb, 0xF312, AVX512F|AVX512VL, Modrm|EVex=3D2|MaskingMorZ|Space0F38|= VexW0|Disp8MemShift=3D1|NoSuf, { RegXMM, RegXMM|Word|Unspecified|BaseIndex } -vpmovusqb, 0xF312, AVX512F|AVX512VL, Modrm|EVex=3D3|MaskingMorZ|Space0F38|= VexW0|Disp8MemShift=3D2|NoSuf, { RegYMM, RegXMM|Dword|Unspecified|BaseIndex= } - -vpmovqd, 0xF335, AVX512F|AVX512VL, Modrm|EVex=3D2|MaskingMorZ|Space0F38|Ve= xW0|Disp8MemShift=3D3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovqd, 0xF335, AVX512F|AVX512VL, Modrm|EVex=3D3|MaskingMorZ|Space0F38|Ve= xW=3D1|Disp8MemShift=3D4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } -vpmovsqd, 0xF325, AVX512F|AVX512VL, Modrm|EVex=3D2|MaskingMorZ|Space0F38|V= exW0|Disp8MemShift=3D3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovsqd, 0xF325, AVX512F|AVX512VL, Modrm|EVex=3D3|MaskingMorZ|Space0F38|V= exW=3D1|Disp8MemShift=3D4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } -vpmovusqd, 0xF315, AVX512F|AVX512VL, Modrm|EVex=3D2|MaskingMorZ|Space0F38|= VexW0|Disp8MemShift=3D3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex= } -vpmovusqd, 0xF315, AVX512F|AVX512VL, Modrm|EVex=3D3|MaskingMorZ|Space0F38|= VexW=3D1|Disp8MemShift=3D4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } - -vpmovqw, 0xF334, AVX512F|AVX512VL, Modrm|EVex=3D2|MaskingMorZ|Space0F38|Ve= xW0|Disp8MemShift=3D2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } -vpmovqw, 0xF334, AVX512F|AVX512VL, Modrm|EVex=3D3|MaskingMorZ|Space0F38|Ve= xW0|Disp8MemShift=3D3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovsqw, 0xF324, AVX512F|AVX512VL, Modrm|EVex=3D2|MaskingMorZ|Space0F38|V= exW0|Disp8MemShift=3D2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } -vpmovsqw, 0xF324, AVX512F|AVX512VL, Modrm|EVex=3D3|MaskingMorZ|Space0F38|V= exW0|Disp8MemShift=3D3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovusqw, 0xF314, AVX512F|AVX512VL, Modrm|EVex=3D2|MaskingMorZ|Space0F38|= VexW0|Disp8MemShift=3D2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex= } -vpmovusqw, 0xF314, AVX512F|AVX512VL, Modrm|EVex=3D3|MaskingMorZ|Space0F38|= VexW0|Disp8MemShift=3D3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex= } - -vpmovsxbd, 0x6621, AVX512F|AVX512VL, Modrm|EVex=3D2|Masking=3D3|Space0F38|= VexWIG|Disp8MemShift=3D2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXM= M } -vpmovsxbd, 0x6621, AVX512F|AVX512VL, Modrm|EVex=3D3|Masking=3D3|Space0F38|= VexWIG|Disp8MemShift=3D3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYM= M } -vpmovzxbd, 0x6631, AVX512F|AVX512VL, Modrm|EVex=3D2|Masking=3D3|Space0F38|= VexWIG|Disp8MemShift=3D2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXM= M } -vpmovzxbd, 0x6631, AVX512F|AVX512VL, Modrm|EVex=3D3|Masking=3D3|Space0F38|= VexWIG|Disp8MemShift=3D3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYM= M } - -vpmovsxbq, 0x6622, AVX512F|AVX512VL, Modrm|EVex=3D2|Masking=3D3|Space0F38|= VexWIG|Disp8MemShift=3D1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM= } -vpmovsxbq, 0x6622, AVX512F|AVX512VL, Modrm|EVex=3D3|Masking=3D3|Space0F38|= VexWIG|Disp8MemShift=3D2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYM= M } -vpmovzxbq, 0x6632, AVX512F|AVX512VL, Modrm|EVex=3D2|Masking=3D3|Space0F38|= VexWIG|Disp8MemShift=3D1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM= } -vpmovzxbq, 0x6632, AVX512F|AVX512VL, Modrm|EVex=3D3|Masking=3D3|Space0F38|= VexWIG|Disp8MemShift=3D2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYM= M } - -vpmovsxdq, 0x6625, AVX512F|AVX512VL, Modrm|EVex=3D2|Masking=3D3|Space0F38|= VexW0|Disp8MemShift=3D3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM= } -vpmovsxdq, 0x6625, AVX512F|AVX512VL, Modrm|EVex=3D3|Masking=3D3|Space0F38|= VexW=3D1|Disp8MemShift=3D4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } -vpmovzxdq, 0x6635, AVX512F|AVX512VL, Modrm|EVex=3D2|Masking=3D3|Space0F38|= VexW0|Disp8M[...] [diff truncated at 100000 bytes]