From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2119) id 59E773858C60; Sat, 1 Jul 2023 13:33:06 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 59E773858C60 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Jeff Law To: bfd-cvs@sourceware.org Subject: [binutils-gdb] RISC-V: Add support for the Zvkn ISA extension X-Act-Checkin: binutils-gdb X-Git-Author: =?utf-8?q?Christoph_M=C3=BCllner?= X-Git-Refname: refs/heads/master X-Git-Oldrev: 259a2647dc158e196e4e03719cdc6bb0ff657d1d X-Git-Newrev: c62d5acf8478b0cb3c93130cb15fa76aecd93a02 Message-Id: <20230701133306.59E773858C60@sourceware.org> Date: Sat, 1 Jul 2023 13:33:06 +0000 (GMT) X-BeenThere: binutils-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 01 Jul 2023 13:33:06 -0000 https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3Dc62d5acf8478= b0cb3c93130cb15fa76aecd93a02 commit c62d5acf8478b0cb3c93130cb15fa76aecd93a02 Author: Christoph M=C3=BCllner Date: Fri Jun 30 22:44:12 2023 +0200 RISC-V: Add support for the Zvkn ISA extension =20 Zvkn is part of the vector crypto extensions. =20 Zvkn is shorthand for the following set of extensions: - Zvkned - Zvknhb - Zvbb - Zvkt =20 bfd/ChangeLog: =20 * elfxx-riscv.c: Define Zvkn extension. =20 gas/ChangeLog: =20 * testsuite/gas/riscv/zvkn.d: New test. * testsuite/gas/riscv/zvkn.s: New test. =20 Signed-off-by: Nathan Huckleberry Signed-off-by: Christoph M=C3=BCllner Diff: --- bfd/elfxx-riscv.c | 5 +++++ gas/testsuite/gas/riscv/zvkn.d | 45 ++++++++++++++++++++++++++++++++++++++= ++++ gas/testsuite/gas/riscv/zvkn.s | 36 +++++++++++++++++++++++++++++++++ 3 files changed, 86 insertions(+) diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 10cdcc2eb84..426139d4960 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1156,6 +1156,10 @@ static struct riscv_implicit_subset riscv_implicit_s= ubsets[] =3D {"zks", "zbkx", check_implicit_always}, {"zks", "zksed", check_implicit_always}, {"zks", "zksh", check_implicit_always}, + {"zvkn", "zvkned", check_implicit_always}, + {"zvkn", "zvknha", check_implicit_always}, + {"zvkn", "zvknhb", check_implicit_always}, + {"zvkn", "zvbb", check_implicit_always}, {"smaia", "ssaia", check_implicit_always}, {"smstateen", "ssstateen", check_implicit_always}, {"smepmp", "zicsr", check_implicit_always}, @@ -1265,6 +1269,7 @@ static struct riscv_supported_ext riscv_supported_std= _z_ext[] =3D {"zvbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvkg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvkn", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvkned", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvknha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvknhb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, diff --git a/gas/testsuite/gas/riscv/zvkn.d b/gas/testsuite/gas/riscv/zvkn.d new file mode 100644 index 00000000000..abb92b9f001 --- /dev/null +++ b/gas/testsuite/gas/riscv/zvkn.d @@ -0,0 +1,45 @@ +#as: -march=3Drv64gc_zvkn +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+a280a277[ ]+vaesdf.vv[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+ba862277[ ]+vsha2ch.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+06860257[ ]+vandn.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+04860257[ ]+vandn.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+0685c257[ ]+vandn.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+0485c257[ ]+vandn.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+4a852257[ ]+vbrev.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+48852257[ ]+vbrev.v[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+4a842257[ ]+vbrev8.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+48842257[ ]+vbrev8.v[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+4a84a257[ ]+vrev8.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+4884a257[ ]+vrev8.v[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+4a84a257[ ]+vrev8.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+4884a257[ ]+vrev8.v[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+4a862257[ ]+vclz.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+48862257[ ]+vclz.v[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+4a86a257[ ]+vctz.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+4886a257[ ]+vctz.v[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+4a872257[ ]+vcpop.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+48872257[ ]+vcpop.v[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+56860257[ ]+vrol.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+54860257[ ]+vrol.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+5685c257[ ]+vrol.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+5485c257[ ]+vrol.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+52860257[ ]+vror.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+50860257[ ]+vror.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+5285c257[ ]+vror.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+5085c257[ ]+vror.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+52803257[ ]+vror.vi[ ]+v4,v8,0 +[ ]+[0-9a-f]+:[ ]+548fb257[ ]+vror.vi[ ]+v4,v8,63,v0.t +[ ]+[0-9a-f]+:[ ]+d6860257[ ]+vwsll.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+d4860257[ ]+vwsll.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+d685c257[ ]+vwsll.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+d485c257[ ]+vwsll.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+d6803257[ ]+vwsll.vi[ ]+v4,v8,0 +[ ]+[0-9a-f]+:[ ]+d48fb257[ ]+vwsll.vi[ ]+v4,v8,31,v0.t + diff --git a/gas/testsuite/gas/riscv/zvkn.s b/gas/testsuite/gas/riscv/zvkn.s new file mode 100644 index 00000000000..44e8f1769ce --- /dev/null +++ b/gas/testsuite/gas/riscv/zvkn.s @@ -0,0 +1,36 @@ + vaesdf.vv v4, v8 + vsha2ch.vv v4, v8, v12 + vandn.vv v4, v8, v12 + vandn.vv v4, v8, v12, v0.t + vandn.vx v4, v8, a1 + vandn.vx v4, v8, a1, v0.t + vbrev.v v4, v8 + vbrev.v v4, v8, v0.t + vbrev8.v v4, v8 + vbrev8.v v4, v8, v0.t + vrev8.v v4, v8 + vrev8.v v4, v8, v0.t + vrev8.v v4, v8 + vrev8.v v4, v8, v0.t + vclz.v v4, v8 + vclz.v v4, v8, v0.t + vctz.v v4, v8 + vctz.v v4, v8, v0.t + vcpop.v v4, v8 + vcpop.v v4, v8, v0.t + vrol.vv v4, v8, v12 + vrol.vv v4, v8, v12, v0.t + vrol.vx v4, v8, a1 + vrol.vx v4, v8, a1, v0.t + vror.vv v4, v8, v12 + vror.vv v4, v8, v12, v0.t + vror.vx v4, v8, a1 + vror.vx v4, v8, a1, v0.t + vror.vi v4, v8, 0 + vror.vi v4, v8, 63, v0.t + vwsll.vv v4, v8, v12 + vwsll.vv v4, v8, v12, v0.t + vwsll.vx v4, v8, a1 + vwsll.vx v4, v8, a1, v0.t + vwsll.vi v4, v8, 0 + vwsll.vi v4, v8, 31, v0.t