From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2119) id BA1AA3858D38; Sat, 1 Jul 2023 13:33:26 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org BA1AA3858D38 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Jeff Law To: bfd-cvs@sourceware.org Subject: [binutils-gdb] RISC-V: Add support for the Zvksg ISA extension X-Act-Checkin: binutils-gdb X-Git-Author: Nathan Huckleberry X-Git-Refname: refs/heads/master X-Git-Oldrev: 33057f810e91dd1a76279e6160bcf3ae110a1abe X-Git-Newrev: c6cffecd3cc181bcd1960960eefc848fb0424757 Message-Id: <20230701133326.BA1AA3858D38@sourceware.org> Date: Sat, 1 Jul 2023 13:33:26 +0000 (GMT) X-BeenThere: binutils-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 01 Jul 2023 13:33:26 -0000 https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3Dc6cffecd3cc1= 81bcd1960960eefc848fb0424757 commit c6cffecd3cc181bcd1960960eefc848fb0424757 Author: Nathan Huckleberry Date: Fri Jun 30 22:44:32 2023 +0200 RISC-V: Add support for the Zvksg ISA extension =20 Zvksg is part of the vector crypto extensions. =20 Zvksg is shorthand for the following set of extensions: - Zvks - Zvkg =20 bfd/ChangeLog: =20 * elfxx-riscv.c: Define Zvksg extension. =20 gas/ChangeLog: =20 * testsuite/gas/riscv/zvksg.d: New test. * testsuite/gas/riscv/zvksg.s: New test. =20 Signed-off-by: Nathan Huckleberry Signed-off-by: Christoph M=C3=BCllner Diff: --- bfd/elfxx-riscv.c | 3 +++ gas/testsuite/gas/riscv/zvksg.d | 12 ++++++++++++ gas/testsuite/gas/riscv/zvksg.s | 4 ++++ 3 files changed, 19 insertions(+) diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 5d51ef6b262..e2a7d8cebcd 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1165,6 +1165,8 @@ static struct riscv_implicit_subset riscv_implicit_su= bsets[] =3D {"zvks", "zvksed", check_implicit_always}, {"zvks", "zvksh", check_implicit_always}, {"zvks", "zvbb", check_implicit_always}, + {"zvksg", "zvks", check_implicit_always}, + {"zvksg", "zvkg", check_implicit_always}, {"smaia", "ssaia", check_implicit_always}, {"smstateen", "ssstateen", check_implicit_always}, {"smepmp", "zicsr", check_implicit_always}, @@ -1282,6 +1284,7 @@ static struct riscv_supported_ext riscv_supported_std= _z_ext[] =3D {"zvksed", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvksh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvks", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvksg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, diff --git a/gas/testsuite/gas/riscv/zvksg.d b/gas/testsuite/gas/riscv/zvks= g.d new file mode 100644 index 00000000000..24a7126e9a7 --- /dev/null +++ b/gas/testsuite/gas/riscv/zvksg.d @@ -0,0 +1,12 @@ +#as: -march=3Drv64gc_zvksg +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+86802277[ ]+vsm4k.vi[ ]+v4,v8,0 +[ ]+[0-9a-f]+:[ ]+ae802277[ ]+vsm3c.vi[ ]+v4,v8,0 +[ ]+[0-9a-f]+:[ ]+b2862277[ ]+vghsh.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+a2c8a277[ ]+vgmul.vv[ ]+v4,v12 diff --git a/gas/testsuite/gas/riscv/zvksg.s b/gas/testsuite/gas/riscv/zvks= g.s new file mode 100644 index 00000000000..8da053e1d6f --- /dev/null +++ b/gas/testsuite/gas/riscv/zvksg.s @@ -0,0 +1,4 @@ + vsm4k.vi v4, v8, 0 + vsm3c.vi v4, v8, 0 + vghsh.vv v4, v8, v12 + vgmul.vv v4, v12