From: Jeff Law <law@sourceware.org>
To: bfd-cvs@sourceware.org
Subject: [binutils-gdb] RISC-V: Add support for the Zvknc ISA extension
Date: Sat, 1 Jul 2023 13:33:31 +0000 (GMT) [thread overview]
Message-ID: <20230701133331.CC593385840D@sourceware.org> (raw)
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=937cc1c690c959240075eb45720310533d3a1c0d
commit 937cc1c690c959240075eb45720310533d3a1c0d
Author: Nathan Huckleberry <nhuck@google.com>
Date: Fri Jun 30 22:44:37 2023 +0200
RISC-V: Add support for the Zvknc ISA extension
Zvknc is part of the vector crypto extensions.
Zvknc is shorthand for the following set of extensxions:
- Zvkn
- Zvbc
bfd/ChangeLog:
* elfxx-riscv.c: Define Zvknc extension.
gas/ChangeLog:
* testsuite/gas/riscv/zvknc.d: New test.
* testsuite/gas/riscv/zvknc.s: New test.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diff:
---
bfd/elfxx-riscv.c | 3 +++
gas/testsuite/gas/riscv/zvknc.d | 18 ++++++++++++++++++
gas/testsuite/gas/riscv/zvknc.s | 10 ++++++++++
3 files changed, 31 insertions(+)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index e2a7d8cebcd..95b3ab3c2c7 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1162,6 +1162,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"zvkn", "zvbb", check_implicit_always},
{"zvkng", "zvkn", check_implicit_always},
{"zvkng", "zvkg", check_implicit_always},
+ {"zvknc", "zvkn", check_implicit_always},
+ {"zvknc", "zvbc", check_implicit_always},
{"zvks", "zvksed", check_implicit_always},
{"zvks", "zvksh", check_implicit_always},
{"zvks", "zvbb", check_implicit_always},
@@ -1278,6 +1280,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zvkg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvkn", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvkng", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvknc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvkned", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvknha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvknhb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
diff --git a/gas/testsuite/gas/riscv/zvknc.d b/gas/testsuite/gas/riscv/zvknc.d
new file mode 100644
index 00000000000..f68103b129e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvknc.d
@@ -0,0 +1,18 @@
+#as: -march=rv64gc_zvknc
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+a280a277[ ]+vaesdf.vv[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+ba862277[ ]+vsha2ch.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+32862257[ +vclmul.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+30862257[ ]+vclmul.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+3285e257[ ]+vclmul.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+3085e257[ ]+vclmul.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+36862257[ ]+vclmulh.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+34862257[ ]+vclmulh.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+3685e257[ ]+vclmulh.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+3485e257[ ]+vclmulh.vx[ ]+v4,v8,a1,v0.t
diff --git a/gas/testsuite/gas/riscv/zvknc.s b/gas/testsuite/gas/riscv/zvknc.s
new file mode 100644
index 00000000000..60b10d8b8b5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvknc.s
@@ -0,0 +1,10 @@
+ vaesdf.vv v4, v8
+ vsha2ch.vv v4, v8, v12
+ vclmul.vv v4, v8, v12
+ vclmul.vv v4, v8, v12, v0.t
+ vclmul.vx v4, v8, a1
+ vclmul.vx v4, v8, a1, v0.t
+ vclmulh.vv v4, v8, v12
+ vclmulh.vv v4, v8, v12, v0.t
+ vclmulh.vx v4, v8, a1
+ vclmulh.vx v4, v8, a1, v0.t
reply other threads:[~2023-07-01 13:33 UTC|newest]
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