From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1861) id 64DC3385E02C; Fri, 21 Jul 2023 18:00:51 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 64DC3385E02C Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Jose E. Marchesi To: bfd-cvs@sourceware.org Subject: [binutils-gdb] bpf: opcodes, gas: support for signed register move V4 instructions X-Act-Checkin: binutils-gdb X-Git-Author: Jose E. Marchesi X-Git-Refname: refs/heads/master X-Git-Oldrev: 01deb24db99ea7909a30679ddb3cd4cba7b14fc7 X-Git-Newrev: 2f3dbc5fb5e781fc17d8f68f9c960a993f06d801 Message-Id: <20230721180051.64DC3385E02C@sourceware.org> Date: Fri, 21 Jul 2023 18:00:51 +0000 (GMT) X-BeenThere: binutils-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 21 Jul 2023 18:00:51 -0000 https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D2f3dbc5fb5e7= 81fc17d8f68f9c960a993f06d801 commit 2f3dbc5fb5e781fc17d8f68f9c960a993f06d801 Author: Jose E. Marchesi Date: Fri Jul 21 17:22:58 2023 +0200 bpf: opcodes, gas: support for signed register move V4 instructions =20 This commit adds the signed register move (movs) instructions introduced in the BPF ISA version 4, including opcodes and assembler tests. =20 Tested in bpf-unknown-none. =20 include/ChangeLog: =20 2023-07-21 Jose E. Marchesi =20 * opcode/bpf.h (BPF_OFFSET16_MOVS8): Define. (BPF_OFFSET16_MOVS16): Likewise. (BPF_OFFSET16_MOVS32): Likewise. (enum bpf_insn_id): Add entries for MOVS{8,16,32}R and MOVS32{8,16,32}R. =20 opcodes/ChangeLog: =20 2023-07-21 Jose E. Marchesi =20 * bpf-opc.c (bpf_opcodes): Add entries for MOVS{8,16,32}R and MOVS32{8,16,32}R instructions. and MOVS32I instructions. =20 gas/ChangeLog: =20 2023-07-21 Jose E. Marchesi =20 * testsuite/gas/bpf/alu.s: Test movs instructions. * testsuite/gas/bpf/alu-pseudoc.s: Likewise. * testsuite/gas/bpf/alu32.s: Likewise for movs32 instruction. * testsuite/gas/bpf/alu32-pseudoc.s: Likewise. * testsuite/gas/bpf/alu.d: Add expected results. * testsuite/gas/bpf/alu32.d: Likewise. * testsuite/gas/bpf/alu-be.d: Likewise. * testsuite/gas/bpf/alu32-be.d: Likewise. * testsuite/gas/bpf/alu-pseudoc.d: Likewise. * testsuite/gas/bpf/alu32-pseudoc.d: Likewise. * testsuite/gas/bpf/alu-be-pseudoc.d: Likewise. * testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise. Diff: --- gas/ChangeLog | 15 +++++++++++++++ gas/doc/c-bpf.texi | 24 ++++++++++++++++++++++++ gas/testsuite/gas/bpf/alu-be-pseudoc.d | 3 +++ gas/testsuite/gas/bpf/alu-be.d | 3 +++ gas/testsuite/gas/bpf/alu-pseudoc.d | 3 +++ gas/testsuite/gas/bpf/alu-pseudoc.s | 3 +++ gas/testsuite/gas/bpf/alu.d | 3 +++ gas/testsuite/gas/bpf/alu.s | 3 +++ gas/testsuite/gas/bpf/alu32-be-pseudoc.d | 3 +++ gas/testsuite/gas/bpf/alu32-be.d | 3 +++ gas/testsuite/gas/bpf/alu32-pseudoc.d | 3 +++ gas/testsuite/gas/bpf/alu32-pseudoc.s | 3 +++ gas/testsuite/gas/bpf/alu32.d | 3 +++ gas/testsuite/gas/bpf/alu32.s | 3 +++ include/ChangeLog | 8 ++++++++ include/opcode/bpf.h | 5 +++++ opcodes/ChangeLog | 5 +++++ opcodes/bpf-opc.c | 12 ++++++++++++ 18 files changed, 105 insertions(+) diff --git a/gas/ChangeLog b/gas/ChangeLog index 3d22461266a..66c95a1b9a5 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,18 @@ +2023-07-21 Jose E. Marchesi + + * testsuite/gas/bpf/alu.s: Test movs instructions. + * testsuite/gas/bpf/alu-pseudoc.s: Likewise. + * testsuite/gas/bpf/alu32.s: Likewise for movs32 instruction. + * testsuite/gas/bpf/alu32-pseudoc.s: Likewise. + * testsuite/gas/bpf/alu.d: Add expected results. + * testsuite/gas/bpf/alu32.d: Likewise. + * testsuite/gas/bpf/alu-be.d: Likewise. + * testsuite/gas/bpf/alu32-be.d: Likewise. + * testsuite/gas/bpf/alu-pseudoc.d: Likewise. + * testsuite/gas/bpf/alu32-pseudoc.d: Likewise. + * testsuite/gas/bpf/alu-be-pseudoc.d: Likewise. + * testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise. + 2023-07-03 Nick Clifton =20 * configure: Regenerate. diff --git a/gas/doc/c-bpf.texi b/gas/doc/c-bpf.texi index 4742f89ea17..a3814e95c3a 100644 --- a/gas/doc/c-bpf.texi +++ b/gas/doc/c-bpf.texi @@ -259,6 +259,18 @@ ambiguity in the pseudoc syntax. @itemx rd =3D imm32 Move the 64-bit value of @code{rs} in @code{rd}, or load @code{imm32} in @code{rd}. + +@item movs rd, rs, 8 +@itemx rd s=3D (i8) rs +Move the sign-extended 8-bit value in @code{rs} to @code{rd}. + +@item movs rd, rs, 16 +@itemx rd s=3D (i16) rs +Move the sign-extended 16-bit value in @code{rs} to @code{rd}. + +@item movs rd, rs, 32 +@itemx rd s=3D (i32) rs +Move the sign-extended 32-bit value in @code{rs} to @code{rd}. @end table =20 @subsection 32-bit arithmetic instructions @@ -354,6 +366,18 @@ ambiguity in the pseudoc syntax. @itemx rd =3D imm32 Move the 32-bit value of @code{rs} in @code{rd}, or load @code{imm32} in @code{rd}. + +@item mov32s rd, rs, 8 +@itemx rd s=3D (i8) rs +Move the sign-extended 8-bit value in @code{rs} to @code{rd}. + +@item mov32s rd, rs, 16 +@itemx rd s=3D (i16) rs +Move the sign-extended 16-bit value in @code{rs} to @code{rd}. + +@item mov32s rd, rs, 32 +@itemx rd s=3D (i32) rs +Move the sign-extended 32-bit value in @code{rs} to @code{rd}. @end table =20 @subsection Endianness conversion instructions diff --git a/gas/testsuite/gas/bpf/alu-be-pseudoc.d b/gas/testsuite/gas/bpf= /alu-be-pseudoc.d index 8d8c29e91c7..486d7923478 100644 --- a/gas/testsuite/gas/bpf/alu-be-pseudoc.d +++ b/gas/testsuite/gas/bpf/alu-be-pseudoc.d @@ -63,3 +63,6 @@ Disassembly of section .text: 1a0: dc 60 00 00 00 00 00 10 r6=3Dbe16 r6 1a8: dc 50 00 00 00 00 00 20 r5=3Dbe32 r5 1b0: dc 40 00 00 00 00 00 40 r4=3Dbe64 r4 + 1b8: bf 12 00 08 00 00 00 00 r1 s=3D \(i8\) r2 + 1c0: bf 12 00 10 00 00 00 00 r1 s=3D \(i16\) r2 + 1c8: bf 12 00 20 00 00 00 00 r1 s=3D \(i32\) r2 diff --git a/gas/testsuite/gas/bpf/alu-be.d b/gas/testsuite/gas/bpf/alu-be.d index 170db4b853d..a082c46af1c 100644 --- a/gas/testsuite/gas/bpf/alu-be.d +++ b/gas/testsuite/gas/bpf/alu-be.d @@ -63,3 +63,6 @@ Disassembly of section .text: 1a0: dc 60 00 00 00 00 00 10 endbe %r6,16 1a8: dc 50 00 00 00 00 00 20 endbe %r5,32 1b0: dc 40 00 00 00 00 00 40 endbe %r4,64 + 1b8: bf 12 00 08 00 00 00 00 movs %r1,%r2,8 + 1c0: bf 12 00 10 00 00 00 00 movs %r1,%r2,16 + 1c8: bf 12 00 20 00 00 00 00 movs %r1,%r2,32 diff --git a/gas/testsuite/gas/bpf/alu-pseudoc.d b/gas/testsuite/gas/bpf/al= u-pseudoc.d index 5d69e68a4f0..cf1ef2ac029 100644 --- a/gas/testsuite/gas/bpf/alu-pseudoc.d +++ b/gas/testsuite/gas/bpf/alu-pseudoc.d @@ -63,3 +63,6 @@ Disassembly of section .text: 1a0: dc 06 00 00 10 00 00 00 r6=3Dbe16 r6 1a8: dc 05 00 00 20 00 00 00 r5=3Dbe32 r5 1b0: dc 04 00 00 40 00 00 00 r4=3Dbe64 r4 + 1b8: bf 21 08 00 00 00 00 00 r1 s=3D \(i8\) r2 + 1c0: bf 21 10 00 00 00 00 00 r1 s=3D \(i16\) r2 + 1c8: bf 21 20 00 00 00 00 00 r1 s=3D \(i32\) r2 diff --git a/gas/testsuite/gas/bpf/alu-pseudoc.s b/gas/testsuite/gas/bpf/al= u-pseudoc.s index a271bef977d..513c8b8f4f9 100644 --- a/gas/testsuite/gas/bpf/alu-pseudoc.s +++ b/gas/testsuite/gas/bpf/alu-pseudoc.s @@ -55,3 +55,6 @@ r6 =3D be16 r6 r5 =3D be32 r5 r4 =3D be64 r4 + r1 s=3D (i8) r2 + r1 s=3D (i16) r2 + r1 s=3D (i32) r2 diff --git a/gas/testsuite/gas/bpf/alu.d b/gas/testsuite/gas/bpf/alu.d index 476891b9afd..409018ddf55 100644 --- a/gas/testsuite/gas/bpf/alu.d +++ b/gas/testsuite/gas/bpf/alu.d @@ -63,3 +63,6 @@ Disassembly of section .text: 1a0: dc 06 00 00 10 00 00 00 endbe %r6,16 1a8: dc 05 00 00 20 00 00 00 endbe %r5,32 1b0: dc 04 00 00 40 00 00 00 endbe %r4,64 + 1b8: bf 21 08 00 00 00 00 00 movs %r1,%r2,8 + 1c0: bf 21 10 00 00 00 00 00 movs %r1,%r2,16 + 1c8: bf 21 20 00 00 00 00 00 movs %r1,%r2,32 diff --git a/gas/testsuite/gas/bpf/alu.s b/gas/testsuite/gas/bpf/alu.s index bb3f9265200..6f8c30fff68 100644 --- a/gas/testsuite/gas/bpf/alu.s +++ b/gas/testsuite/gas/bpf/alu.s @@ -55,3 +55,6 @@ endbe %r6,16 endbe %r5,32 endbe %r4,64 + movs %r1,%r2,8 + movs %r1,%r2,16 + movs %r1,%r2,32 diff --git a/gas/testsuite/gas/bpf/alu32-be-pseudoc.d b/gas/testsuite/gas/b= pf/alu32-be-pseudoc.d index 6daad3b6926..79a638fb37e 100644 --- a/gas/testsuite/gas/bpf/alu32-be-pseudoc.d +++ b/gas/testsuite/gas/bpf/alu32-be-pseudoc.d @@ -57,3 +57,6 @@ Disassembly of section .text: 170: c4 40 00 00 7e ad be ef w4 s>>=3D0x7eadbeef 178: cc 56 00 00 00 00 00 00 w5 s>>=3Dw6 180: 8c 23 00 00 00 00 00 00 w2=3D-w3 + 188: bc 12 00 08 00 00 00 00 w1 s=3D \(i8\) w2 + 190: bc 12 00 10 00 00 00 00 w1 s=3D \(i16\) w2 + 198: bc 12 00 20 00 00 00 00 w1 s=3D \(i32\) w2 diff --git a/gas/testsuite/gas/bpf/alu32-be.d b/gas/testsuite/gas/bpf/alu32= -be.d index 6de8f0660d8..0549bf23131 100644 --- a/gas/testsuite/gas/bpf/alu32-be.d +++ b/gas/testsuite/gas/bpf/alu32-be.d @@ -57,3 +57,6 @@ Disassembly of section .text: 170: c4 40 00 00 7e ad be ef arsh32 %r4,0x7eadbeef 178: cc 56 00 00 00 00 00 00 arsh32 %r5,%r6 180: 8c 23 00 00 00 00 00 00 neg32 %r2,%r3 + 188: bc 12 00 08 00 00 00 00 movs32 %r1,%r2,8 + 190: bc 12 00 10 00 00 00 00 movs32 %r1,%r2,16 + 198: bc 12 00 20 00 00 00 00 movs32 %r1,%r2,32 diff --git a/gas/testsuite/gas/bpf/alu32-pseudoc.d b/gas/testsuite/gas/bpf/= alu32-pseudoc.d index f339c808d26..175dd1f1cd6 100644 --- a/gas/testsuite/gas/bpf/alu32-pseudoc.d +++ b/gas/testsuite/gas/bpf/alu32-pseudoc.d @@ -57,3 +57,6 @@ Disassembly of section .text: 170: c4 04 00 00 ef be ad 7e w4 s>>=3D0x7eadbeef 178: cc 65 00 00 00 00 00 00 w5 s>>=3Dw6 180: 8c 32 00 00 00 00 00 00 w2=3D-w3 + 188: bc 21 08 00 00 00 00 00 w1 s=3D \(i8\) w2 + 190: bc 21 10 00 00 00 00 00 w1 s=3D \(i16\) w2 + 198: bc 21 20 00 00 00 00 00 w1 s=3D \(i32\) w2 diff --git a/gas/testsuite/gas/bpf/alu32-pseudoc.s b/gas/testsuite/gas/bpf/= alu32-pseudoc.s index 0a0d41fdf46..5a0e442154f 100644 --- a/gas/testsuite/gas/bpf/alu32-pseudoc.s +++ b/gas/testsuite/gas/bpf/alu32-pseudoc.s @@ -49,3 +49,6 @@ w4 s>>=3D 2125315823 w5 s>>=3D w6 w2 =3D - w3 + w1 s=3D (i8) w2 + w1 s=3D (i16) w2 + w1 s=3D (i32) w2 diff --git a/gas/testsuite/gas/bpf/alu32.d b/gas/testsuite/gas/bpf/alu32.d index 712d1c7328e..68aa86fce09 100644 --- a/gas/testsuite/gas/bpf/alu32.d +++ b/gas/testsuite/gas/bpf/alu32.d @@ -57,3 +57,6 @@ Disassembly of section .text: 170: c4 04 00 00 ef be ad 7e arsh32 %r4,0x7eadbeef 178: cc 65 00 00 00 00 00 00 arsh32 %r5,%r6 180: 8c 32 00 00 00 00 00 00 neg32 %r2,%r3 + 188: bc 21 08 00 00 00 00 00 movs32 %r1,%r2,8 + 190: bc 21 10 00 00 00 00 00 movs32 %r1,%r2,16 + 198: bc 21 20 00 00 00 00 00 movs32 %r1,%r2,32 diff --git a/gas/testsuite/gas/bpf/alu32.s b/gas/testsuite/gas/bpf/alu32.s index f43ea4a4d23..14f0a12de2c 100644 --- a/gas/testsuite/gas/bpf/alu32.s +++ b/gas/testsuite/gas/bpf/alu32.s @@ -49,3 +49,6 @@ arsh32 %r4, 0x7eadbeef arsh32 %r5, %r6 neg32 %r2, %r3 + movs32 %r1,%r2,8 + movs32 %r1,%r2,16 + movs32 %r1,%r2,32 diff --git a/include/ChangeLog b/include/ChangeLog index f0c8fe875ea..5872f284533 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,11 @@ +2023-07-21 Jose E. Marchesi + + * opcode/bpf.h (BPF_OFFSET16_MOVS8): Define. + (BPF_OFFSET16_MOVS16): Likewise. + (BPF_OFFSET16_MOVS32): Likewise. + (enum bpf_insn_id): Add entries for MOVS{8,16,32}R and + MOVS32{8,16,32}R. + 2023-07-03 Nick Clifton =20 2.41 Branch Point. diff --git a/include/opcode/bpf.h b/include/opcode/bpf.h index f928979f86f..48f06c264ba 100644 --- a/include/opcode/bpf.h +++ b/include/opcode/bpf.h @@ -131,6 +131,9 @@ typedef uint64_t bpf_insn_word; even if these are multi-byte or infra-byte. Bleh. */ =20 #define BPF_OFFSET16_SDIVMOD ((uint64_t)0x1 << 32) +#define BPF_OFFSET16_MOVS8 ((uint64_t)8 << 32) +#define BPF_OFFSET16_MOVS16 ((uint64_t)16 << 32) +#define BPF_OFFSET16_MOVS32 ((uint64_t)32 << 32) =20 #define BPF_IMM32_END16 ((uint64_t)0x00000010) #define BPF_IMM32_END32 ((uint64_t)0x00000020) @@ -162,6 +165,7 @@ enum bpf_insn_id BPF_INSN_ANDR, BPF_INSN_ANDI, BPF_INSN_XORR, BPF_INSN_XORI, BPF_INSN_NEGR, BPF_INSN_NEGI, BPF_INSN_LSHR, BPF_INSN_LSHI, BPF_INSN_RSHR, BPF_INSN_RSHI, BPF_INSN_ARSHR, BPF_INSN_ARSHI, + BPF_INSN_MOVS8R, BPF_INSN_MOVS16R, BPF_INSN_MOVS32R, BPF_INSN_MOVR, BPF_INSN_MOVI, /* ALU32 instructions. */ BPF_INSN_ADD32R, BPF_INSN_ADD32I, BPF_INSN_SUB32R, BPF_INSN_SUB32I, @@ -171,6 +175,7 @@ enum bpf_insn_id BPF_INSN_AND32R, BPF_INSN_AND32I, BPF_INSN_XOR32R, BPF_INSN_XOR32I, BPF_INSN_NEG32R, BPF_INSN_NEG32I, BPF_INSN_LSH32R, BPF_INSN_LSH32I, BPF_INSN_RSH32R, BPF_INSN_RSH32I, BPF_INSN_ARSH32R, BPF_INSN_ARSH32I, + BPF_INSN_MOVS328R, BPF_INSN_MOVS3216R, BPF_INSN_MOVS3232R, BPF_INSN_MOV32R, BPF_INSN_MOV32I, /* Endianness conversion instructions. */ BPF_INSN_ENDLE16, BPF_INSN_ENDLE32, BPF_INSN_ENDLE64, diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index f202d1941bc..55d4e7d657f 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2023-07-21 Jose E. Marchesi + + * bpf-opc.c (bpf_opcodes): Add entries for MOVS{8,16,32}R and + MOVS32{8,16,32}R instructions. and MOVS32I instructions. + 2023-07-21 Jose E. Marchesi =20 * Makefile.am (TARGET64_LIBOPCODES_CFILES): Add missing bpf-dis.c diff --git a/opcodes/bpf-opc.c b/opcodes/bpf-opc.c index f89d93a5c78..72be1d956d5 100644 --- a/opcodes/bpf-opc.c +++ b/opcodes/bpf-opc.c @@ -89,6 +89,12 @@ const struct bpf_opcode bpf_opcodes[] =3D BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_ARSH|BPF_SRC_X}, {BPF_INSN_ARSHI, "arsh%W%dr , %i32", "%dr%ws>>=3D %i32", BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_ARSH|BPF_SRC_K}, + {BPF_INSN_MOVS8R, "movs%W%dr , %sr , 8", "%dr%ws=3D%w( i8 )%w%sr", + BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU64|BPF_CODE_MOV|BPF_SRC_X|B= PF_OFFSET16_MOVS8}, + {BPF_INSN_MOVS16R, "movs%W%dr , %sr , 16", "%dr%ws=3D%w( i16 )%w%sr", + BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU64|BPF_CODE_MOV|BPF_SRC_X|B= PF_OFFSET16_MOVS16}, + {BPF_INSN_MOVS32R, "movs%W%dr , %sr , 32", "%dr%ws=3D%w( i32 )%w%sr", + BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU64|BPF_CODE_MOV|BPF_SRC_X|B= PF_OFFSET16_MOVS32}, {BPF_INSN_MOVR, "mov%W%dr , %sr", "%dr =3D %sr", BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_MOV|BPF_SRC_X}, {BPF_INSN_MOVI, "mov%W%dr , %i32", "%dr =3D %i32", @@ -151,6 +157,12 @@ const struct bpf_opcode bpf_opcodes[] =3D BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_ARSH|BPF_SRC_X}, {BPF_INSN_ARSH32I, "arsh32%W%dr , %i32", "%dw%Ws>>=3D %i32", BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_ARSH|BPF_SRC_K}, + {BPF_INSN_MOVS328R, "movs32%W%dr , %sr , 8", "%dw%ws=3D%w( i8 )%w%sw", + BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU|BPF_CODE_MOV|BPF_SRC_X|BPF= _OFFSET16_MOVS8}, + {BPF_INSN_MOVS3216R, "movs32%W%dr , %sr , 16", "%dw%ws=3D%w( i16 )%w%sw", + BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU|BPF_CODE_MOV|BPF_SRC_X|BPF= _OFFSET16_MOVS16}, + {BPF_INSN_MOVS3232R, "movs32%W%dr , %sr , 32", "%dw%ws=3D%w( i32 )%w%sw", + BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU|BPF_CODE_MOV|BPF_SRC_X|BPF= _OFFSET16_MOVS32}, {BPF_INSN_MOV32R, "mov32%W%dr , %sr", "%dw =3D %sw", BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_MOV|BPF_SRC_X}, {BPF_INSN_MOV32I, "mov32%W%dr , %i32", "%dw =3D %i32",