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From: Tsukasa OI <a4lg@sourceware.org>
To: bfd-cvs@sourceware.org
Subject: [binutils-gdb] RISC-V: Implications from 'Zc[fd]' extensions
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https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D6e30678feb8a=
b38ad80a589226c5d0e9c9dc399e

commit 6e30678feb8ab38ad80a589226c5d0e9c9dc399e
Author: Tsukasa OI <research_trasio@irq.a4lg.com>
Date:   Mon Jul 24 05:09:39 2023 +0000

    RISC-V: Implications from 'Zc[fd]' extensions
   =20
    The version 1.0.4-1 of the code size reduction specification clarifies
    that 'Zcf' implies 'F' and 'Zcd' implies 'D'.
   =20
    cf:
    <https://github.com/riscv/riscv-code-size-reduction/releases/tag/v1.0.4=
-1>
   =20
    This commit adds those implications.
   =20
    bfd/ChangeLog:
   =20
            * elfxx-riscv.c (riscv_implicit_subsets): Add two implications,
            'Zcf' -> 'F' and 'Zcd' -> 'D'.
   =20
    gas/ChangeLog:
   =20
            * testsuite/gas/riscv/march-imply-zcd.d: New test.
            * testsuite/gas/riscv/march-imply-zcf.d: New test.

Diff:
---
 bfd/elfxx-riscv.c                         | 2 ++
 gas/testsuite/gas/riscv/march-imply-zcd.d | 6 ++++++
 gas/testsuite/gas/riscv/march-imply-zcf.d | 6 ++++++
 3 files changed, 14 insertions(+)

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index eaf496649db..b43d2cfa0fa 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1132,6 +1132,8 @@ static struct riscv_implicit_subset riscv_implicit_su=
bsets[] =3D
   {"zvl256b", "zvl128b",	check_implicit_always},
   {"zvl128b", "zvl64b",		check_implicit_always},
   {"zvl64b", "zvl32b",		check_implicit_always},
+  {"zcd", "d",		check_implicit_always},
+  {"zcf", "f",		check_implicit_always},
   {"zfa", "f",		check_implicit_always},
   {"d", "f",		check_implicit_always},
   {"zfh", "zfhmin",	check_implicit_always},
diff --git a/gas/testsuite/gas/riscv/march-imply-zcd.d b/gas/testsuite/gas/=
riscv/march-imply-zcd.d
new file mode 100644
index 00000000000..e7c75f649a8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/march-imply-zcd.d
@@ -0,0 +1,6 @@
+#as: -march=3Drv32i_zcd -march-attr -misa-spec=3D20191213
+#readelf: -A
+#source: empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_f2p2_d2p2_zicsr2p0_zca1p0_zcd1p0"
diff --git a/gas/testsuite/gas/riscv/march-imply-zcf.d b/gas/testsuite/gas/=
riscv/march-imply-zcf.d
new file mode 100644
index 00000000000..3829637a16f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/march-imply-zcf.d
@@ -0,0 +1,6 @@
+#as: -march=3Drv32i_zcf -march-attr -misa-spec=3D20191213
+#readelf: -A
+#source: empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_f2p2_zicsr2p0_zca1p0_zcf1p0"