From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1386) id CB1203858C39; Mon, 7 Aug 2023 09:57:03 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org CB1203858C39 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Jan Beulich To: bfd-cvs@sourceware.org Subject: [binutils-gdb] RISC-V: move comment describing rules for riscv_opcodes[] X-Act-Checkin: binutils-gdb X-Git-Author: Jan Beulich X-Git-Refname: refs/heads/master X-Git-Oldrev: 2f98b09492b33b95afcc1ac22d212ee4a5be0149 X-Git-Newrev: 8d27b09d0877982dc2252c01a3f1d9c631b2d6eb Message-Id: <20230807095703.CB1203858C39@sourceware.org> Date: Mon, 7 Aug 2023 09:57:03 +0000 (GMT) X-BeenThere: binutils-cvs@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 07 Aug 2023 09:57:03 -0000 https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D8d27b09d0877= 982dc2252c01a3f1d9c631b2d6eb commit 8d27b09d0877982dc2252c01a3f1d9c631b2d6eb Author: Jan Beulich Date: Mon Aug 7 11:56:50 2023 +0200 RISC-V: move comment describing rules for riscv_opcodes[] =20 It makes little sense to have this comment meanwhile over a hundred lines ahead of the array. In fact until spotting the comment, I was wondering why those pretty important aspects aren't spelled out anywhere. Diff: --- opcodes/riscv-opc.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 6a854736fec..3efab9a407d 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -131,16 +131,6 @@ const float riscv_fli_numval[32] =3D 0x1p+3, 0x1p+4, 0x1p+7, 0x1p+8, 0x1p+15, 0x1p+16, 0x0p+0, 0x0p+0 }; =20 -/* The order of overloaded instructions matters. Label arguments and - register arguments look the same. Instructions that can have either - for arguments must apear in the correct order in this table for the - assembler to pick the right one. In other words, entries with - immediate operands must apear after the same instruction with - registers. - - Because of the lookup algorithm used, entries with the same opcode - name must be contiguous. */ - #define MASK_RS1 (OP_MASK_RS1 << OP_SH_RS1) #define MASK_RS2 (OP_MASK_RS2 << OP_SH_RS2) #define MASK_RD (OP_MASK_RD << OP_SH_RD) @@ -329,6 +319,16 @@ match_th_load_pair(const struct riscv_opcode *op, return rd1 !=3D rd2 && rd1 !=3D rs && rd2 !=3D rs && match_opcode (op, i= nsn); } =20 +/* The order of overloaded instructions matters. Label arguments and + register arguments look the same. Instructions that can have either + for arguments must apear in the correct order in this table for the + assembler to pick the right one. In other words, entries with + immediate operands must apear after the same instruction with + registers. + + Because of the lookup algorithm used, entries with the same opcode + name must be contiguous. */ + const struct riscv_opcode riscv_opcodes[] =3D { /* name, xlen, isa, operands, match, mask, match_func, pinfo. */