* [binutils-gdb] RISC-V: reduce redundancy in load/store macro insn handling
@ 2023-11-03 9:04 Jan Beulich
0 siblings, 0 replies; only message in thread
From: Jan Beulich @ 2023-11-03 9:04 UTC (permalink / raw)
To: bfd-cvs
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=c76820a017db5f7267d3e86851af41dd8adcbebf
commit c76820a017db5f7267d3e86851af41dd8adcbebf
Author: Jan Beulich <jbeulich@suse.com>
Date: Fri Nov 3 10:03:36 2023 +0100
RISC-V: reduce redundancy in load/store macro insn handling
Within the groups L{B,BU,H,HU,W,WU,D}, S{B,H,W,D}, FL{H,W,D,Q}, and
FS{H,W,D,Q} the sole difference between the handling is the insn
mnemonic passed to the common handling functions. The intended mnemonic,
however, can easily be retrieved. Furthermore leverags that Sx and FSx
are then handled identically, too, and hence their cases can also be
folded.
Diff:
---
gas/config/tc-riscv.c | 91 ++++----------------------------------------------
include/opcode/riscv.h | 22 ++----------
opcodes/riscv-opc.c | 38 ++++++++++-----------
3 files changed, 28 insertions(+), 123 deletions(-)
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index aa952a68edd..30e14bbb9ad 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -2056,88 +2056,18 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
BFD_RELOC_RISCV_TLS_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
break;
- case M_LB:
- pcrel_load (rd, rd, imm_expr, "lb",
+ case M_Lx:
+ pcrel_load (rd, rd, imm_expr, ip->insn_mo->name,
BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
break;
- case M_LBU:
- pcrel_load (rd, rd, imm_expr, "lbu",
+ case M_FLx:
+ pcrel_load (rd, rs1, imm_expr, ip->insn_mo->name,
BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
break;
- case M_LH:
- pcrel_load (rd, rd, imm_expr, "lh",
- BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
- break;
-
- case M_LHU:
- pcrel_load (rd, rd, imm_expr, "lhu",
- BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
- break;
-
- case M_LW:
- pcrel_load (rd, rd, imm_expr, "lw",
- BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
- break;
-
- case M_LWU:
- pcrel_load (rd, rd, imm_expr, "lwu",
- BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
- break;
-
- case M_LD:
- pcrel_load (rd, rd, imm_expr, "ld",
- BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
- break;
-
- case M_FLW:
- pcrel_load (rd, rs1, imm_expr, "flw",
- BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
- break;
-
- case M_FLD:
- pcrel_load (rd, rs1, imm_expr, "fld",
- BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
- break;
-
- case M_FLQ:
- pcrel_load (rd, rs1, imm_expr, "flq",
- BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
- break;
-
- case M_SB:
- pcrel_store (rs2, rs1, imm_expr, "sb",
- BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
- break;
-
- case M_SH:
- pcrel_store (rs2, rs1, imm_expr, "sh",
- BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
- break;
-
- case M_SW:
- pcrel_store (rs2, rs1, imm_expr, "sw",
- BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
- break;
-
- case M_SD:
- pcrel_store (rs2, rs1, imm_expr, "sd",
- BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
- break;
-
- case M_FSW:
- pcrel_store (rs2, rs1, imm_expr, "fsw",
- BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
- break;
-
- case M_FSD:
- pcrel_store (rs2, rs1, imm_expr, "fsd",
- BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
- break;
-
- case M_FSQ:
- pcrel_store (rs2, rs1, imm_expr, "fsq",
+ case M_Sx_FSx:
+ pcrel_store (rs2, rs1, imm_expr, ip->insn_mo->name,
BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
break;
@@ -2165,15 +2095,6 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
vector_macro (ip);
break;
- case M_FLH:
- pcrel_load (rd, rs1, imm_expr, "flh",
- BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I);
- break;
- case M_FSH:
- pcrel_store (rs2, rs1, imm_expr, "fsh",
- BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S);
- break;
-
default:
as_bad (_("internal: macro %s not implemented"), ip->insn_mo->name);
break;
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 93dd5169ebc..791148914af 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -538,23 +538,9 @@ enum
M_LGA,
M_LA_TLS_GD,
M_LA_TLS_IE,
- M_LB,
- M_LBU,
- M_LH,
- M_LHU,
- M_LW,
- M_LWU,
- M_LD,
- M_SB,
- M_SH,
- M_SW,
- M_SD,
- M_FLW,
- M_FLD,
- M_FLQ,
- M_FSW,
- M_FSD,
- M_FSQ,
+ M_Lx,
+ M_FLx,
+ M_Sx_FSx,
M_CALL,
M_J,
M_LI,
@@ -563,8 +549,6 @@ enum
M_SEXTB,
M_SEXTH,
M_VMSGE,
- M_FLH,
- M_FSH,
M_NUM_MACROS
};
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 8e0ae85eb06..8d92d8b1aaf 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -462,20 +462,20 @@ const struct riscv_opcode riscv_opcodes[] =
{"sub", 0, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_SUB, MASK_C_SUB, match_opcode, INSN_ALIAS },
{"sub", 0, INSN_CLASS_I, "d,s,t", MATCH_SUB, MASK_SUB, match_opcode, 0 },
{"lb", 0, INSN_CLASS_I, "d,o(s)", MATCH_LB, MASK_LB, match_opcode, INSN_DREF|INSN_1_BYTE },
-{"lb", 0, INSN_CLASS_I, "d,A", 0, (int) M_LB, match_never, INSN_MACRO },
+{"lb", 0, INSN_CLASS_I, "d,A", 0, (int) M_Lx, match_never, INSN_MACRO },
{"lbu", 0, INSN_CLASS_ZCB, "Ct,Wcb(Cs)", MATCH_C_LBU, MASK_C_LBU, match_opcode, INSN_ALIAS|INSN_DREF|INSN_1_BYTE },
{"lbu", 0, INSN_CLASS_I, "d,o(s)", MATCH_LBU, MASK_LBU, match_opcode, INSN_DREF|INSN_1_BYTE },
-{"lbu", 0, INSN_CLASS_I, "d,A", 0, (int) M_LBU, match_never, INSN_MACRO },
+{"lbu", 0, INSN_CLASS_I, "d,A", 0, (int) M_Lx, match_never, INSN_MACRO },
{"lh", 0, INSN_CLASS_ZCB, "Ct,Wch(Cs)", MATCH_C_LH, MASK_C_LH, match_opcode, INSN_ALIAS|INSN_DREF|INSN_2_BYTE },
{"lh", 0, INSN_CLASS_I, "d,o(s)", MATCH_LH, MASK_LH, match_opcode, INSN_DREF|INSN_2_BYTE },
-{"lh", 0, INSN_CLASS_I, "d,A", 0, (int) M_LH, match_never, INSN_MACRO },
+{"lh", 0, INSN_CLASS_I, "d,A", 0, (int) M_Lx, match_never, INSN_MACRO },
{"lhu", 0, INSN_CLASS_ZCB, "Ct,Wch(Cs)", MATCH_C_LHU, MASK_C_LHU, match_opcode, INSN_ALIAS|INSN_DREF|INSN_2_BYTE },
{"lhu", 0, INSN_CLASS_I, "d,o(s)", MATCH_LHU, MASK_LHU, match_opcode, INSN_DREF|INSN_2_BYTE },
-{"lhu", 0, INSN_CLASS_I, "d,A", 0, (int) M_LHU, match_never, INSN_MACRO },
+{"lhu", 0, INSN_CLASS_I, "d,A", 0, (int) M_Lx, match_never, INSN_MACRO },
{"lw", 0, INSN_CLASS_C, "d,Cm(Cc)", MATCH_C_LWSP, MASK_C_LWSP, match_rd_nonzero, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
{"lw", 0, INSN_CLASS_C, "Ct,Ck(Cs)", MATCH_C_LW, MASK_C_LW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
{"lw", 0, INSN_CLASS_I, "d,o(s)", MATCH_LW, MASK_LW, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"lw", 0, INSN_CLASS_I, "d,A", 0, (int) M_LW, match_never, INSN_MACRO },
+{"lw", 0, INSN_CLASS_I, "d,A", 0, (int) M_Lx, match_never, INSN_MACRO },
{"not", 0, INSN_CLASS_ZCB, "Cs,Cw", MATCH_C_NOT, MASK_C_NOT, match_opcode, INSN_ALIAS },
{"not", 0, INSN_CLASS_I, "d,s", MATCH_XORI|MASK_IMM, MASK_XORI|MASK_IMM, match_opcode, INSN_ALIAS },
{"ori", 0, INSN_CLASS_I, "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, 0 },
@@ -498,14 +498,14 @@ const struct riscv_opcode riscv_opcodes[] =
{"sgtu", 0, INSN_CLASS_I, "d,t,s", MATCH_SLTU, MASK_SLTU, match_opcode, INSN_ALIAS },
{"sb", 0, INSN_CLASS_ZCB, "Ct,Wcb(Cs)", MATCH_C_SB, MASK_C_SB, match_opcode, INSN_DREF|INSN_1_BYTE|INSN_ALIAS },
{"sb", 0, INSN_CLASS_I, "t,q(s)", MATCH_SB, MASK_SB, match_opcode, INSN_DREF|INSN_1_BYTE },
-{"sb", 0, INSN_CLASS_I, "t,A,s", 0, (int) M_SB, match_never, INSN_MACRO },
+{"sb", 0, INSN_CLASS_I, "t,A,s", 0, (int) M_Sx_FSx, match_never, INSN_MACRO },
{"sh", 0, INSN_CLASS_ZCB, "Ct,Wch(Cs)", MATCH_C_SH, MASK_C_SH, match_opcode, INSN_DREF|INSN_2_BYTE|INSN_ALIAS },
{"sh", 0, INSN_CLASS_I, "t,q(s)", MATCH_SH, MASK_SH, match_opcode, INSN_DREF|INSN_2_BYTE },
-{"sh", 0, INSN_CLASS_I, "t,A,s", 0, (int) M_SH, match_never, INSN_MACRO },
+{"sh", 0, INSN_CLASS_I, "t,A,s", 0, (int) M_Sx_FSx, match_never, INSN_MACRO },
{"sw", 0, INSN_CLASS_C, "CV,CM(Cc)", MATCH_C_SWSP, MASK_C_SWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
{"sw", 0, INSN_CLASS_C, "Ct,Ck(Cs)", MATCH_C_SW, MASK_C_SW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
{"sw", 0, INSN_CLASS_I, "t,q(s)", MATCH_SW, MASK_SW, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"sw", 0, INSN_CLASS_I, "t,A,s", 0, (int) M_SW, match_never, INSN_MACRO },
+{"sw", 0, INSN_CLASS_I, "t,A,s", 0, (int) M_Sx_FSx, match_never, INSN_MACRO },
{"fence", 0, INSN_CLASS_I, "", MATCH_FENCE|MASK_PRED|MASK_SUCC, MASK_FENCE|MASK_RD|MASK_RS1|MASK_IMM, match_opcode, INSN_ALIAS },
{"fence", 0, INSN_CLASS_I, "P,Q", MATCH_FENCE, MASK_FENCE|MASK_RD|MASK_RS1|(MASK_IMM & ~MASK_PRED & ~MASK_SUCC), match_opcode, 0 },
{"fence.i", 0, INSN_CLASS_ZIFENCEI, "", MATCH_FENCE_I, MASK_FENCE|MASK_RD|MASK_RS1|MASK_IMM, match_opcode, 0 },
@@ -524,15 +524,15 @@ const struct riscv_opcode riscv_opcodes[] =
{"xor", 0, INSN_CLASS_C, "Cs,Ct,Cw", MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS },
{"xor", 0, INSN_CLASS_I, "d,s,t", MATCH_XOR, MASK_XOR, match_opcode, 0 },
{"lwu", 64, INSN_CLASS_I, "d,o(s)", MATCH_LWU, MASK_LWU, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"lwu", 64, INSN_CLASS_I, "d,A", 0, (int) M_LWU, match_never, INSN_MACRO },
+{"lwu", 64, INSN_CLASS_I, "d,A", 0, (int) M_Lx, match_never, INSN_MACRO },
{"ld", 64, INSN_CLASS_C, "d,Cn(Cc)", MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
{"ld", 64, INSN_CLASS_C, "Ct,Cl(Cs)", MATCH_C_LD, MASK_C_LD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
{"ld", 64, INSN_CLASS_I, "d,o(s)", MATCH_LD, MASK_LD, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"ld", 64, INSN_CLASS_I, "d,A", 0, (int) M_LD, match_never, INSN_MACRO },
+{"ld", 64, INSN_CLASS_I, "d,A", 0, (int) M_Lx, match_never, INSN_MACRO },
{"sd", 64, INSN_CLASS_C, "CV,CN(Cc)", MATCH_C_SDSP, MASK_C_SDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
{"sd", 64, INSN_CLASS_C, "Ct,Cl(Cs)", MATCH_C_SD, MASK_C_SD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
{"sd", 64, INSN_CLASS_I, "t,q(s)", MATCH_SD, MASK_SD, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"sd", 64, INSN_CLASS_I, "t,A,s", 0, (int) M_SD, match_never, INSN_MACRO },
+{"sd", 64, INSN_CLASS_I, "t,A,s", 0, (int) M_Sx_FSx, match_never, INSN_MACRO },
{"sext.w", 64, INSN_CLASS_C, "d,CU", MATCH_C_ADDIW, MASK_C_ADDIW|MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS },
{"sext.w", 64, INSN_CLASS_I, "d,s", MATCH_ADDIW, MASK_ADDIW|MASK_IMM, match_opcode, INSN_ALIAS },
{"addiw", 64, INSN_CLASS_C, "d,CU,Co", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS },
@@ -663,9 +663,9 @@ const struct riscv_opcode riscv_opcodes[] =
/* Half-precision floating-point instruction subset. */
{"flh", 0, INSN_CLASS_ZFHMIN, "D,o(s)", MATCH_FLH, MASK_FLH, match_opcode, INSN_DREF|INSN_2_BYTE },
-{"flh", 0, INSN_CLASS_ZFHMIN, "D,A,s", 0, (int) M_FLH, match_never, INSN_MACRO },
+{"flh", 0, INSN_CLASS_ZFHMIN, "D,A,s", 0, (int) M_FLx, match_never, INSN_MACRO },
{"fsh", 0, INSN_CLASS_ZFHMIN, "T,q(s)", MATCH_FSH, MASK_FSH, match_opcode, INSN_DREF|INSN_2_BYTE },
-{"fsh", 0, INSN_CLASS_ZFHMIN, "T,A,s", 0, (int) M_FSH, match_never, INSN_MACRO },
+{"fsh", 0, INSN_CLASS_ZFHMIN, "T,A,s", 0, (int) M_Sx_FSx, match_never, INSN_MACRO },
{"fmv.x.h", 0, INSN_CLASS_ZFHMIN, "d,S", MATCH_FMV_X_H, MASK_FMV_X_H, match_opcode, 0 },
{"fmv.h.x", 0, INSN_CLASS_ZFHMIN, "D,s", MATCH_FMV_H_X, MASK_FMV_H_X, match_opcode, 0 },
{"fmv.h", 0, INSN_CLASS_ZFH_INX, "D,U", MATCH_FSGNJ_H, MASK_FSGNJ_H, match_rs1_eq_rs2, INSN_ALIAS },
@@ -746,11 +746,11 @@ const struct riscv_opcode riscv_opcodes[] =
{"flw", 32, INSN_CLASS_F_AND_C, "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
{"flw", 32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
{"flw", 0, INSN_CLASS_F, "D,o(s)", MATCH_FLW, MASK_FLW, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"flw", 0, INSN_CLASS_F, "D,A,s", 0, (int) M_FLW, match_never, INSN_MACRO },
+{"flw", 0, INSN_CLASS_F, "D,A,s", 0, (int) M_FLx, match_never, INSN_MACRO },
{"fsw", 32, INSN_CLASS_F_AND_C, "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
{"fsw", 32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
{"fsw", 0, INSN_CLASS_F, "T,q(s)", MATCH_FSW, MASK_FSW, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"fsw", 0, INSN_CLASS_F, "T,A,s", 0, (int) M_FSW, match_never, INSN_MACRO },
+{"fsw", 0, INSN_CLASS_F, "T,A,s", 0, (int) M_Sx_FSx, match_never, INSN_MACRO },
{"fmv.x.w", 0, INSN_CLASS_F, "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 },
{"fmv.w.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 },
{"fmv.x.s", 0, INSN_CLASS_F, "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 },
@@ -808,11 +808,11 @@ const struct riscv_opcode riscv_opcodes[] =
{"fld", 0, INSN_CLASS_D_AND_C, "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
{"fld", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
{"fld", 0, INSN_CLASS_D, "D,o(s)", MATCH_FLD, MASK_FLD, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"fld", 0, INSN_CLASS_D, "D,A,s", 0, (int) M_FLD, match_never, INSN_MACRO },
+{"fld", 0, INSN_CLASS_D, "D,A,s", 0, (int) M_FLx, match_never, INSN_MACRO },
{"fsd", 0, INSN_CLASS_D_AND_C, "CT,CN(Cc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
{"fsd", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
{"fsd", 0, INSN_CLASS_D, "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"fsd", 0, INSN_CLASS_D, "T,A,s", 0, (int) M_FSD, match_never, INSN_MACRO },
+{"fsd", 0, INSN_CLASS_D, "T,A,s", 0, (int) M_Sx_FSx, match_never, INSN_MACRO },
{"fmv.d", 0, INSN_CLASS_D_INX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS },
{"fneg.d", 0, INSN_CLASS_D_INX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS },
{"fabs.d", 0, INSN_CLASS_D_INX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS },
@@ -867,9 +867,9 @@ const struct riscv_opcode riscv_opcodes[] =
/* Quad-precision floating-point instruction subset. */
{"flq", 0, INSN_CLASS_Q, "D,o(s)", MATCH_FLQ, MASK_FLQ, match_opcode, INSN_DREF|INSN_16_BYTE },
-{"flq", 0, INSN_CLASS_Q, "D,A,s", 0, (int) M_FLQ, match_never, INSN_MACRO },
+{"flq", 0, INSN_CLASS_Q, "D,A,s", 0, (int) M_FLx, match_never, INSN_MACRO },
{"fsq", 0, INSN_CLASS_Q, "T,q(s)", MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE },
-{"fsq", 0, INSN_CLASS_Q, "T,A,s", 0, (int) M_FSQ, match_never, INSN_MACRO },
+{"fsq", 0, INSN_CLASS_Q, "T,A,s", 0, (int) M_Sx_FSx, match_never, INSN_MACRO },
{"fmv.q", 0, INSN_CLASS_Q_INX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS },
{"fneg.q", 0, INSN_CLASS_Q_INX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS },
{"fabs.q", 0, INSN_CLASS_Q_INX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS },
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2023-11-03 9:04 [binutils-gdb] RISC-V: reduce redundancy in load/store macro insn handling Jan Beulich
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