[binutils-gdb] aarch64: Add LSE128 instruction operand support

[binutils-gdb] aarch64: Add LSE128 instruction operand support

[Victor Do Nascimento]

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=6219f9dae7d04b52ef171e0aa3341bf977b05a68

commit 6219f9dae7d04b52ef171e0aa3341bf977b05a68
Author: Victor Do Nascimento <victor.donascimento@arm.com>
Date:   Mon Oct 30 11:47:23 2023 +0000

    aarch64: Add LSE128 instruction operand support
    
    Given the particular encoding of the LSE128 instructions, create the
    necessary shared input+output operand register description and
    handling in the code to allow for the encoding of the LSE128 128-bit
    atomic operations.
    
    gas/ChangeLog:
    
            * config/tc-aarch64.c (parse_operands):
    
    include/ChangeLog:
    
            * opcode/aarch64.h (enum aarch64_opnd):
    
    opcodes/ChangeLog:
    
            * aarch64-opc.c (fields):
            (aarch64_print_operand):
            * aarch64-opc.h (enum aarch64_field_kind):
            * aarch64-tbl.h (AARCH64_OPERANDS):

Diff:
---
 gas/config/tc-aarch64.c  | 5 +++++
 include/opcode/aarch64.h | 2 ++
 opcodes/aarch64-opc.c    | 4 ++++
 opcodes/aarch64-opc.h    | 2 ++
 opcodes/aarch64-tbl.h    | 2 ++
 5 files changed, 15 insertions(+)

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index c6566e11128..4367455aa23 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -7863,6 +7863,11 @@ parse_operands (char *str, const aarch64_opcode *opcode)
 	  po_char_or_fail ('!');
 	  break;
 
+	case AARCH64_OPND_LSE128_Rt:
+	case AARCH64_OPND_LSE128_Rt2:
+	  po_int_fp_reg_or_fail (REG_TYPE_R_64);
+	  break;
+
 	default:
 	  as_fatal (_("unhandled operand code %d"), operands[i]);
 	}
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index c0817604380..1ede57094f8 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -521,6 +521,8 @@ enum aarch64_opnd
   AARCH64_OPND_BARRIER_PSB,	/* Barrier operand for PSB.  */
   AARCH64_OPND_BARRIER_GCSB,	/* Barrier operand for GCSB.  */
   AARCH64_OPND_BTI_TARGET,	/* BTI {<target>}.  */
+  AARCH64_OPND_LSE128_Rt,	/* LSE128 <Xt1>.  */
+  AARCH64_OPND_LSE128_Rt2,	/* LSE128 <Xt2>.  */
   AARCH64_OPND_SVE_ADDR_RI_S4x16,   /* SVE [<Xn|SP>, #<simm4>*16].  */
   AARCH64_OPND_SVE_ADDR_RI_S4x32,   /* SVE [<Xn|SP>, #<simm4>*32].  */
   AARCH64_OPND_SVE_ADDR_RI_S4xVL,   /* SVE [<Xn|SP>, #<simm4>, MUL VL].  */
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 336a49feb68..5a0f0e9f52e 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -226,6 +226,8 @@ const aarch64_field fields[] =
     { 10,  8 }, /* CSSC_imm8.  */
     { 11,  1 },	/* H: in advsimd scalar x indexed element instructions.  */
     { 21,  1 },	/* L: in advsimd scalar x indexed element instructions.  */
+    {  0,  5 },	/* LSE128_Rt: Shared input+output operand register.  */
+    { 16,  5 },	/* LSE128_Rt2: Shared input+output operand register 2.  */
     { 20,  1 },	/* M: in advsimd scalar x indexed element instructions.  */
     { 22,  1 },	/* N: in logical (immediate) instructions.  */
     { 30,  1 },	/* Q: in most AdvSIMD instructions.  */
@@ -3770,6 +3772,8 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
     case AARCH64_OPND_Rt_SYS:
     case AARCH64_OPND_PAIRREG:
     case AARCH64_OPND_SVE_Rm:
+    case AARCH64_OPND_LSE128_Rt:
+    case AARCH64_OPND_LSE128_Rt2:
       /* The optional-ness of <Xt> in e.g. IC <ic_op>{, <Xt>} is determined by
 	 the <ic_op>, therefore we use opnd->present to override the
 	 generic optional-ness information.  */
diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index 75d2feb02ea..cf217e86376 100644
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -36,6 +36,8 @@ enum aarch64_field_kind
   FLD_CSSC_imm8,
   FLD_H,
   FLD_L,
+  FLD_LSE128_Rt,
+  FLD_LSE128_Rt2,
   FLD_M,
   FLD_N,
   FLD_Q,
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index e624b855d1b..bc385427016 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -6308,6 +6308,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
       "the GCSB option name DSYNC")					\
     Y(SYSTEM, hint, "BTI_TARGET", 0, F (),				\
       "BTI targets j/c/jc")						\
+    Y(INT_REG, regno, "LSE128_Rt", 0, F(FLD_LSE128_Rt), "an integer register") \
+    Y(INT_REG, regno, "LSE128_Rt2", 0, F(FLD_LSE128_Rt2), "an integer register") \
     Y(ADDRESS, sve_addr_ri_s4, "SVE_ADDR_RI_S4x16",			\
       4 << OPD_F_OD_LSB, F(FLD_Rn),					\
       "an address with a 4-bit signed offset, multiplied by 16")	\