[binutils-gdb] aarch64: Fix error in THE system register checking

[binutils-gdb] aarch64: Fix error in THE system register checking

[Victor Do Nascimento]

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=f11f256f5638679548cd7e1fb189135575cb7b5f

commit f11f256f5638679548cd7e1fb189135575cb7b5f
Author: Victor Do Nascimento <victor.donascimento@arm.com>
Date:   Thu Nov 9 11:19:47 2023 +0000

    aarch64: Fix error in THE system register checking
    
    The erroneous omission of a "reg_value == " in the THE system register
    encoding check added in [1] led to an error which was not picked up in
    GCC but which was flagged in Clang due to its use of
    [-Werror,-Wconstant-logical-operand] check.  Together with this fix we
    add a new test for the THE registers to pick up their illegal use,
    adding an extra and important layer of validation.
    
    Furthermore, in separating system register from instruction
    implementation (with which only the former was of concern in the cited
    patch), additions made to `aarch64-tbl.h' are rolled back so
    that these can be added later when adding THE instructions to the
    codebase, a more natural place for these changes.
    
    [1] https://sourceware.org/pipermail/binutils/2023-November/130314.html
    
    opcodes/ChangeLog:
    
            * aarch64-opc.c (aarch64_sys_ins_reg_supported_p): Fix typo.
            * aarch64-tbl.h (THE): Remove.
             (aarch64_feature_set aarch64_feature_the): Likewise.
    
    gas/ChangeLog:
    
            * testsuite/gas/aarch64/illegal-sysreg-8.l: Add tests for THE
            system registers.
            * testsuite/gas/aarch64/illegal-sysreg-8.s: Likewise.

Diff:
---
 gas/testsuite/gas/aarch64/illegal-sysreg-8.l | 8 ++++++++
 gas/testsuite/gas/aarch64/illegal-sysreg-8.s | 2 ++
 opcodes/aarch64-opc.c                        | 2 +-
 opcodes/aarch64-tbl.h                        | 3 ---
 4 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/gas/testsuite/gas/aarch64/illegal-sysreg-8.l b/gas/testsuite/gas/aarch64/illegal-sysreg-8.l
index 6a5f8fe567c..773e8d80f7a 100644
--- a/gas/testsuite/gas/aarch64/illegal-sysreg-8.l
+++ b/gas/testsuite/gas/aarch64/illegal-sysreg-8.l
@@ -3,6 +3,14 @@
 .*: *Info: macro .*
 .*: Error: selected processor does not support system register name 'ccsidr2_el1'
 .*: *Info: macro .*
+.*: Error: selected processor does not support system register name 'rcwmask_el1'
+.*: *Info: macro .*
+.*: Error: selected processor does not support system register name 'rcwmask_el1'
+.*: *Info: macro .*
+.*: Error: selected processor does not support system register name 'rcwsmask_el1'
+.*: *Info: macro .*
+.*: Error: selected processor does not support system register name 'rcwsmask_el1'
+.*: *Info: macro .*
 .*: Error: selected processor does not support system register name 'trfcr_el1'
 .*: *Info: macro .*
 .*: Error: selected processor does not support system register name 'trfcr_el1'
diff --git a/gas/testsuite/gas/aarch64/illegal-sysreg-8.s b/gas/testsuite/gas/aarch64/illegal-sysreg-8.s
index a1a7ae6faed..0ce61ddfe45 100644
--- a/gas/testsuite/gas/aarch64/illegal-sysreg-8.s
+++ b/gas/testsuite/gas/aarch64/illegal-sysreg-8.s
@@ -16,6 +16,8 @@
 	.arch	armv8.2-a
 
 	roreg	ccsidr2_el1
+	rwreg	rcwmask_el1
+	rwreg	rcwsmask_el1
 
 	.arch	armv8.3-a
 
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 5a0f0e9f52e..f8d4c1a4d33 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -5037,7 +5037,7 @@ aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
     return true;
 
   if ((reg_value == CPENC (3,0,13,0,3)
-       || CPENC (3,0,13,0,6))
+       || reg_value == CPENC (3,0,13,0,6))
       && AARCH64_CPU_HAS_FEATURE (features, THE))
     return true;
 
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index feea209ea30..74fd6695d81 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2578,8 +2578,6 @@ static const aarch64_feature_set aarch64_feature_chk =
   AARCH64_FEATURE (CHK);
 static const aarch64_feature_set aarch64_feature_gcs =
   AARCH64_FEATURE (GCS);
-static const aarch64_feature_set aarch64_feature_the =
-  AARCH64_FEATURE (THE);
 
 #define CORE		&aarch64_feature_v8
 #define FP		&aarch64_feature_fp
@@ -2641,7 +2639,6 @@ static const aarch64_feature_set aarch64_feature_the =
 #define CSSC	  &aarch64_feature_cssc
 #define CHK	  &aarch64_feature_chk
 #define GCS	  &aarch64_feature_gcs
-#define THE	  &aarch64_feature_the
 
 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }