From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2098) id B666C3858D33; Thu, 16 Nov 2023 12:18:18 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B666C3858D33 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: SRINATH PARVATHANENI To: bfd-cvs@sourceware.org Subject: [binutils-gdb] aarch64: Add features to the Statistical Profiling Extension. X-Act-Checkin: binutils-gdb X-Git-Author: Srinath Parvathaneni X-Git-Refname: refs/heads/master X-Git-Oldrev: ebd5c32f2f0c2cfaeb5b86e9dd792cc62530be84 X-Git-Newrev: 43e228e98c33d3dbb428f4061de0362ba13ffbf5 Message-Id: <20231116121818.B666C3858D33@sourceware.org> Date: Thu, 16 Nov 2023 12:18:18 +0000 (GMT) X-BeenThere: binutils-cvs@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 16 Nov 2023 12:18:18 -0000 https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D43e228e98c33= d3dbb428f4061de0362ba13ffbf5 commit 43e228e98c33d3dbb428f4061de0362ba13ffbf5 Author: Srinath Parvathaneni Date: Thu Nov 16 12:16:53 2023 +0000 aarch64: Add features to the Statistical Profiling Extension. =20 This patch adds features to the Statistical Profiling Extension, identified as FEAT_SPEv1p4, FEAT_SPE_FDS, and FEAT_SPE_CRR, which are enabled by default from Armv9.4-A. =20 Also adds support for system register "pmsdsfr_el1". Diff: --- gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.d | 3 +++ gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l | 3 +++ gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d | 10 ++++++++++ gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s | 2 ++ include/opcode/aarch64.h | 11 ++++++++++- opcodes/aarch64-sys-regs.def | 1 + 6 files changed, 29 insertions(+), 1 deletion(-) diff --git a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.d b/gas/testsu= ite/gas/aarch64/armv8_9-a-sysregs-bad.d new file mode 100644 index 00000000000..2471b6b52c3 --- /dev/null +++ b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.d @@ -0,0 +1,3 @@ +#as: -march=3Darmv8.8-a +#source: armv8_9-a-sysregs.s +#error_output: armv8_9-a-sysregs-bad.l diff --git a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l b/gas/testsu= ite/gas/aarch64/armv8_9-a-sysregs-bad.l new file mode 100644 index 00000000000..48c55680aa0 --- /dev/null +++ b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Error: selected processor does not support system register name 'pmsds= fr_el1' +.*: Error: selected processor does not support system register name 'pmsds= fr_el1' diff --git a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d b/gas/testsuite/= gas/aarch64/armv8_9-a-sysregs.d new file mode 100644 index 00000000000..d4cb769fdf6 --- /dev/null +++ b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d @@ -0,0 +1,10 @@ +#as: -march=3Darmv8.9-a +#objdump: -dr + +.*: file format .* + +Disassembly of section \.text: + +0+ <.*>: +.*: d53c9a83 mrs x3, pmsdsfr_el1 +.*: d51c9a83 msr pmsdsfr_el1, x3 diff --git a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s b/gas/testsuite/= gas/aarch64/armv8_9-a-sysregs.s new file mode 100644 index 00000000000..4200d7ce60e --- /dev/null +++ b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s @@ -0,0 +1,2 @@ + mrs x3, PMSDSFR_EL1 + msr PMSDSFR_EL1, x3 diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 6be2885c78f..881a4211eab 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -163,6 +163,12 @@ enum aarch64_feature_bit { AARCH64_FEATURE_CHK, /* Guarded Control Stack. */ AARCH64_FEATURE_GCS, + /* SPE Call Return branch records. */ + AARCH64_FEATURE_SPE_CRR, + /* SPE Filter by data source. */ + AARCH64_FEATURE_SPE_FDS, + /* Additional SPE events. */ + AARCH64_FEATURE_SPEv1p4, /* SME2. */ AARCH64_FEATURE_SME2, /* Translation Hardening Extension. */ @@ -224,7 +230,10 @@ enum aarch64_feature_bit { #define AARCH64_ARCH_V8_8A_FEATURES(X) (AARCH64_FEATBIT (X, V8_8A) \ | AARCH64_FEATBIT (X, MOPS) \ | AARCH64_FEATBIT (X, HBC)) -#define AARCH64_ARCH_V8_9A_FEATURES(X) (AARCH64_FEATBIT (X, V8_9A)) +#define AARCH64_ARCH_V8_9A_FEATURES(X) (AARCH64_FEATBIT (X, V8_9A) \ + | AARCH64_FEATBIT (X, SPEv1p4) \ + | AARCH64_FEATBIT (X, SPE_CRR) \ + | AARCH64_FEATBIT (X, SPE_FDS)) =20 #define AARCH64_ARCH_V9A_FEATURES(X) (AARCH64_FEATBIT (X, V9A) \ | AARCH64_FEATBIT (X, F16) \ diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def index 96bdadb0b0f..aab2c7264ca 100644 --- a/opcodes/aarch64-sys-regs.def +++ b/opcodes/aarch64-sys-regs.def @@ -676,6 +676,7 @@ SYSREG ("pmscr_el1", CPENC (3,0,9,9,0), F_ARCHEXT, AARCH64_FEATURE (PR= OFILE)) SYSREG ("pmscr_el12", CPENC (3,5,9,9,0), F_ARCHEXT, AARCH64_FEATURE (P= ROFILE)) SYSREG ("pmscr_el2", CPENC (3,4,9,9,0), F_ARCHEXT, AARCH64_FEATURE (PR= OFILE)) + SYSREG ("pmsdsfr_el1", CPENC (3,4,9,10,4), F_ARCHEXT, AARCH64_FEATURE (= SPE_FDS)) SYSREG ("pmselr_el0", CPENC (3,3,9,12,5), 0, AARCH64_NO_FEATURES) SYSREG ("pmsevfr_el1", CPENC (3,0,9,9,5), F_ARCHEXT, AARCH64_FEATURE (P= ROFILE)) SYSREG ("pmsfcr_el1", CPENC (3,0,9,9,4), F_ARCHEXT, AARCH64_FEATURE (P= ROFILE))