From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2098) id 12FB63858030; Thu, 16 Nov 2023 14:25:01 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 12FB63858030 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: SRINATH PARVATHANENI To: bfd-cvs@sourceware.org Subject: [binutils-gdb] aarch64: Add new AT system instructions. X-Act-Checkin: binutils-gdb X-Git-Author: Srinath Parvathaneni X-Git-Refname: refs/heads/master X-Git-Oldrev: 311276f10c4f85827d3264a2682ae9219917060f X-Git-Newrev: 281fda33bcf47d5d541e28aac1e5772ebdf1eb1a Message-Id: <20231116142501.12FB63858030@sourceware.org> Date: Thu, 16 Nov 2023 14:25:01 +0000 (GMT) X-BeenThere: binutils-cvs@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 16 Nov 2023 14:25:01 -0000 https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D281fda33bcf4= 7d5d541e28aac1e5772ebdf1eb1a commit 281fda33bcf47d5d541e28aac1e5772ebdf1eb1a Author: Srinath Parvathaneni Date: Thu Nov 16 14:24:27 2023 +0000 aarch64: Add new AT system instructions. =20 This patch adds 3 new AT system instructions through FEAT_ATS1A feature, which are available by default from Armv9.4-A architecture. Diff: --- gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l | 3 +++ gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d | 3 +++ gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s | 5 +++++ include/opcode/aarch64.h | 5 ++++- opcodes/aarch64-opc.c | 9 +++++++++ 5 files changed, 24 insertions(+), 1 deletion(-) diff --git a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l b/gas/testsu= ite/gas/aarch64/armv8_9-a-sysregs-bad.l index 63397bcb162..1b67843a4dd 100644 --- a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l +++ b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l @@ -24,3 +24,6 @@ .*: Error: selected processor does not support system register name 'pfar_= el1' .*: Error: selected processor does not support system register name 'pfar_= el2' .*: Error: selected processor does not support system register name 'pfar_= el12' +.*: Error: selected processor does not support system register name 's1e1a' +.*: Error: selected processor does not support system register name 's1e2a' +.*: Error: selected processor does not support system register name 's1e3a' diff --git a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d b/gas/testsuite/= gas/aarch64/armv8_9-a-sysregs.d index 3b66e2bc57c..18376bb5ac1 100644 --- a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d +++ b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d @@ -31,3 +31,6 @@ Disassembly of section \.text: .*: d51860a0 msr pfar_el1, x0 .*: d51c60a0 msr pfar_el2, x0 .*: d51d60a0 msr pfar_el12, x0 +.*: d5087941 at s1e1a, x1 +.*: d50c7943 at s1e2a, x3 +.*: d50e7945 at s1e3a, x5 diff --git a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s b/gas/testsuite/= gas/aarch64/armv8_9-a-sysregs.s index 9ad0a532acc..4e494a965f6 100644 --- a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s +++ b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s @@ -27,3 +27,8 @@ msr PFAR_EL1, x0 msr PFAR_EL2, x0 msr PFAR_EL12, x0 + + /* AT. */ + at s1e1a, x1 + at s1e2a, x3 + at s1e3a, x5 diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 03ef907cac1..792d6a4f4a7 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -183,6 +183,8 @@ enum aarch64_feature_bit { AARCH64_FEATURE_FGT2, /* Physical Fault Address. */ AARCH64_FEATURE_PFAR, + /* Address Translate Stage 1. */ + AARCH64_FEATURE_ATS1A, AARCH64_NUM_FEATURES }; =20 @@ -245,7 +247,8 @@ enum aarch64_feature_bit { | AARCH64_FEATBIT (X, RASv2) \ | AARCH64_FEATBIT (X, SCTLR2) \ | AARCH64_FEATBIT (X, FGT2) \ - | AARCH64_FEATBIT (X, PFAR)) + | AARCH64_FEATBIT (X, PFAR) \ + | AARCH64_FEATBIT (X, ATS1A)) =20 #define AARCH64_ARCH_V9A_FEATURES(X) (AARCH64_FEATBIT (X, V9A) \ | AARCH64_FEATBIT (X, F16) \ diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index e4b3522c02f..4d84071ba8c 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -4810,6 +4810,9 @@ const aarch64_sys_ins_reg aarch64_sys_regs_at[] =3D { "s1e3w", CPENS (6, C7, C8, 1), F_HASXT }, { "s1e1rp", CPENS (0, C7, C9, 0), F_HASXT | F_ARCHEXT }, { "s1e1wp", CPENS (0, C7, C9, 1), F_HASXT | F_ARCHEXT }, + { "s1e1a", CPENS (0, C7, C9, 2), F_HASXT | F_ARCHEXT }, + { "s1e2a", CPENS (4, C7, C9, 2), F_HASXT | F_ARCHEXT }, + { "s1e3a", CPENS (6, C7, C9, 2), F_HASXT | F_ARCHEXT }, { 0, CPENS(0,0,0,0), 0 } }; =20 @@ -5041,6 +5044,12 @@ aarch64_sys_ins_reg_supported_p (const aarch64_featu= re_set features, && AARCH64_CPU_HAS_FEATURE (features, THE)) return true; =20 + if ((reg_value =3D=3D CPENS (0, C7, C9, 2) + || reg_value =3D=3D CPENS (4, C7, C9, 2) + || reg_value =3D=3D CPENS (6, C7, C9, 2)) + && AARCH64_CPU_HAS_FEATURE (features, ATS1A)) + return true; + return false; }