From: YunQiang Su <syq@sourceware.org>
To: bfd-cvs@sourceware.org
Subject: [binutils-gdb/binutils-2_41-branch] Gold/MIPS: Add targ_extra_size=64 for mips32 triples
Date: Tue, 21 Nov 2023 05:03:44 +0000 (GMT) [thread overview]
Message-ID: <20231121050344.4237A3858D37@sourceware.org> (raw)
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=eb49941e7e16bfcd71bd76544c84bf347b03e64f
commit eb49941e7e16bfcd71bd76544c84bf347b03e64f
Author: YunQiang Su <yunqiang.su@cipunited.com>
Date: Tue Nov 21 12:57:15 2023 +0800
Gold/MIPS: Add targ_extra_size=64 for mips32 triples
Backport commit: 619a8a364d6cdc43d6677f86369aa2b5d1a1cc0f
Diff:
---
gold/ChangeLog | 4 ++++
gold/configure.tgt | 2 ++
2 files changed, 6 insertions(+)
diff --git a/gold/ChangeLog b/gold/ChangeLog
index 3b09989d32d..4288254a68c 100644
--- a/gold/ChangeLog
+++ b/gold/ChangeLog
@@ -1,3 +1,7 @@
+2023-11-21 YunQiang Su <yunqiang.su@cipunited.com>
+
+ * configure.tgt (mips targets): Set targ_extra_size=64.
+
2023-11-21 YunQiang Su <yunqiang.su@cipunited.com>
* configure.tgt (mips targets): Set targ_machine to EM_MIPS for
diff --git a/gold/configure.tgt b/gold/configure.tgt
index 751c8fd06c6..836727f67de 100644
--- a/gold/configure.tgt
+++ b/gold/configure.tgt
@@ -157,6 +157,7 @@ mips*el*-*-*|mips*le*-*-*)
targ_obj=mips
targ_machine=EM_MIPS
targ_size=32
+ targ_extra_size=64
targ_big_endian=false
targ_extra_big_endian=true
;;
@@ -164,6 +165,7 @@ mips*-*-*)
targ_obj=mips
targ_machine=EM_MIPS
targ_size=32
+ targ_extra_size=64
targ_big_endian=true
targ_extra_big_endian=false
;;
reply other threads:[~2023-11-21 5:03 UTC|newest]
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