From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7803) id 05CED3857BAA; Thu, 23 Nov 2023 02:09:04 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 05CED3857BAA Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Nelson Chu To: bfd-cvs@sourceware.org Subject: [binutils-gdb] RISC-V: Add load/store segment instructions for T-Head VECTOR vendor extension X-Act-Checkin: binutils-gdb X-Git-Author: Jin Ma X-Git-Refname: refs/heads/master X-Git-Oldrev: 0bd0e6522a8763828d8ff6e5886ebd7fd14141e0 X-Git-Newrev: 763c4daa35a9f98533d91309917ae70d51893064 Message-Id: <20231123020904.05CED3857BAA@sourceware.org> Date: Thu, 23 Nov 2023 02:09:04 +0000 (GMT) X-BeenThere: binutils-cvs@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 23 Nov 2023 02:09:04 -0000 https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3D763c4daa35a9= f98533d91309917ae70d51893064 commit 763c4daa35a9f98533d91309917ae70d51893064 Author: Jin Ma Date: Sat Nov 18 15:05:31 2023 +0800 RISC-V: Add load/store segment instructions for T-Head VECTOR vendor ex= tension =20 T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. =20 This patch adds provides load/store segment instructions for T-Head VEC= TOR vendor extension, which same as the "Zvlsseg" extension in RVI 0.71 vec= tor extension, but belongs to the "XTheadVector" extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). =20 [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 =20 Co-developed-by: Lifang Xia Co-developed-by: Christoph M=C3=BCllner =20 gas/ChangeLog: =20 * testsuite/gas/riscv/x-thead-vector.d: Add test. * testsuite/gas/riscv/x-thead-vector.s: Likewise. =20 include/ChangeLog: =20 * opcode/riscv-opc.h (MATCH_TH_VLSEG2BV): New. =20 opcodes/ChangeLog: =20 * riscv-opc.c: Likewise. Diff: --- gas/testsuite/gas/riscv/x-thead-vector.d | 840 +++++++++++++++++++++++++++= +++ gas/testsuite/gas/riscv/x-thead-vector.s | 868 +++++++++++++++++++++++++++= ++++ include/opcode/riscv-opc.h | 169 ++++++ opcodes/riscv-opc.c | 280 ++++++++++ 4 files changed, 2157 insertions(+) diff --git a/gas/testsuite/gas/riscv/x-thead-vector.d b/gas/testsuite/gas/r= iscv/x-thead-vector.d index d7cb1e1a457..90ea839457a 100644 --- a/gas/testsuite/gas/riscv/x-thead-vector.d +++ b/gas/testsuite/gas/riscv/x-thead-vector.d @@ -142,3 +142,843 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+03057207[ ]+th.vleff.v[ ]+v4,\(a0\) [ ]+[0-9a-f]+:[ ]+03057207[ ]+th.vleff.v[ ]+v4,\(a0\) [ ]+[0-9a-f]+:[ ]+01057207[ ]+th.vleff.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+32050207[ ]+th.vlseg2b.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+32050207[ ]+th.vlseg2b.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+30050207[ ]+th.vlseg2b.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+32055207[ ]+th.vlseg2h.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+32055207[ 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index c65e9e8790c..d356c016c2f 100644 --- a/gas/testsuite/gas/riscv/x-thead-vector.s +++ b/gas/testsuite/gas/riscv/x-thead-vector.s @@ -137,3 +137,871 @@ th.vleff.v v4, (a0) th.vleff.v v4, 0(a0) th.vleff.v v4, (a0), v0.t + + th.vlseg2b.v v4, (a0) + th.vlseg2b.v v4, 0(a0) + th.vlseg2b.v v4, (a0), v0.t + th.vlseg2h.v v4, (a0) + th.vlseg2h.v v4, 0(a0) + th.vlseg2h.v v4, (a0), v0.t + th.vlseg2w.v v4, (a0) + th.vlseg2w.v v4, 0(a0) + th.vlseg2w.v v4, (a0), v0.t + th.vlseg2bu.v v4, (a0) + th.vlseg2bu.v v4, 0(a0) + th.vlseg2bu.v v4, (a0), v0.t + th.vlseg2hu.v v4, (a0) + th.vlseg2hu.v v4, 0(a0) + th.vlseg2hu.v v4, (a0), v0.t + th.vlseg2wu.v v4, (a0) + th.vlseg2wu.v v4, 0(a0) + th.vlseg2wu.v v4, (a0), v0.t + th.vlseg2e.v v4, (a0) + th.vlseg2e.v v4, 0(a0) + th.vlseg2e.v v4, (a0), v0.t + th.vsseg2b.v v4, (a0) + th.vsseg2b.v v4, 0(a0) + th.vsseg2b.v v4, (a0), v0.t + th.vsseg2h.v v4, (a0) + th.vsseg2h.v v4, 0(a0) + th.vsseg2h.v v4, (a0), v0.t + th.vsseg2w.v v4, (a0) + th.vsseg2w.v v4, 0(a0) + th.vsseg2w.v v4, (a0), v0.t + th.vsseg2e.v v4, (a0) + th.vsseg2e.v v4, 0(a0) + th.vsseg2e.v v4, (a0), v0.t + + th.vlseg3b.v v4, (a0) + th.vlseg3b.v v4, 0(a0) + th.vlseg3b.v v4, (a0), v0.t + th.vlseg3h.v v4, (a0) + th.vlseg3h.v v4, 0(a0) + th.vlseg3h.v v4, (a0), v0.t + th.vlseg3w.v v4, (a0) + th.vlseg3w.v v4, 0(a0) + th.vlseg3w.v v4, (a0), v0.t + th.vlseg3bu.v v4, (a0) + th.vlseg3bu.v v4, 0(a0) + th.vlseg3bu.v v4, (a0), v0.t + th.vlseg3hu.v v4, (a0) + th.vlseg3hu.v v4, 0(a0) + th.vlseg3hu.v v4, (a0), v0.t + th.vlseg3wu.v v4, (a0) + th.vlseg3wu.v v4, 0(a0) + th.vlseg3wu.v v4, (a0), v0.t + th.vlseg3e.v v4, (a0) + th.vlseg3e.v v4, 0(a0) + th.vlseg3e.v v4, (a0), v0.t + th.vsseg3b.v v4, (a0) + th.vsseg3b.v v4, 0(a0) + th.vsseg3b.v v4, (a0), v0.t + th.vsseg3h.v v4, (a0) + th.vsseg3h.v v4, 0(a0) + th.vsseg3h.v v4, (a0), v0.t + th.vsseg3w.v v4, (a0) + th.vsseg3w.v v4, 0(a0) + th.vsseg3w.v v4, (a0), v0.t + th.vsseg3e.v v4, (a0) + th.vsseg3e.v v4, 0(a0) + th.vsseg3e.v v4, (a0), v0.t + + th.vlseg4b.v v4, (a0) + th.vlseg4b.v v4, 0(a0) + th.vlseg4b.v v4, (a0), v0.t + th.vlseg4h.v v4, (a0) + th.vlseg4h.v v4, 0(a0) + th.vlseg4h.v v4, (a0), v0.t + th.vlseg4w.v v4, (a0) + th.vlseg4w.v v4, 0(a0) + th.vlseg4w.v v4, (a0), v0.t + th.vlseg4bu.v v4, (a0) + th.vlseg4bu.v v4, 0(a0) + th.vlseg4bu.v v4, (a0), v0.t + th.vlseg4hu.v v4, (a0) + th.vlseg4hu.v v4, 0(a0) + th.vlseg4hu.v v4, (a0), v0.t + th.vlseg4wu.v v4, (a0) + th.vlseg4wu.v v4, 0(a0) + th.vlseg4wu.v v4, (a0), v0.t + th.vlseg4e.v v4, (a0) + th.vlseg4e.v v4, 0(a0) + th.vlseg4e.v v4, (a0), v0.t + th.vsseg4b.v v4, (a0) + th.vsseg4b.v v4, 0(a0) + th.vsseg4b.v v4, (a0), v0.t + th.vsseg4h.v v4, (a0) + th.vsseg4h.v v4, 0(a0) + th.vsseg4h.v v4, (a0), v0.t + th.vsseg4w.v v4, (a0) + th.vsseg4w.v v4, 0(a0) + th.vsseg4w.v v4, (a0), v0.t + th.vsseg4e.v v4, (a0) + th.vsseg4e.v v4, 0(a0) + th.vsseg4e.v v4, (a0), v0.t + + th.vlseg5b.v v4, (a0) + th.vlseg5b.v v4, 0(a0) + th.vlseg5b.v v4, (a0), v0.t + th.vlseg5h.v v4, (a0) + th.vlseg5h.v v4, 0(a0) + th.vlseg5h.v v4, (a0), v0.t + th.vlseg5w.v v4, (a0) + th.vlseg5w.v v4, 0(a0) + th.vlseg5w.v v4, (a0), v0.t + th.vlseg5bu.v v4, (a0) + th.vlseg5bu.v v4, 0(a0) + th.vlseg5bu.v v4, (a0), v0.t + th.vlseg5hu.v v4, (a0) + th.vlseg5hu.v v4, 0(a0) + th.vlseg5hu.v v4, (a0), v0.t + th.vlseg5wu.v v4, (a0) + th.vlseg5wu.v v4, 0(a0) + th.vlseg5wu.v v4, (a0), v0.t + th.vlseg5e.v v4, (a0) + th.vlseg5e.v v4, 0(a0) + th.vlseg5e.v v4, (a0), v0.t + th.vsseg5b.v v4, (a0) + th.vsseg5b.v v4, 0(a0) + th.vsseg5b.v v4, (a0), v0.t + th.vsseg5h.v v4, (a0) + th.vsseg5h.v v4, 0(a0) + th.vsseg5h.v v4, (a0), v0.t + th.vsseg5w.v v4, (a0) + th.vsseg5w.v v4, 0(a0) + th.vsseg5w.v v4, (a0), v0.t + th.vsseg5e.v v4, (a0) + th.vsseg5e.v v4, 0(a0) + th.vsseg5e.v v4, (a0), v0.t + + th.vlseg6b.v v4, (a0) + th.vlseg6b.v v4, 0(a0) + th.vlseg6b.v v4, (a0), v0.t + th.vlseg6h.v v4, (a0) + th.vlseg6h.v v4, 0(a0) + th.vlseg6h.v v4, (a0), v0.t + th.vlseg6w.v v4, (a0) + th.vlseg6w.v v4, 0(a0) + th.vlseg6w.v v4, (a0), v0.t + th.vlseg6bu.v v4, (a0) + th.vlseg6bu.v v4, 0(a0) + th.vlseg6bu.v v4, (a0), v0.t + th.vlseg6hu.v v4, (a0) + th.vlseg6hu.v v4, 0(a0) + th.vlseg6hu.v v4, (a0), v0.t + th.vlseg6wu.v v4, (a0) + th.vlseg6wu.v v4, 0(a0) + th.vlseg6wu.v v4, (a0), v0.t + th.vlseg6e.v v4, (a0) + th.vlseg6e.v v4, 0(a0) + th.vlseg6e.v v4, (a0), v0.t + th.vsseg6b.v v4, (a0) + th.vsseg6b.v v4, 0(a0) + th.vsseg6b.v v4, (a0), v0.t + th.vsseg6h.v v4, (a0) + th.vsseg6h.v v4, 0(a0) + th.vsseg6h.v v4, (a0), v0.t + th.vsseg6w.v v4, (a0) + th.vsseg6w.v v4, 0(a0) + th.vsseg6w.v v4, (a0), v0.t + th.vsseg6e.v v4, (a0) + th.vsseg6e.v v4, 0(a0) + th.vsseg6e.v v4, (a0), v0.t + + th.vlseg7b.v v4, (a0) + th.vlseg7b.v v4, 0(a0) + th.vlseg7b.v v4, (a0), v0.t + th.vlseg7h.v v4, (a0) + th.vlseg7h.v v4, 0(a0) + th.vlseg7h.v v4, (a0), v0.t + th.vlseg7w.v v4, (a0) + th.vlseg7w.v v4, 0(a0) + th.vlseg7w.v v4, (a0), v0.t + th.vlseg7bu.v v4, (a0) + th.vlseg7bu.v v4, 0(a0) + th.vlseg7bu.v v4, (a0), v0.t + th.vlseg7hu.v v4, (a0) + th.vlseg7hu.v v4, 0(a0) + th.vlseg7hu.v v4, (a0), v0.t + th.vlseg7wu.v v4, (a0) + th.vlseg7wu.v v4, 0(a0) + th.vlseg7wu.v v4, (a0), v0.t + th.vlseg7e.v v4, (a0) + th.vlseg7e.v v4, 0(a0) + th.vlseg7e.v v4, (a0), v0.t + th.vsseg7b.v v4, (a0) + th.vsseg7b.v v4, 0(a0) + th.vsseg7b.v v4, (a0), v0.t + th.vsseg7h.v v4, (a0) + th.vsseg7h.v v4, 0(a0) + th.vsseg7h.v v4, (a0), v0.t + th.vsseg7w.v v4, (a0) + th.vsseg7w.v v4, 0(a0) + th.vsseg7w.v v4, (a0), v0.t + th.vsseg7e.v v4, (a0) + th.vsseg7e.v v4, 0(a0) + th.vsseg7e.v v4, (a0), v0.t + + th.vlseg8b.v v4, (a0) + th.vlseg8b.v v4, 0(a0) + th.vlseg8b.v v4, (a0), v0.t + th.vlseg8h.v v4, (a0) + th.vlseg8h.v v4, 0(a0) + th.vlseg8h.v v4, (a0), v0.t + th.vlseg8w.v v4, (a0) + th.vlseg8w.v v4, 0(a0) + th.vlseg8w.v v4, (a0), v0.t + th.vlseg8bu.v v4, (a0) + th.vlseg8bu.v v4, 0(a0) + th.vlseg8bu.v v4, (a0), v0.t + th.vlseg8hu.v v4, (a0) + th.vlseg8hu.v v4, 0(a0) + th.vlseg8hu.v v4, (a0), v0.t + th.vlseg8wu.v v4, (a0) + th.vlseg8wu.v v4, 0(a0) + th.vlseg8wu.v v4, (a0), v0.t + th.vlseg8e.v v4, (a0) + th.vlseg8e.v v4, 0(a0) + th.vlseg8e.v v4, (a0), v0.t + th.vsseg8b.v v4, (a0) + th.vsseg8b.v v4, 0(a0) + th.vsseg8b.v v4, (a0), v0.t + th.vsseg8h.v v4, (a0) + th.vsseg8h.v v4, 0(a0) + th.vsseg8h.v v4, (a0), v0.t + th.vsseg8w.v v4, (a0) + th.vsseg8w.v v4, 0(a0) + th.vsseg8w.v v4, (a0), v0.t + th.vsseg8e.v v4, (a0) + th.vsseg8e.v v4, 0(a0) + th.vsseg8e.v v4, (a0), v0.t + + th.vlsseg2b.v v4, (a0), a1 + th.vlsseg2b.v v4, 0(a0), a1 + th.vlsseg2b.v v4, (a0), a1, v0.t + th.vlsseg2h.v v4, (a0), a1 + th.vlsseg2h.v v4, 0(a0), a1 + th.vlsseg2h.v v4, (a0), a1, v0.t + th.vlsseg2w.v v4, (a0), a1 + th.vlsseg2w.v v4, 0(a0), a1 + th.vlsseg2w.v v4, (a0), a1, v0.t + th.vlsseg2bu.v v4, (a0), a1 + th.vlsseg2bu.v v4, 0(a0), a1 + th.vlsseg2bu.v v4, (a0), a1, v0.t + th.vlsseg2hu.v v4, (a0), a1 + th.vlsseg2hu.v v4, 0(a0), a1 + th.vlsseg2hu.v v4, (a0), a1, v0.t + th.vlsseg2wu.v v4, (a0), a1 + th.vlsseg2wu.v v4, 0(a0), a1 + th.vlsseg2wu.v v4, (a0), a1, v0.t + th.vlsseg2e.v v4, (a0), a1 + th.vlsseg2e.v v4, 0(a0), a1 + th.vlsseg2e.v v4, (a0), a1, v0.t + th.vssseg2b.v v4, (a0), a1 + th.vssseg2b.v v4, 0(a0), a1 + th.vssseg2b.v v4, (a0), a1, v0.t + th.vssseg2h.v v4, (a0), a1 + th.vssseg2h.v v4, 0(a0), a1 + th.vssseg2h.v v4, (a0), a1, v0.t + th.vssseg2w.v v4, (a0), a1 + th.vssseg2w.v v4, 0(a0), a1 + th.vssseg2w.v v4, (a0), a1, v0.t + th.vssseg2e.v v4, (a0), a1 + th.vssseg2e.v v4, 0(a0), a1 + th.vssseg2e.v v4, (a0), a1, v0.t + + th.vlsseg3b.v v4, (a0), a1 + th.vlsseg3b.v v4, 0(a0), a1 + th.vlsseg3b.v v4, (a0), a1, v0.t + th.vlsseg3h.v v4, (a0), a1 + th.vlsseg3h.v v4, 0(a0), a1 + th.vlsseg3h.v v4, (a0), a1, v0.t + th.vlsseg3w.v v4, (a0), a1 + th.vlsseg3w.v v4, 0(a0), a1 + th.vlsseg3w.v v4, (a0), a1, v0.t + th.vlsseg3bu.v v4, (a0), a1 + th.vlsseg3bu.v v4, 0(a0), a1 + th.vlsseg3bu.v v4, (a0), a1, v0.t + th.vlsseg3hu.v v4, (a0), a1 + th.vlsseg3hu.v v4, 0(a0), a1 + th.vlsseg3hu.v v4, (a0), a1, v0.t + th.vlsseg3wu.v v4, (a0), a1 + th.vlsseg3wu.v v4, 0(a0), a1 + th.vlsseg3wu.v v4, (a0), a1, v0.t + th.vlsseg3e.v v4, (a0), a1 + th.vlsseg3e.v v4, 0(a0), a1 + th.vlsseg3e.v v4, (a0), a1, v0.t + th.vssseg3b.v v4, (a0), a1 + th.vssseg3b.v v4, 0(a0), a1 + th.vssseg3b.v v4, (a0), a1, v0.t + th.vssseg3h.v v4, (a0), a1 + th.vssseg3h.v v4, 0(a0), a1 + th.vssseg3h.v v4, (a0), a1, v0.t + th.vssseg3w.v v4, (a0), a1 + th.vssseg3w.v v4, 0(a0), a1 + th.vssseg3w.v v4, (a0), a1, v0.t + th.vssseg3e.v v4, (a0), a1 + th.vssseg3e.v v4, 0(a0), a1 + th.vssseg3e.v v4, (a0), a1, v0.t + + th.vlsseg4b.v v4, (a0), a1 + th.vlsseg4b.v v4, 0(a0), a1 + th.vlsseg4b.v v4, (a0), a1, v0.t + th.vlsseg4h.v v4, (a0), a1 + th.vlsseg4h.v v4, 0(a0), a1 + th.vlsseg4h.v v4, (a0), a1, v0.t + th.vlsseg4w.v v4, (a0), a1 + th.vlsseg4w.v v4, 0(a0), a1 + th.vlsseg4w.v v4, (a0), a1, v0.t + th.vlsseg4bu.v v4, (a0), a1 + th.vlsseg4bu.v v4, 0(a0), a1 + th.vlsseg4bu.v v4, (a0), a1, v0.t + th.vlsseg4hu.v v4, (a0), a1 + th.vlsseg4hu.v v4, 0(a0), a1 + th.vlsseg4hu.v v4, (a0), a1, v0.t + th.vlsseg4wu.v v4, (a0), a1 + th.vlsseg4wu.v v4, 0(a0), a1 + th.vlsseg4wu.v v4, (a0), a1, v0.t + th.vlsseg4e.v v4, (a0), a1 + th.vlsseg4e.v v4, 0(a0), a1 + th.vlsseg4e.v v4, (a0), a1, v0.t + th.vssseg4b.v v4, (a0), a1 + th.vssseg4b.v v4, 0(a0), a1 + th.vssseg4b.v v4, (a0), a1, v0.t + th.vssseg4h.v v4, (a0), a1 + th.vssseg4h.v v4, 0(a0), a1 + th.vssseg4h.v v4, (a0), a1, v0.t + th.vssseg4w.v v4, (a0), a1 + th.vssseg4w.v v4, 0(a0), a1 + th.vssseg4w.v v4, (a0), a1, v0.t + th.vssseg4e.v v4, (a0), a1 + th.vssseg4e.v v4, 0(a0), a1 + th.vssseg4e.v v4, (a0), a1, v0.t + + th.vlsseg5b.v v4, (a0), a1 + th.vlsseg5b.v v4, 0(a0), a1 + th.vlsseg5b.v v4, (a0), a1, v0.t + th.vlsseg5h.v v4, (a0), a1 + th.vlsseg5h.v v4, 0(a0), a1 + th.vlsseg5h.v v4, (a0), a1, v0.t + th.vlsseg5w.v v4, (a0), a1 + th.vlsseg5w.v v4, 0(a0), a1 + th.vlsseg5w.v v4, (a0), a1, v0.t + th.vlsseg5bu.v v4, (a0), a1 + th.vlsseg5bu.v v4, 0(a0), a1 + th.vlsseg5bu.v v4, (a0), a1, v0.t + th.vlsseg5hu.v v4, (a0), a1 + th.vlsseg5hu.v v4, 0(a0), a1 + th.vlsseg5hu.v v4, (a0), a1, v0.t + th.vlsseg5wu.v v4, (a0), a1 + th.vlsseg5wu.v v4, 0(a0), a1 + th.vlsseg5wu.v v4, (a0), a1, v0.t + th.vlsseg5e.v v4, (a0), a1 + th.vlsseg5e.v v4, 0(a0), a1 + th.vlsseg5e.v v4, (a0), a1, v0.t + th.vssseg5b.v v4, (a0), a1 + th.vssseg5b.v v4, 0(a0), a1 + th.vssseg5b.v v4, (a0), a1, v0.t + th.vssseg5h.v v4, (a0), a1 + th.vssseg5h.v v4, 0(a0), a1 + th.vssseg5h.v v4, (a0), a1, v0.t + th.vssseg5w.v v4, (a0), a1 + th.vssseg5w.v v4, 0(a0), a1 + th.vssseg5w.v v4, (a0), a1, v0.t + th.vssseg5e.v v4, (a0), a1 + th.vssseg5e.v v4, 0(a0), a1 + th.vssseg5e.v v4, (a0), a1, v0.t + + th.vlsseg6b.v v4, (a0), a1 + th.vlsseg6b.v v4, 0(a0), a1 + th.vlsseg6b.v v4, (a0), a1, v0.t + th.vlsseg6h.v v4, (a0), a1 + th.vlsseg6h.v v4, 0(a0), a1 + th.vlsseg6h.v v4, (a0), a1, v0.t + th.vlsseg6w.v v4, (a0), a1 + th.vlsseg6w.v v4, 0(a0), a1 + th.vlsseg6w.v v4, (a0), a1, v0.t + th.vlsseg6bu.v v4, (a0), a1 + th.vlsseg6bu.v v4, 0(a0), a1 + th.vlsseg6bu.v v4, (a0), a1, v0.t + th.vlsseg6hu.v v4, (a0), a1 + th.vlsseg6hu.v v4, 0(a0), a1 + th.vlsseg6hu.v v4, (a0), a1, v0.t + th.vlsseg6wu.v v4, (a0), a1 + th.vlsseg6wu.v v4, 0(a0), a1 + th.vlsseg6wu.v v4, (a0), a1, v0.t + th.vlsseg6e.v v4, (a0), a1 + th.vlsseg6e.v v4, 0(a0), a1 + th.vlsseg6e.v v4, (a0), a1, v0.t + th.vssseg6b.v v4, (a0), a1 + th.vssseg6b.v v4, 0(a0), a1 + th.vssseg6b.v v4, (a0), a1, v0.t + th.vssseg6h.v v4, (a0), a1 + th.vssseg6h.v v4, 0(a0), a1 + th.vssseg6h.v v4, (a0), a1, v0.t + th.vssseg6w.v v4, (a0), a1 + th.vssseg6w.v v4, 0(a0), a1 + th.vssseg6w.v v4, (a0), a1, v0.t + th.vssseg6e.v v4, (a0), a1 + th.vssseg6e.v v4, 0(a0), a1 + th.vssseg6e.v v4, (a0), a1, v0.t + + th.vlsseg7b.v v4, (a0), a1 + th.vlsseg7b.v v4, 0(a0), a1 + th.vlsseg7b.v v4, (a0), a1, v0.t + th.vlsseg7h.v v4, (a0), a1 + th.vlsseg7h.v v4, 0(a0), a1 + th.vlsseg7h.v v4, (a0), a1, v0.t + th.vlsseg7w.v v4, (a0), a1 + th.vlsseg7w.v v4, 0(a0), a1 + th.vlsseg7w.v v4, (a0), a1, v0.t + th.vlsseg7bu.v v4, (a0), a1 + th.vlsseg7bu.v v4, 0(a0), a1 + th.vlsseg7bu.v v4, (a0), a1, v0.t + th.vlsseg7hu.v v4, (a0), a1 + th.vlsseg7hu.v v4, 0(a0), a1 + th.vlsseg7hu.v v4, (a0), a1, v0.t + th.vlsseg7wu.v v4, (a0), a1 + th.vlsseg7wu.v v4, 0(a0), a1 + th.vlsseg7wu.v v4, (a0), a1, v0.t + th.vlsseg7e.v v4, (a0), a1 + th.vlsseg7e.v v4, 0(a0), a1 + th.vlsseg7e.v v4, (a0), a1, v0.t + th.vssseg7b.v v4, (a0), a1 + th.vssseg7b.v v4, 0(a0), a1 + th.vssseg7b.v v4, (a0), a1, v0.t + th.vssseg7h.v v4, (a0), a1 + th.vssseg7h.v v4, 0(a0), a1 + th.vssseg7h.v v4, (a0), a1, v0.t + th.vssseg7w.v v4, (a0), a1 + th.vssseg7w.v v4, 0(a0), a1 + th.vssseg7w.v v4, (a0), a1, v0.t + th.vssseg7e.v v4, (a0), a1 + th.vssseg7e.v v4, 0(a0), a1 + th.vssseg7e.v v4, (a0), a1, v0.t + + th.vlsseg8b.v v4, (a0), a1 + th.vlsseg8b.v v4, 0(a0), a1 + th.vlsseg8b.v v4, (a0), a1, v0.t + th.vlsseg8h.v v4, (a0), a1 + th.vlsseg8h.v v4, 0(a0), a1 + th.vlsseg8h.v v4, (a0), a1, v0.t + th.vlsseg8w.v v4, (a0), a1 + th.vlsseg8w.v v4, 0(a0), a1 + th.vlsseg8w.v v4, (a0), a1, v0.t + th.vlsseg8bu.v v4, (a0), a1 + th.vlsseg8bu.v v4, 0(a0), a1 + th.vlsseg8bu.v v4, (a0), a1, v0.t + th.vlsseg8hu.v v4, (a0), a1 + th.vlsseg8hu.v v4, 0(a0), a1 + th.vlsseg8hu.v v4, (a0), a1, v0.t + th.vlsseg8wu.v v4, (a0), a1 + th.vlsseg8wu.v v4, 0(a0), a1 + th.vlsseg8wu.v v4, (a0), a1, v0.t + th.vlsseg8e.v v4, (a0), a1 + th.vlsseg8e.v v4, 0(a0), a1 + th.vlsseg8e.v v4, (a0), a1, v0.t + th.vssseg8b.v v4, (a0), a1 + th.vssseg8b.v v4, 0(a0), a1 + th.vssseg8b.v v4, (a0), a1, v0.t + th.vssseg8h.v v4, (a0), a1 + th.vssseg8h.v v4, 0(a0), a1 + th.vssseg8h.v v4, (a0), a1, v0.t + th.vssseg8w.v v4, (a0), a1 + th.vssseg8w.v v4, 0(a0), a1 + th.vssseg8w.v v4, (a0), a1, v0.t + th.vssseg8e.v v4, (a0), a1 + th.vssseg8e.v v4, 0(a0), a1 + th.vssseg8e.v v4, (a0), a1, v0.t + + th.vlxseg2b.v v4, (a0), v12 + th.vlxseg2b.v v4, 0(a0), v12 + th.vlxseg2b.v v4, (a0), v12, v0.t + th.vlxseg2h.v v4, (a0), v12 + th.vlxseg2h.v v4, 0(a0), v12 + th.vlxseg2h.v v4, (a0), v12, v0.t + th.vlxseg2w.v v4, (a0), v12 + th.vlxseg2w.v v4, 0(a0), v12 + th.vlxseg2w.v v4, (a0), v12, v0.t + th.vlxseg2bu.v v4, (a0), v12 + th.vlxseg2bu.v v4, 0(a0), v12 + th.vlxseg2bu.v v4, (a0), v12, v0.t + th.vlxseg2hu.v v4, (a0), v12 + th.vlxseg2hu.v v4, 0(a0), v12 + th.vlxseg2hu.v v4, (a0), v12, v0.t + th.vlxseg2wu.v v4, (a0), v12 + th.vlxseg2wu.v v4, 0(a0), v12 + th.vlxseg2wu.v v4, (a0), v12, v0.t + th.vlxseg2e.v v4, (a0), v12 + th.vlxseg2e.v v4, 0(a0), v12 + th.vlxseg2e.v v4, (a0), v12, v0.t + th.vsxseg2b.v v4, (a0), v12 + th.vsxseg2b.v v4, 0(a0), v12 + th.vsxseg2b.v v4, (a0), v12, v0.t + th.vsxseg2h.v v4, (a0), v12 + th.vsxseg2h.v v4, 0(a0), v12 + th.vsxseg2h.v v4, (a0), v12, v0.t + th.vsxseg2w.v v4, (a0), v12 + th.vsxseg2w.v v4, 0(a0), v12 + th.vsxseg2w.v v4, (a0), v12, v0.t + th.vsxseg2e.v v4, (a0), v12 + th.vsxseg2e.v v4, 0(a0), v12 + th.vsxseg2e.v v4, (a0), v12, v0.t + + th.vlxseg3b.v v4, (a0), v12 + th.vlxseg3b.v v4, 0(a0), v12 + th.vlxseg3b.v v4, (a0), v12, v0.t + th.vlxseg3h.v v4, (a0), v12 + th.vlxseg3h.v v4, 0(a0), v12 + th.vlxseg3h.v v4, (a0), v12, v0.t + th.vlxseg3w.v v4, (a0), v12 + th.vlxseg3w.v v4, 0(a0), v12 + th.vlxseg3w.v v4, (a0), v12, v0.t + th.vlxseg3bu.v v4, (a0), v12 + th.vlxseg3bu.v v4, 0(a0), v12 + th.vlxseg3bu.v v4, (a0), v12, v0.t + th.vlxseg3hu.v v4, (a0), v12 + th.vlxseg3hu.v v4, 0(a0), v12 + th.vlxseg3hu.v v4, (a0), v12, v0.t + th.vlxseg3wu.v v4, (a0), v12 + th.vlxseg3wu.v v4, 0(a0), v12 + th.vlxseg3wu.v v4, (a0), v12, v0.t + th.vlxseg3e.v v4, (a0), v12 + th.vlxseg3e.v v4, 0(a0), v12 + th.vlxseg3e.v v4, (a0), v12, v0.t + th.vsxseg3b.v v4, (a0), v12 + th.vsxseg3b.v v4, 0(a0), v12 + th.vsxseg3b.v v4, (a0), v12, v0.t + th.vsxseg3h.v v4, (a0), v12 + th.vsxseg3h.v v4, 0(a0), v12 + th.vsxseg3h.v v4, (a0), v12, v0.t + th.vsxseg3w.v v4, (a0), v12 + th.vsxseg3w.v v4, 0(a0), v12 + th.vsxseg3w.v v4, (a0), v12, v0.t + th.vsxseg3e.v v4, (a0), v12 + th.vsxseg3e.v v4, 0(a0), v12 + th.vsxseg3e.v v4, (a0), v12, v0.t + + th.vlxseg4b.v v4, (a0), v12 + th.vlxseg4b.v v4, 0(a0), v12 + th.vlxseg4b.v v4, (a0), v12, v0.t + th.vlxseg4h.v v4, (a0), v12 + th.vlxseg4h.v v4, 0(a0), v12 + th.vlxseg4h.v v4, (a0), v12, v0.t + th.vlxseg4w.v v4, (a0), v12 + th.vlxseg4w.v v4, 0(a0), v12 + th.vlxseg4w.v v4, (a0), v12, v0.t + th.vlxseg4bu.v v4, (a0), v12 + th.vlxseg4bu.v v4, 0(a0), v12 + th.vlxseg4bu.v v4, (a0), v12, v0.t + th.vlxseg4hu.v v4, (a0), v12 + th.vlxseg4hu.v v4, 0(a0), v12 + th.vlxseg4hu.v v4, (a0), v12, v0.t + th.vlxseg4wu.v v4, (a0), v12 + th.vlxseg4wu.v v4, 0(a0), v12 + th.vlxseg4wu.v v4, (a0), v12, v0.t + th.vlxseg4e.v v4, (a0), v12 + th.vlxseg4e.v v4, 0(a0), v12 + th.vlxseg4e.v v4, (a0), v12, v0.t + th.vsxseg4b.v v4, (a0), v12 + th.vsxseg4b.v v4, 0(a0), v12 + th.vsxseg4b.v v4, (a0), v12, v0.t + th.vsxseg4h.v v4, (a0), v12 + th.vsxseg4h.v v4, 0(a0), v12 + th.vsxseg4h.v v4, (a0), v12, v0.t + th.vsxseg4w.v v4, (a0), v12 + th.vsxseg4w.v v4, 0(a0), v12 + th.vsxseg4w.v v4, (a0), v12, v0.t + th.vsxseg4e.v v4, (a0), v12 + th.vsxseg4e.v v4, 0(a0), v12 + th.vsxseg4e.v v4, (a0), v12, v0.t + + th.vlxseg5b.v v4, (a0), v12 + th.vlxseg5b.v v4, 0(a0), v12 + th.vlxseg5b.v v4, (a0), v12, v0.t + th.vlxseg5h.v v4, (a0), v12 + th.vlxseg5h.v v4, 0(a0), v12 + th.vlxseg5h.v v4, (a0), v12, v0.t + th.vlxseg5w.v v4, (a0), v12 + th.vlxseg5w.v v4, 0(a0), v12 + th.vlxseg5w.v v4, (a0), v12, v0.t + th.vlxseg5bu.v v4, (a0), v12 + th.vlxseg5bu.v v4, 0(a0), v12 + th.vlxseg5bu.v v4, (a0), v12, v0.t + th.vlxseg5hu.v v4, (a0), v12 + th.vlxseg5hu.v v4, 0(a0), v12 + th.vlxseg5hu.v v4, (a0), v12, v0.t + th.vlxseg5wu.v v4, (a0), v12 + th.vlxseg5wu.v v4, 0(a0), v12 + th.vlxseg5wu.v v4, (a0), v12, v0.t + th.vlxseg5e.v v4, (a0), v12 + th.vlxseg5e.v v4, 0(a0), v12 + th.vlxseg5e.v v4, (a0), v12, v0.t + th.vsxseg5b.v v4, (a0), v12 + th.vsxseg5b.v v4, 0(a0), v12 + th.vsxseg5b.v v4, (a0), v12, v0.t + th.vsxseg5h.v v4, (a0), v12 + th.vsxseg5h.v v4, 0(a0), v12 + th.vsxseg5h.v v4, (a0), v12, v0.t + th.vsxseg5w.v v4, (a0), v12 + th.vsxseg5w.v v4, 0(a0), v12 + th.vsxseg5w.v v4, (a0), v12, v0.t + th.vsxseg5e.v v4, (a0), v12 + th.vsxseg5e.v v4, 0(a0), v12 + th.vsxseg5e.v v4, (a0), v12, v0.t + + th.vlxseg6b.v v4, (a0), v12 + th.vlxseg6b.v v4, 0(a0), v12 + th.vlxseg6b.v v4, (a0), v12, v0.t + th.vlxseg6h.v v4, (a0), v12 + th.vlxseg6h.v v4, 0(a0), v12 + th.vlxseg6h.v v4, (a0), v12, v0.t + th.vlxseg6w.v v4, (a0), v12 + th.vlxseg6w.v v4, 0(a0), v12 + th.vlxseg6w.v v4, (a0), v12, v0.t + th.vlxseg6bu.v v4, (a0), v12 + th.vlxseg6bu.v v4, 0(a0), v12 + th.vlxseg6bu.v v4, (a0), v12, v0.t + th.vlxseg6hu.v v4, (a0), v12 + th.vlxseg6hu.v v4, 0(a0), v12 + th.vlxseg6hu.v v4, (a0), v12, v0.t + th.vlxseg6wu.v v4, (a0), v12 + th.vlxseg6wu.v v4, 0(a0), v12 + th.vlxseg6wu.v v4, (a0), v12, v0.t + th.vlxseg6e.v v4, (a0), v12 + th.vlxseg6e.v v4, 0(a0), v12 + th.vlxseg6e.v v4, (a0), v12, v0.t + th.vsxseg6b.v v4, (a0), v12 + th.vsxseg6b.v v4, 0(a0), v12 + th.vsxseg6b.v v4, (a0), v12, v0.t + th.vsxseg6h.v v4, (a0), v12 + th.vsxseg6h.v v4, 0(a0), v12 + th.vsxseg6h.v v4, (a0), v12, v0.t + th.vsxseg6w.v v4, (a0), v12 + th.vsxseg6w.v v4, 0(a0), v12 + th.vsxseg6w.v v4, (a0), v12, v0.t + th.vsxseg6e.v v4, (a0), v12 + th.vsxseg6e.v v4, 0(a0), v12 + th.vsxseg6e.v v4, (a0), v12, v0.t + + th.vlxseg7b.v v4, (a0), v12 + th.vlxseg7b.v v4, 0(a0), v12 + th.vlxseg7b.v v4, (a0), v12, v0.t + th.vlxseg7h.v v4, (a0), v12 + th.vlxseg7h.v v4, 0(a0), v12 + th.vlxseg7h.v v4, (a0), v12, v0.t + th.vlxseg7w.v v4, (a0), v12 + th.vlxseg7w.v v4, 0(a0), v12 + th.vlxseg7w.v v4, (a0), v12, v0.t + th.vlxseg7bu.v v4, (a0), v12 + th.vlxseg7bu.v v4, 0(a0), v12 + th.vlxseg7bu.v v4, (a0), v12, v0.t + th.vlxseg7hu.v v4, (a0), v12 + th.vlxseg7hu.v v4, 0(a0), v12 + th.vlxseg7hu.v v4, (a0), v12, v0.t + th.vlxseg7wu.v v4, (a0), v12 + th.vlxseg7wu.v v4, 0(a0), v12 + th.vlxseg7wu.v v4, (a0), v12, v0.t + th.vlxseg7e.v v4, (a0), v12 + th.vlxseg7e.v v4, 0(a0), v12 + th.vlxseg7e.v v4, (a0), v12, v0.t + th.vsxseg7b.v v4, (a0), v12 + th.vsxseg7b.v v4, 0(a0), v12 + th.vsxseg7b.v v4, (a0), v12, v0.t + th.vsxseg7h.v v4, (a0), v12 + th.vsxseg7h.v v4, 0(a0), v12 + th.vsxseg7h.v v4, (a0), v12, v0.t + th.vsxseg7w.v v4, (a0), v12 + th.vsxseg7w.v v4, 0(a0), v12 + th.vsxseg7w.v v4, (a0), v12, v0.t + th.vsxseg7e.v v4, (a0), v12 + th.vsxseg7e.v v4, 0(a0), v12 + th.vsxseg7e.v v4, (a0), v12, v0.t + + th.vlxseg8b.v v4, (a0), v12 + th.vlxseg8b.v v4, 0(a0), v12 + th.vlxseg8b.v v4, (a0), v12, v0.t + th.vlxseg8h.v v4, (a0), v12 + th.vlxseg8h.v v4, 0(a0), v12 + th.vlxseg8h.v v4, (a0), v12, v0.t + th.vlxseg8w.v v4, (a0), v12 + th.vlxseg8w.v v4, 0(a0), v12 + th.vlxseg8w.v v4, (a0), v12, v0.t + th.vlxseg8bu.v v4, (a0), v12 + th.vlxseg8bu.v v4, 0(a0), v12 + th.vlxseg8bu.v v4, (a0), v12, v0.t + th.vlxseg8hu.v v4, (a0), v12 + th.vlxseg8hu.v v4, 0(a0), v12 + th.vlxseg8hu.v v4, (a0), v12, v0.t + th.vlxseg8wu.v v4, (a0), v12 + th.vlxseg8wu.v v4, 0(a0), v12 + th.vlxseg8wu.v v4, (a0), v12, v0.t + th.vlxseg8e.v v4, (a0), v12 + th.vlxseg8e.v v4, 0(a0), v12 + th.vlxseg8e.v v4, (a0), v12, v0.t + th.vsxseg8b.v v4, (a0), v12 + th.vsxseg8b.v v4, 0(a0), v12 + th.vsxseg8b.v v4, (a0), v12, v0.t + th.vsxseg8h.v v4, (a0), v12 + th.vsxseg8h.v v4, 0(a0), v12 + th.vsxseg8h.v v4, (a0), v12, v0.t + th.vsxseg8w.v v4, (a0), v12 + th.vsxseg8w.v v4, 0(a0), v12 + th.vsxseg8w.v v4, (a0), v12, v0.t + th.vsxseg8e.v v4, (a0), v12 + th.vsxseg8e.v v4, 0(a0), v12 + th.vsxseg8e.v v4, (a0), v12, v0.t + + th.vlseg2bff.v v4, (a0) + th.vlseg2bff.v v4, 0(a0) + th.vlseg2bff.v v4, (a0), v0.t + th.vlseg2hff.v v4, (a0) + th.vlseg2hff.v v4, 0(a0) + th.vlseg2hff.v v4, (a0), v0.t + th.vlseg2wff.v v4, (a0) + th.vlseg2wff.v v4, 0(a0) + th.vlseg2wff.v v4, (a0), v0.t + th.vlseg2buff.v v4, (a0) + th.vlseg2buff.v v4, 0(a0) + th.vlseg2buff.v v4, (a0), v0.t + th.vlseg2huff.v v4, (a0) + th.vlseg2huff.v v4, 0(a0) + th.vlseg2huff.v v4, (a0), v0.t + th.vlseg2wuff.v v4, (a0) + th.vlseg2wuff.v v4, 0(a0) + th.vlseg2wuff.v v4, (a0), v0.t + th.vlseg2eff.v v4, (a0) + th.vlseg2eff.v v4, 0(a0) + th.vlseg2eff.v v4, (a0), v0.t + + th.vlseg3bff.v v4, (a0) + th.vlseg3bff.v v4, 0(a0) + th.vlseg3bff.v v4, (a0), v0.t + th.vlseg3hff.v v4, (a0) + th.vlseg3hff.v v4, 0(a0) + th.vlseg3hff.v v4, (a0), v0.t + th.vlseg3wff.v v4, (a0) + th.vlseg3wff.v v4, 0(a0) + th.vlseg3wff.v v4, (a0), v0.t + th.vlseg3buff.v v4, (a0) + th.vlseg3buff.v v4, 0(a0) + th.vlseg3buff.v v4, (a0), v0.t + th.vlseg3huff.v v4, (a0) + th.vlseg3huff.v v4, 0(a0) + th.vlseg3huff.v v4, (a0), v0.t + th.vlseg3wuff.v v4, (a0) + th.vlseg3wuff.v v4, 0(a0) + th.vlseg3wuff.v v4, (a0), v0.t + th.vlseg3eff.v v4, (a0) + th.vlseg3eff.v v4, 0(a0) + th.vlseg3eff.v v4, (a0), v0.t + + th.vlseg4bff.v v4, (a0) + th.vlseg4bff.v v4, 0(a0) + th.vlseg4bff.v v4, (a0), v0.t + th.vlseg4hff.v v4, (a0) + th.vlseg4hff.v v4, 0(a0) + th.vlseg4hff.v v4, (a0), v0.t + th.vlseg4wff.v v4, (a0) + th.vlseg4wff.v v4, 0(a0) + th.vlseg4wff.v v4, (a0), v0.t + th.vlseg4buff.v v4, (a0) + th.vlseg4buff.v v4, 0(a0) + th.vlseg4buff.v v4, (a0), v0.t + th.vlseg4huff.v v4, (a0) + th.vlseg4huff.v v4, 0(a0) + th.vlseg4huff.v v4, (a0), v0.t + th.vlseg4wuff.v v4, (a0) + th.vlseg4wuff.v v4, 0(a0) + th.vlseg4wuff.v v4, (a0), v0.t + th.vlseg4eff.v v4, (a0) + th.vlseg4eff.v v4, 0(a0) + th.vlseg4eff.v v4, (a0), v0.t + + th.vlseg5bff.v v4, (a0) + th.vlseg5bff.v v4, 0(a0) + th.vlseg5bff.v v4, (a0), v0.t + th.vlseg5hff.v v4, (a0) + th.vlseg5hff.v v4, 0(a0) + th.vlseg5hff.v v4, (a0), v0.t + th.vlseg5wff.v v4, (a0) + th.vlseg5wff.v v4, 0(a0) + th.vlseg5wff.v v4, (a0), v0.t + th.vlseg5buff.v v4, (a0) + th.vlseg5buff.v v4, 0(a0) + th.vlseg5buff.v v4, (a0), v0.t + th.vlseg5huff.v v4, (a0) + th.vlseg5huff.v v4, 0(a0) + th.vlseg5huff.v v4, (a0), v0.t + th.vlseg5wuff.v v4, (a0) + th.vlseg5wuff.v v4, 0(a0) + th.vlseg5wuff.v v4, (a0), v0.t + th.vlseg5eff.v v4, (a0) + th.vlseg5eff.v v4, 0(a0) + th.vlseg5eff.v v4, (a0), v0.t + + th.vlseg6bff.v v4, (a0) + th.vlseg6bff.v v4, 0(a0) + th.vlseg6bff.v v4, (a0), v0.t + th.vlseg6hff.v v4, (a0) + th.vlseg6hff.v v4, 0(a0) + th.vlseg6hff.v v4, (a0), v0.t + th.vlseg6wff.v v4, (a0) + th.vlseg6wff.v v4, 0(a0) + th.vlseg6wff.v v4, (a0), v0.t + th.vlseg6buff.v v4, (a0) + th.vlseg6buff.v v4, 0(a0) + th.vlseg6buff.v v4, (a0), v0.t + th.vlseg6huff.v v4, (a0) + th.vlseg6huff.v v4, 0(a0) + th.vlseg6huff.v v4, (a0), v0.t + th.vlseg6wuff.v v4, (a0) + th.vlseg6wuff.v v4, 0(a0) + th.vlseg6wuff.v v4, (a0), v0.t + th.vlseg6eff.v v4, (a0) + th.vlseg6eff.v v4, 0(a0) + th.vlseg6eff.v v4, (a0), v0.t + + th.vlseg7bff.v v4, (a0) + th.vlseg7bff.v v4, 0(a0) + th.vlseg7bff.v v4, (a0), v0.t + th.vlseg7hff.v v4, (a0) + th.vlseg7hff.v v4, 0(a0) + th.vlseg7hff.v v4, (a0), v0.t + th.vlseg7wff.v v4, (a0) + th.vlseg7wff.v v4, 0(a0) + th.vlseg7wff.v v4, (a0), v0.t + th.vlseg7buff.v v4, (a0) + th.vlseg7buff.v v4, 0(a0) + th.vlseg7buff.v v4, (a0), v0.t + th.vlseg7huff.v v4, (a0) + th.vlseg7huff.v v4, 0(a0) + th.vlseg7huff.v v4, (a0), v0.t + th.vlseg7wuff.v v4, (a0) + th.vlseg7wuff.v v4, 0(a0) + th.vlseg7wuff.v v4, (a0), v0.t + th.vlseg7eff.v v4, (a0) + th.vlseg7eff.v v4, 0(a0) + th.vlseg7eff.v v4, (a0), v0.t + + th.vlseg8bff.v v4, (a0) + th.vlseg8bff.v v4, 0(a0) + th.vlseg8bff.v v4, (a0), v0.t + th.vlseg8hff.v v4, (a0) + th.vlseg8hff.v v4, 0(a0) + th.vlseg8hff.v v4, (a0), v0.t + th.vlseg8wff.v v4, (a0) + th.vlseg8wff.v v4, 0(a0) + th.vlseg8wff.v v4, (a0), v0.t + th.vlseg8buff.v v4, (a0) + th.vlseg8buff.v v4, 0(a0) + th.vlseg8buff.v v4, (a0), v0.t + th.vlseg8huff.v v4, (a0) + th.vlseg8huff.v v4, 0(a0) + th.vlseg8huff.v v4, (a0), v0.t + th.vlseg8wuff.v v4, (a0) + th.vlseg8wuff.v v4, 0(a0) + th.vlseg8wuff.v v4, (a0), v0.t + th.vlseg8eff.v v4, (a0) + th.vlseg8eff.v v4, 0(a0) + th.vlseg8eff.v v4, (a0), v0.t diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 792958b8925..6556de2b17d 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2681,6 +2681,175 @@ #define MASK_TH_VLHFFV 0xfdf0707f #define MATCH_TH_VLWFFV 0x11006007 #define MASK_TH_VLWFFV 0xfdf0707f +#define MATCH_TH_VLSEG2BV 0x30000007 +#define MASK_TH_VLSEG2BV 0xfdf0707f +#define MATCH_TH_VLSEG2HV 0x30005007 +#define MASK_TH_VLSEG2HV 0xfdf0707f +#define MATCH_TH_VLSEG2WV 0x30006007 +#define MASK_TH_VLSEG2WV 0xfdf0707f +#define MATCH_TH_VLSEG3BV 0x50000007 +#define MASK_TH_VLSEG3BV 0xfdf0707f +#define MATCH_TH_VLSEG3HV 0x50005007 +#define MASK_TH_VLSEG3HV 0xfdf0707f +#define MATCH_TH_VLSEG3WV 0x50006007 +#define MASK_TH_VLSEG3WV 0xfdf0707f +#define MATCH_TH_VLSEG4BV 0x70000007 +#define MASK_TH_VLSEG4BV 0xfdf0707f +#define MATCH_TH_VLSEG4HV 0x70005007 +#define MASK_TH_VLSEG4HV 0xfdf0707f +#define MATCH_TH_VLSEG4WV 0x70006007 +#define MASK_TH_VLSEG4WV 0xfdf0707f +#define MATCH_TH_VLSEG5BV 0x90000007 +#define MASK_TH_VLSEG5BV 0xfdf0707f +#define MATCH_TH_VLSEG5HV 0x90005007 +#define MASK_TH_VLSEG5HV 0xfdf0707f +#define MATCH_TH_VLSEG5WV 0x90006007 +#define MASK_TH_VLSEG5WV 0xfdf0707f +#define MATCH_TH_VLSEG6BV 0xb0000007 +#define MASK_TH_VLSEG6BV 0xfdf0707f +#define MATCH_TH_VLSEG6HV 0xb0005007 +#define MASK_TH_VLSEG6HV 0xfdf0707f +#define MATCH_TH_VLSEG6WV 0xb0006007 +#define MASK_TH_VLSEG6WV 0xfdf0707f +#define MATCH_TH_VLSEG7BV 0xd0000007 +#define MASK_TH_VLSEG7BV 0xfdf0707f +#define MATCH_TH_VLSEG7HV 0xd0005007 +#define MASK_TH_VLSEG7HV 0xfdf0707f +#define MATCH_TH_VLSEG7WV 0xd0006007 +#define MASK_TH_VLSEG7WV 0xfdf0707f +#define MATCH_TH_VLSEG8BV 0xf0000007 +#define MASK_TH_VLSEG8BV 0xfdf0707f +#define MATCH_TH_VLSEG8HV 0xf0005007 +#define MASK_TH_VLSEG8HV 0xfdf0707f +#define MATCH_TH_VLSEG8WV 0xf0006007 +#define MASK_TH_VLSEG8WV 0xfdf0707f +#define MATCH_TH_VLSSEG2BV 0x38000007 +#define MASK_TH_VLSSEG2BV 0xfc00707f +#define MATCH_TH_VLSSEG2HV 0x38005007 +#define MASK_TH_VLSSEG2HV 0xfc00707f +#define MATCH_TH_VLSSEG2WV 0x38006007 +#define MASK_TH_VLSSEG2WV 0xfc00707f +#define MATCH_TH_VLSSEG3BV 0x58000007 +#define MASK_TH_VLSSEG3BV 0xfc00707f +#define MATCH_TH_VLSSEG3HV 0x58005007 +#define MASK_TH_VLSSEG3HV 0xfc00707f +#define MATCH_TH_VLSSEG3WV 0x58006007 +#define MASK_TH_VLSSEG3WV 0xfc00707f +#define MATCH_TH_VLSSEG4BV 0x78000007 +#define MASK_TH_VLSSEG4BV 0xfc00707f +#define MATCH_TH_VLSSEG4HV 0x78005007 +#define MASK_TH_VLSSEG4HV 0xfc00707f +#define MATCH_TH_VLSSEG4WV 0x78006007 +#define MASK_TH_VLSSEG4WV 0xfc00707f +#define MATCH_TH_VLSSEG5BV 0x98000007 +#define MASK_TH_VLSSEG5BV 0xfc00707f +#define MATCH_TH_VLSSEG5HV 0x98005007 +#define MASK_TH_VLSSEG5HV 0xfc00707f +#define MATCH_TH_VLSSEG5WV 0x98006007 +#define MASK_TH_VLSSEG5WV 0xfc00707f +#define MATCH_TH_VLSSEG6BV 0xb8000007 +#define MASK_TH_VLSSEG6BV 0xfc00707f +#define MATCH_TH_VLSSEG6HV 0xb8005007 +#define MASK_TH_VLSSEG6HV 0xfc00707f +#define MATCH_TH_VLSSEG6WV 0xb8006007 +#define MASK_TH_VLSSEG6WV 0xfc00707f +#define MATCH_TH_VLSSEG7BV 0xd8000007 +#define MASK_TH_VLSSEG7BV 0xfc00707f +#define MATCH_TH_VLSSEG7HV 0xd8005007 +#define MASK_TH_VLSSEG7HV 0xfc00707f +#define MATCH_TH_VLSSEG7WV 0xd8006007 +#define MASK_TH_VLSSEG7WV 0xfc00707f +#define MATCH_TH_VLSSEG8BV 0xf8000007 +#define MASK_TH_VLSSEG8BV 0xfc00707f +#define MATCH_TH_VLSSEG8HV 0xf8005007 +#define MASK_TH_VLSSEG8HV 0xfc00707f +#define MATCH_TH_VLSSEG8WV 0xf8006007 +#define MASK_TH_VLSSEG8WV 0xfc00707f +#define MATCH_TH_VLXSEG2BV 0x3c000007 +#define MASK_TH_VLXSEG2BV 0xfc00707f +#define MATCH_TH_VLXSEG2HV 0x3c005007 +#define MASK_TH_VLXSEG2HV 0xfc00707f +#define MATCH_TH_VLXSEG2WV 0x3c006007 +#define MASK_TH_VLXSEG2WV 0xfc00707f +#define MATCH_TH_VLXSEG3BV 0x5c000007 +#define MASK_TH_VLXSEG3BV 0xfc00707f +#define MATCH_TH_VLXSEG3HV 0x5c005007 +#define MASK_TH_VLXSEG3HV 0xfc00707f +#define MATCH_TH_VLXSEG3WV 0x5c006007 +#define MASK_TH_VLXSEG3WV 0xfc00707f +#define MATCH_TH_VLXSEG4BV 0x7c000007 +#define MASK_TH_VLXSEG4BV 0xfc00707f +#define MATCH_TH_VLXSEG4HV 0x7c005007 +#define MASK_TH_VLXSEG4HV 0xfc00707f +#define MATCH_TH_VLXSEG4WV 0x7c006007 +#define MASK_TH_VLXSEG4WV 0xfc00707f +#define MATCH_TH_VLXSEG5BV 0x9c000007 +#define MASK_TH_VLXSEG5BV 0xfc00707f +#define MATCH_TH_VLXSEG5HV 0x9c005007 +#define MASK_TH_VLXSEG5HV 0xfc00707f +#define MATCH_TH_VLXSEG5WV 0x9c006007 +#define MASK_TH_VLXSEG5WV 0xfc00707f +#define MATCH_TH_VLXSEG6BV 0xbc000007 +#define MASK_TH_VLXSEG6BV 0xfc00707f +#define MATCH_TH_VLXSEG6HV 0xbc005007 +#define MASK_TH_VLXSEG6HV 0xfc00707f +#define MATCH_TH_VLXSEG6WV 0xbc006007 +#define MASK_TH_VLXSEG6WV 0xfc00707f +#define MATCH_TH_VLXSEG7BV 0xdc000007 +#define MASK_TH_VLXSEG7BV 0xfc00707f +#define MATCH_TH_VLXSEG7HV 0xdc005007 +#define MASK_TH_VLXSEG7HV 0xfc00707f +#define MATCH_TH_VLXSEG7WV 0xdc006007 +#define MASK_TH_VLXSEG7WV 0xfc00707f +#define MATCH_TH_VLXSEG8BV 0xfc000007 +#define MASK_TH_VLXSEG8BV 0xfc00707f +#define MATCH_TH_VLXSEG8HV 0xfc005007 +#define MASK_TH_VLXSEG8HV 0xfc00707f +#define MATCH_TH_VLXSEG8WV 0xfc006007 +#define MASK_TH_VLXSEG8WV 0xfc00707f +#define MATCH_TH_VLSEG2BFFV 0x31000007 +#define MASK_TH_VLSEG2BFFV 0xfdf0707f +#define MATCH_TH_VLSEG2HFFV 0x31005007 +#define MASK_TH_VLSEG2HFFV 0xfdf0707f +#define MATCH_TH_VLSEG2WFFV 0x31006007 +#define MASK_TH_VLSEG2WFFV 0xfdf0707f +#define MATCH_TH_VLSEG3BFFV 0x51000007 +#define MASK_TH_VLSEG3BFFV 0xfdf0707f +#define MATCH_TH_VLSEG3HFFV 0x51005007 +#define MASK_TH_VLSEG3HFFV 0xfdf0707f +#define MATCH_TH_VLSEG3WFFV 0x51006007 +#define MASK_TH_VLSEG3WFFV 0xfdf0707f +#define MATCH_TH_VLSEG4BFFV 0x71000007 +#define MASK_TH_VLSEG4BFFV 0xfdf0707f +#define MATCH_TH_VLSEG4HFFV 0x71005007 +#define MASK_TH_VLSEG4HFFV 0xfdf0707f +#define MATCH_TH_VLSEG4WFFV 0x71006007 +#define MASK_TH_VLSEG4WFFV 0xfdf0707f +#define MATCH_TH_VLSEG5BFFV 0x91000007 +#define MASK_TH_VLSEG5BFFV 0xfdf0707f +#define MATCH_TH_VLSEG5HFFV 0x91005007 +#define MASK_TH_VLSEG5HFFV 0xfdf0707f +#define MATCH_TH_VLSEG5WFFV 0x91006007 +#define MASK_TH_VLSEG5WFFV 0xfdf0707f +#define MATCH_TH_VLSEG6BFFV 0xb1000007 +#define MASK_TH_VLSEG6BFFV 0xfdf0707f +#define MATCH_TH_VLSEG6HFFV 0xb1005007 +#define MASK_TH_VLSEG6HFFV 0xfdf0707f +#define MATCH_TH_VLSEG6WFFV 0xb1006007 +#define MASK_TH_VLSEG6WFFV 0xfdf0707f +#define MATCH_TH_VLSEG7BFFV 0xd1000007 +#define MASK_TH_VLSEG7BFFV 0xfdf0707f +#define MATCH_TH_VLSEG7HFFV 0xd1005007 +#define MASK_TH_VLSEG7HFFV 0xfdf0707f +#define MATCH_TH_VLSEG7WFFV 0xd1006007 +#define MASK_TH_VLSEG7WFFV 0xfdf0707f +#define MATCH_TH_VLSEG8BFFV 0xf1000007 +#define MASK_TH_VLSEG8BFFV 0xfdf0707f +#define MATCH_TH_VLSEG8HFFV 0xf1005007 +#define MASK_TH_VLSEG8HFFV 0xfdf0707f +#define MATCH_TH_VLSEG8WFFV 0xf1006007 +#define MASK_TH_VLSEG8WFFV 0xfdf0707f + /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ #define MATCH_VT_MASKC 0x607b #define MASK_VT_MASKC 0xfe00707f diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 54c1e8a62d9..71e4453cd43 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -2281,6 +2281,286 @@ const struct riscv_opcode riscv_opcodes[] =3D {"th.vlhuff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLE16FFV= , MASK_VLE16FFV, match_opcode, INSN_DREF }, {"th.vlwuff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLE32FFV= , MASK_VLE32FFV, match_opcode, INSN_DREF }, {"th.vleff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLE64FFV= , MASK_VLE64FFV, match_opcode, INSN_DREF }, +{"th.vlseg2b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG= 2BV, MASK_TH_VLSEG2BV, match_opcode, INSN_DREF }, +{"th.vlseg2h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG= 2HV, MASK_TH_VLSEG2HV, match_opcode, INSN_DREF }, +{"th.vlseg2w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG= 2WV, MASK_TH_VLSEG2WV, match_opcode, INSN_DREF }, +{"th.vlseg2bu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG2E8= V, MASK_VLSEG2E8V, match_opcode, INSN_DREF }, +{"th.vlseg2hu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG2E1= 6V, MASK_VLSEG2E16V, match_opcode, INSN_DREF }, +{"th.vlseg2wu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG2E3= 2V, MASK_VLSEG2E32V, match_opcode, INSN_DREF }, +{"th.vlseg2e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG2E6= 4V, MASK_VLSEG2E64V, match_opcode, INSN_DREF }, +{"th.vsseg2b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG2E8= V, MASK_VSSEG2E8V, match_opcode, INSN_DREF }, +{"th.vsseg2h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG2E1= 6V, MASK_VSSEG2E16V, match_opcode, INSN_DREF }, +{"th.vsseg2w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG2E3= 2V, MASK_VSSEG2E32V, match_opcode, INSN_DREF }, +{"th.vsseg2e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG2E6= 4V, MASK_VSSEG2E64V, match_opcode, INSN_DREF }, +{"th.vlseg3b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG= 3BV, MASK_TH_VLSEG3BV, match_opcode, INSN_DREF }, +{"th.vlseg3h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG= 3HV, MASK_TH_VLSEG3HV, match_opcode, INSN_DREF }, +{"th.vlseg3w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG= 3WV, MASK_TH_VLSEG3WV, match_opcode, INSN_DREF }, +{"th.vlseg3bu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG3E8= V, MASK_VLSEG3E8V, match_opcode, INSN_DREF }, +{"th.vlseg3hu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG3E1= 6V, MASK_VLSEG3E16V, match_opcode, INSN_DREF }, +{"th.vlseg3wu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG3E3= 2V, MASK_VLSEG3E32V, match_opcode, INSN_DREF }, +{"th.vlseg3e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG3E6= 4V, MASK_VLSEG3E64V, match_opcode, INSN_DREF }, +{"th.vsseg3b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG3E8= V, MASK_VSSEG3E8V, match_opcode, INSN_DREF }, +{"th.vsseg3h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG3E1= 6V, MASK_VSSEG3E16V, match_opcode, INSN_DREF }, +{"th.vsseg3w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG3E3= 2V, MASK_VSSEG3E32V, match_opcode, INSN_DREF }, +{"th.vsseg3e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG3E6= 4V, MASK_VSSEG3E64V, match_opcode, INSN_DREF }, +{"th.vlseg4b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG= 4BV, MASK_TH_VLSEG4BV, match_opcode, INSN_DREF }, +{"th.vlseg4h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG= 4HV, MASK_TH_VLSEG4HV, match_opcode, INSN_DREF }, +{"th.vlseg4w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG= 4WV, MASK_TH_VLSEG4WV, match_opcode, INSN_DREF }, +{"th.vlseg4bu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG4E8= V, MASK_VLSEG4E8V, match_opcode, INSN_DREF }, +{"th.vlseg4hu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG4E1= 6V, MASK_VLSEG4E16V, match_opcode, INSN_DREF }, +{"th.vlseg4wu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG4E3= 2V, MASK_VLSEG4E32V, match_opcode, INSN_DREF }, +{"th.vlseg4e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG4E6= 4V, MASK_VLSEG4E64V, match_opcode, INSN_DREF }, +{"th.vsseg4b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG4E8= V, MASK_VSSEG4E8V, match_opcode, INSN_DREF }, +{"th.vsseg4h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG4E1= 6V, MASK_VSSEG4E16V, match_opcode, INSN_DREF }, +{"th.vsseg4w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG4E3= 2V, MASK_VSSEG4E32V, match_opcode, INSN_DREF }, +{"th.vsseg4e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG4E6= 4V, MASK_VSSEG4E64V, match_opcode, INSN_DREF }, +{"th.vlseg5b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG= 5BV, MASK_TH_VLSEG5BV, match_opcode, INSN_DREF }, +{"th.vlseg5h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG= 5HV, MASK_TH_VLSEG5HV, match_opcode, INSN_DREF }, +{"th.vlseg5w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG= 5WV, MASK_TH_VLSEG5WV, match_opcode, INSN_DREF }, +{"th.vlseg5bu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG5E8= V, MASK_VLSEG5E8V, match_opcode, INSN_DREF }, +{"th.vlseg5hu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG5E1= 6V, MASK_VLSEG5E16V, match_opcode, INSN_DREF }, +{"th.vlseg5wu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG5E3= 2V, MASK_VLSEG5E32V, match_opcode, INSN_DREF }, +{"th.vlseg5e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG5E6= 4V, MASK_VLSEG5E64V, match_opcode, INSN_DREF }, +{"th.vsseg5b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG5E8= V, MASK_VSSEG5E8V, match_opcode, INSN_DREF }, +{"th.vsseg5h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG5E1= 6V, MASK_VSSEG5E16V, match_opcode, INSN_DREF }, +{"th.vsseg5w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG5E3= 2V, MASK_VSSEG5E32V, match_opcode, INSN_DREF }, +{"th.vsseg5e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG5E6= 4V, MASK_VSSEG5E64V, match_opcode, INSN_DREF }, +{"th.vlseg6b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG= 6BV, MASK_TH_VLSEG6BV, match_opcode, INSN_DREF }, +{"th.vlseg6h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG= 6HV, MASK_TH_VLSEG6HV, match_opcode, INSN_DREF }, +{"th.vlseg6w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG= 6WV, MASK_TH_VLSEG6WV, match_opcode, INSN_DREF }, +{"th.vlseg6bu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG6E8= V, MASK_VLSEG6E8V, match_opcode, INSN_DREF }, +{"th.vlseg6hu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG6E1= 6V, MASK_VLSEG6E16V, match_opcode, INSN_DREF }, +{"th.vlseg6wu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG6E3= 2V, MASK_VLSEG6E32V, match_opcode, INSN_DREF }, +{"th.vlseg6e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG6E6= 4V, MASK_VLSEG6E64V, match_opcode, INSN_DREF }, +{"th.vsseg6b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG6E8= V, MASK_VSSEG6E8V, match_opcode, INSN_DREF }, +{"th.vsseg6h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG6E1= 6V, MASK_VSSEG6E16V, match_opcode, INSN_DREF }, +{"th.vsseg6w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG6E3= 2V, MASK_VSSEG6E32V, match_opcode, INSN_DREF }, +{"th.vsseg6e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG6E6= 4V, MASK_VSSEG6E64V, match_opcode, INSN_DREF }, +{"th.vlseg7b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG= 7BV, MASK_TH_VLSEG7BV, match_opcode, INSN_DREF }, +{"th.vlseg7h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG= 7HV, MASK_TH_VLSEG7HV, match_opcode, INSN_DREF }, +{"th.vlseg7w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG= 7WV, MASK_TH_VLSEG7WV, match_opcode, INSN_DREF }, +{"th.vlseg7bu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG7E8= V, MASK_VLSEG7E8V, match_opcode, INSN_DREF }, +{"th.vlseg7hu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG7E1= 6V, MASK_VLSEG7E16V, match_opcode, INSN_DREF }, +{"th.vlseg7wu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG7E3= 2V, MASK_VLSEG7E32V, match_opcode, INSN_DREF }, +{"th.vlseg7e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG7E6= 4V, MASK_VLSEG7E64V, match_opcode, INSN_DREF }, +{"th.vsseg7b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG7E8= V, MASK_VSSEG7E8V, match_opcode, INSN_DREF }, +{"th.vsseg7h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG7E1= 6V, MASK_VSSEG7E16V, match_opcode, INSN_DREF }, +{"th.vsseg7w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG7E3= 2V, MASK_VSSEG7E32V, match_opcode, INSN_DREF }, +{"th.vsseg7e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG7E6= 4V, MASK_VSSEG7E64V, match_opcode, INSN_DREF }, +{"th.vlseg8b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG= 8BV, MASK_TH_VLSEG8BV, match_opcode, INSN_DREF }, +{"th.vlseg8h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG= 8HV, MASK_TH_VLSEG8HV, match_opcode, INSN_DREF }, +{"th.vlseg8w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLSEG= 8WV, MASK_TH_VLSEG8WV, match_opcode, INSN_DREF }, +{"th.vlseg8bu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG8E8= V, MASK_VLSEG8E8V, match_opcode, INSN_DREF }, +{"th.vlseg8hu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG8E1= 6V, MASK_VLSEG8E16V, match_opcode, INSN_DREF }, +{"th.vlseg8wu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG8E3= 2V, MASK_VLSEG8E32V, match_opcode, INSN_DREF }, +{"th.vlseg8e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG8E6= 4V, MASK_VLSEG8E64V, match_opcode, INSN_DREF }, +{"th.vsseg8b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG8E8= V, MASK_VSSEG8E8V, match_opcode, INSN_DREF }, +{"th.vsseg8h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG8E1= 6V, MASK_VSSEG8E16V, match_opcode, INSN_DREF }, +{"th.vsseg8w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG8E3= 2V, MASK_VSSEG8E32V, match_opcode, INSN_DREF }, +{"th.vsseg8e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VSSEG8E6= 4V, MASK_VSSEG8E64V, match_opcode, INSN_DREF }, +{"th.vlsseg2b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_TH_VL= SSEG2BV, MASK_TH_VLSSEG2BV, match_opcode, INSN_DREF }, +{"th.vlsseg2h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_TH_VL= SSEG2HV, MASK_TH_VLSSEG2HV, match_opcode, INSN_DREF }, +{"th.vlsseg2w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_TH_VL= SSEG2WV, MASK_TH_VLSSEG2WV, match_opcode, INSN_DREF }, +{"th.vlsseg2bu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VLSSE= G2E8V, MASK_VLSSEG2E8V, match_opcode, INSN_DREF }, +{"th.vlsseg2hu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VLSSE= G2E16V, MASK_VLSSEG2E16V, match_opcode, INSN_DREF }, +{"th.vlsseg2wu.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VLSSE= G2E32V, MASK_VLSSEG2E32V, match_opcode, INSN_DREF }, +{"th.vlsseg2e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VLSSE= G2E64V, MASK_VLSSEG2E64V, match_opcode, INSN_DREF }, +{"th.vssseg2b.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VSSSE= G2E8V, MASK_VSSSEG2E8V, match_opcode, INSN_DREF }, +{"th.vssseg2h.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VSSSE= G2E16V, MASK_VSSSEG2E16V, match_opcode, INSN_DREF }, +{"th.vssseg2w.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VSSSE= G2E32V, MASK_VSSSEG2E32V, match_opcode, INSN_DREF }, +{"th.vssseg2e.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s),tVm", MATCH_VSSSE= G2E64V, MASK_VSSSEG2E64V, match_opcode, [...] [diff truncated at 100000 bytes]