* [binutils-gdb] RISC-V: Add fixed-point arithmetic instructions for T-Head VECTOR vendor extension
@ 2023-11-23 2:09 Nelson Chu
0 siblings, 0 replies; only message in thread
From: Nelson Chu @ 2023-11-23 2:09 UTC (permalink / raw)
To: bfd-cvs
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=9a51da2636778dce2e2635cb10822a92a51b2b9e
commit 9a51da2636778dce2e2635cb10822a92a51b2b9e
Author: Jin Ma <jinma@linux.alibaba.com>
Date: Sat Nov 18 15:07:20 2023 +0800
RISC-V: Add fixed-point arithmetic instructions for T-Head VECTOR vendor extension
T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.
This patch adds fixed-point arithmetic instructions for the
"XTheadVector" extension. The 'th' prefix and the
"XTheadVector" extension are documented in a PR for the
RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>
gas/ChangeLog:
* testsuite/gas/riscv/x-thead-vector.d: Add tests for
fixed-point arithmetic instructions.
* testsuite/gas/riscv/x-thead-vector.s: Likewise.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_TH_VAADDVV): New.
opcodes/ChangeLog:
* riscv-opc.c: Likewise.
Diff:
---
gas/testsuite/gas/riscv/x-thead-vector.d | 86 +++++++++++++++++++++++++++++
gas/testsuite/gas/riscv/x-thead-vector.s | 92 ++++++++++++++++++++++++++++++++
include/opcode/riscv-opc.h | 12 +++++
opcodes/riscv-opc.c | 36 +++++++++++++
4 files changed, 226 insertions(+)
diff --git a/gas/testsuite/gas/riscv/x-thead-vector.d b/gas/testsuite/gas/riscv/x-thead-vector.d
index c5ad56e1e58..bbcf6d4890a 100644
--- a/gas/testsuite/gas/riscv/x-thead-vector.d
+++ b/gas/testsuite/gas/riscv/x-thead-vector.d
@@ -1304,3 +1304,89 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+5e05c457[ ]+th.vmv.v.x[ ]+v8,a1
[ ]+[0-9a-f]+:[ ]+5e07b457[ ]+th.vmv.v.i[ ]+v8,15
[ ]+[0-9a-f]+:[ ]+5e083457[ ]+th.vmv.v.i[ ]+v8,-16
+[ ]+[0-9a-f]+:[ ]+82860257[ ]+th.vsaddu.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+8285c257[ ]+th.vsaddu.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+8287b257[ ]+th.vsaddu.vi[ ]+v4,v8,15
+[ ]+[0-9a-f]+:[ ]+82883257[ ]+th.vsaddu.vi[ ]+v4,v8,-16
+[ ]+[0-9a-f]+:[ ]+80860257[ ]+th.vsaddu.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+8085c257[ ]+th.vsaddu.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+8087b257[ ]+th.vsaddu.vi[ ]+v4,v8,15,v0.t
+[ ]+[0-9a-f]+:[ ]+80883257[ ]+th.vsaddu.vi[ ]+v4,v8,-16,v0.t
+[ ]+[0-9a-f]+:[ ]+86860257[ ]+th.vsadd.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+8685c257[ ]+th.vsadd.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+8687b257[ ]+th.vsadd.vi[ ]+v4,v8,15
+[ ]+[0-9a-f]+:[ ]+86883257[ ]+th.vsadd.vi[ ]+v4,v8,-16
+[ ]+[0-9a-f]+:[ ]+84860257[ ]+th.vsadd.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+8485c257[ ]+th.vsadd.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+8487b257[ ]+th.vsadd.vi[ ]+v4,v8,15,v0.t
+[ ]+[0-9a-f]+:[ ]+84883257[ ]+th.vsadd.vi[ ]+v4,v8,-16,v0.t
+[ ]+[0-9a-f]+:[ ]+8a860257[ ]+th.vssubu.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+8a85c257[ ]+th.vssubu.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+88860257[ ]+th.vssubu.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+8885c257[ ]+th.vssubu.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+8e860257[ ]+th.vssub.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+8e85c257[ ]+th.vssub.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+8c860257[ ]+th.vssub.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+8c85c257[ ]+th.vssub.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+92860257[ ]+th.vaadd.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+9285c257[ ]+th.vaadd.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+9287b257[ ]+th.vaadd.vi[ ]+v4,v8,15
+[ ]+[0-9a-f]+:[ ]+92883257[ ]+th.vaadd.vi[ ]+v4,v8,-16
+[ ]+[0-9a-f]+:[ ]+90860257[ ]+th.vaadd.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+9085c257[ ]+th.vaadd.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+9087b257[ ]+th.vaadd.vi[ ]+v4,v8,15,v0.t
+[ ]+[0-9a-f]+:[ ]+90883257[ ]+th.vaadd.vi[ ]+v4,v8,-16,v0.t
+[ ]+[0-9a-f]+:[ ]+9a860257[ ]+th.vasub.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+9a85c257[ ]+th.vasub.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+98860257[ ]+th.vasub.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+9885c257[ ]+th.vasub.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+9e860257[ ]+th.vsmul.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+9e85c257[ ]+th.vsmul.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+9c860257[ ]+th.vsmul.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+9c85c257[ ]+th.vsmul.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+f2860257[ ]+th.vwsmaccu.vv[ ]+v4,v12,v8
+[ ]+[0-9a-f]+:[ ]+f285c257[ ]+th.vwsmaccu.vx[ ]+v4,a1,v8
+[ ]+[0-9a-f]+:[ ]+f6860257[ ]+th.vwsmacc.vv[ ]+v4,v12,v8
+[ ]+[0-9a-f]+:[ ]+f685c257[ ]+th.vwsmacc.vx[ ]+v4,a1,v8
+[ ]+[0-9a-f]+:[ ]+fa860257[ ]+th.vwsmaccsu.vv[ ]+v4,v12,v8
+[ ]+[0-9a-f]+:[ ]+fa85c257[ ]+th.vwsmaccsu.vx[ ]+v4,a1,v8
+[ ]+[0-9a-f]+:[ ]+fe85c257[ ]+th.vwsmaccus.vx[ ]+v4,a1,v8
+[ ]+[0-9a-f]+:[ ]+f0860257[ ]+th.vwsmaccu.vv[ ]+v4,v12,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+f085c257[ ]+th.vwsmaccu.vx[ ]+v4,a1,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+f4860257[ ]+th.vwsmacc.vv[ ]+v4,v12,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+f485c257[ ]+th.vwsmacc.vx[ ]+v4,a1,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+f8860257[ ]+th.vwsmaccsu.vv[ ]+v4,v12,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+f885c257[ ]+th.vwsmaccsu.vx[ ]+v4,a1,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+fc85c257[ ]+th.vwsmaccus.vx[ ]+v4,a1,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+aa860257[ ]+th.vssrl.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+aa85c257[ ]+th.vssrl.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+aa80b257[ ]+th.vssrl.vi[ ]+v4,v8,1
+[ ]+[0-9a-f]+:[ ]+aa8fb257[ ]+th.vssrl.vi[ ]+v4,v8,31
+[ ]+[0-9a-f]+:[ ]+a8860257[ ]+th.vssrl.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+a885c257[ ]+th.vssrl.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+a880b257[ ]+th.vssrl.vi[ ]+v4,v8,1,v0.t
+[ ]+[0-9a-f]+:[ ]+a88fb257[ ]+th.vssrl.vi[ ]+v4,v8,31,v0.t
+[ ]+[0-9a-f]+:[ ]+ae860257[ ]+th.vssra.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+ae85c257[ ]+th.vssra.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+ae80b257[ ]+th.vssra.vi[ ]+v4,v8,1
+[ ]+[0-9a-f]+:[ ]+ae8fb257[ ]+th.vssra.vi[ ]+v4,v8,31
+[ ]+[0-9a-f]+:[ ]+ac860257[ ]+th.vssra.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+ac85c257[ ]+th.vssra.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+ac80b257[ ]+th.vssra.vi[ ]+v4,v8,1,v0.t
+[ ]+[0-9a-f]+:[ ]+ac8fb257[ ]+th.vssra.vi[ ]+v4,v8,31,v0.t
+[ ]+[0-9a-f]+:[ ]+ba860257[ ]+th.vnclipu.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+ba85c257[ ]+th.vnclipu.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+ba80b257[ ]+th.vnclipu.vi[ ]+v4,v8,1
+[ ]+[0-9a-f]+:[ ]+ba8fb257[ ]+th.vnclipu.vi[ ]+v4,v8,31
+[ ]+[0-9a-f]+:[ ]+b8860257[ ]+th.vnclipu.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+b885c257[ ]+th.vnclipu.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+b880b257[ ]+th.vnclipu.vi[ ]+v4,v8,1,v0.t
+[ ]+[0-9a-f]+:[ ]+b88fb257[ ]+th.vnclipu.vi[ ]+v4,v8,31,v0.t
+[ ]+[0-9a-f]+:[ ]+be860257[ ]+th.vnclip.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+be85c257[ ]+th.vnclip.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+be80b257[ ]+th.vnclip.vi[ ]+v4,v8,1
+[ ]+[0-9a-f]+:[ ]+be8fb257[ ]+th.vnclip.vi[ ]+v4,v8,31
+[ ]+[0-9a-f]+:[ ]+bc860257[ ]+th.vnclip.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+bc85c257[ ]+th.vnclip.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+bc80b257[ ]+th.vnclip.vi[ ]+v4,v8,1,v0.t
+[ ]+[0-9a-f]+:[ ]+bc8fb257[ ]+th.vnclip.vi[ ]+v4,v8,31,v0.t
diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/riscv/x-thead-vector.s
index 9235de70694..97a0e1a5d79 100644
--- a/gas/testsuite/gas/riscv/x-thead-vector.s
+++ b/gas/testsuite/gas/riscv/x-thead-vector.s
@@ -1340,3 +1340,95 @@
th.vmv.v.x v8, a1
th.vmv.v.i v8, 15
th.vmv.v.i v8, -16
+
+ th.vsaddu.vv v4, v8, v12
+ th.vsaddu.vx v4, v8, a1
+ th.vsaddu.vi v4, v8, 15
+ th.vsaddu.vi v4, v8, -16
+ th.vsaddu.vv v4, v8, v12, v0.t
+ th.vsaddu.vx v4, v8, a1, v0.t
+ th.vsaddu.vi v4, v8, 15, v0.t
+ th.vsaddu.vi v4, v8, -16, v0.t
+ th.vsadd.vv v4, v8, v12
+ th.vsadd.vx v4, v8, a1
+ th.vsadd.vi v4, v8, 15
+ th.vsadd.vi v4, v8, -16
+ th.vsadd.vv v4, v8, v12, v0.t
+ th.vsadd.vx v4, v8, a1, v0.t
+ th.vsadd.vi v4, v8, 15, v0.t
+ th.vsadd.vi v4, v8, -16, v0.t
+ th.vssubu.vv v4, v8, v12
+ th.vssubu.vx v4, v8, a1
+ th.vssubu.vv v4, v8, v12, v0.t
+ th.vssubu.vx v4, v8, a1, v0.t
+ th.vssub.vv v4, v8, v12
+ th.vssub.vx v4, v8, a1
+ th.vssub.vv v4, v8, v12, v0.t
+ th.vssub.vx v4, v8, a1, v0.t
+
+ th.vaadd.vv v4, v8, v12
+ th.vaadd.vx v4, v8, a1
+ th.vaadd.vi v4, v8, 15
+ th.vaadd.vi v4, v8, -16
+ th.vaadd.vv v4, v8, v12, v0.t
+ th.vaadd.vx v4, v8, a1, v0.t
+ th.vaadd.vi v4, v8, 15, v0.t
+ th.vaadd.vi v4, v8, -16, v0.t
+ th.vasub.vv v4, v8, v12
+ th.vasub.vx v4, v8, a1
+ th.vasub.vv v4, v8, v12, v0.t
+ th.vasub.vx v4, v8, a1, v0.t
+
+ th.vsmul.vv v4, v8, v12
+ th.vsmul.vx v4, v8, a1
+ th.vsmul.vv v4, v8, v12, v0.t
+ th.vsmul.vx v4, v8, a1, v0.t
+
+ th.vwsmaccu.vv v4, v12, v8
+ th.vwsmaccu.vx v4, a1, v8
+ th.vwsmacc.vv v4, v12, v8
+ th.vwsmacc.vx v4, a1, v8
+ th.vwsmaccsu.vv v4, v12, v8
+ th.vwsmaccsu.vx v4, a1, v8
+ th.vwsmaccus.vx v4, a1, v8
+ th.vwsmaccu.vv v4, v12, v8, v0.t
+ th.vwsmaccu.vx v4, a1, v8, v0.t
+ th.vwsmacc.vv v4, v12, v8, v0.t
+ th.vwsmacc.vx v4, a1, v8, v0.t
+ th.vwsmaccsu.vv v4, v12, v8, v0.t
+ th.vwsmaccsu.vx v4, a1, v8, v0.t
+ th.vwsmaccus.vx v4, a1, v8, v0.t
+
+ th.vssrl.vv v4, v8, v12
+ th.vssrl.vx v4, v8, a1
+ th.vssrl.vi v4, v8, 1
+ th.vssrl.vi v4, v8, 31
+ th.vssrl.vv v4, v8, v12, v0.t
+ th.vssrl.vx v4, v8, a1, v0.t
+ th.vssrl.vi v4, v8, 1, v0.t
+ th.vssrl.vi v4, v8, 31, v0.t
+ th.vssra.vv v4, v8, v12
+ th.vssra.vx v4, v8, a1
+ th.vssra.vi v4, v8, 1
+ th.vssra.vi v4, v8, 31
+ th.vssra.vv v4, v8, v12, v0.t
+ th.vssra.vx v4, v8, a1, v0.t
+ th.vssra.vi v4, v8, 1, v0.t
+ th.vssra.vi v4, v8, 31, v0.t
+
+ th.vnclipu.vv v4, v8, v12
+ th.vnclipu.vx v4, v8, a1
+ th.vnclipu.vi v4, v8, 1
+ th.vnclipu.vi v4, v8, 31
+ th.vnclipu.vv v4, v8, v12, v0.t
+ th.vnclipu.vx v4, v8, a1, v0.t
+ th.vnclipu.vi v4, v8, 1, v0.t
+ th.vnclipu.vi v4, v8, 31, v0.t
+ th.vnclip.vv v4, v8, v12
+ th.vnclip.vx v4, v8, a1
+ th.vnclip.vi v4, v8, 1
+ th.vnclip.vi v4, v8, 31
+ th.vnclip.vv v4, v8, v12, v0.t
+ th.vnclip.vx v4, v8, a1, v0.t
+ th.vnclip.vi v4, v8, 1, v0.t
+ th.vnclip.vi v4, v8, 31, v0.t
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index df4b7abcedb..5cca4c5bb43 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2897,6 +2897,18 @@
#define MASK_TH_VSBCVXM 0xfe00707f
#define MATCH_TH_VWMACCSUVV 0xf8002057
#define MASK_TH_VWMACCSUVV 0xfc00707f
+#define MATCH_TH_VAADDVV 0x90000057
+#define MASK_TH_VAADDVV 0xfc00707f
+#define MATCH_TH_VAADDVX 0x90004057
+#define MASK_TH_VAADDVX 0xfc00707f
+#define MATCH_TH_VAADDVI 0x90003057
+#define MASK_TH_VAADDVI 0xfc00707f
+#define MATCH_TH_VASUBVV 0x98000057
+#define MASK_TH_VASUBVV 0xfc00707f
+#define MATCH_TH_VASUBVX 0x98004057
+#define MASK_TH_VASUBVX 0xfc00707f
+#define MATCH_TH_VWSMACCSUVV 0xf8000057
+#define MASK_TH_VWSMACCSUVV 0xfc00707f
/* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
#define MATCH_VT_MASKC 0x607b
#define MASK_VT_MASKC 0xfe00707f
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index b0061ebb3f7..6a8d41df0e6 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2722,6 +2722,42 @@ const struct riscv_opcode riscv_opcodes[] =
{"th.vmv.v.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs", MATCH_VMVVV, MASK_VMVVV, match_opcode, 0 },
{"th.vmv.v.x", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s", MATCH_VMVVX, MASK_VMVVX, match_opcode, 0 },
{"th.vmv.v.i", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vi", MATCH_VMVVI, MASK_VMVVI, match_opcode, 0 },
+{"th.vsaddu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VSADDUVV, MASK_VSADDUVV, match_opcode, 0 },
+{"th.vsaddu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VSADDUVX, MASK_VSADDUVX, match_opcode, 0 },
+{"th.vsaddu.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_VSADDUVI, MASK_VSADDUVI, match_opcode, 0 },
+{"th.vsadd.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VSADDVV, MASK_VSADDVV, match_opcode, 0 },
+{"th.vsadd.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VSADDVX, MASK_VSADDVX, match_opcode, 0 },
+{"th.vsadd.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_VSADDVI, MASK_VSADDVI, match_opcode, 0 },
+{"th.vssubu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VSSUBUVV, MASK_VSSUBUVV, match_opcode, 0 },
+{"th.vssubu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VSSUBUVX, MASK_VSSUBUVX, match_opcode, 0 },
+{"th.vssub.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VSSUBVV, MASK_VSSUBVV, match_opcode, 0 },
+{"th.vssub.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VSSUBVX, MASK_VSSUBVX, match_opcode, 0 },
+{"th.vaadd.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VAADDVV, MASK_TH_VAADDVV, match_opcode, 0 },
+{"th.vaadd.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VAADDVX, MASK_TH_VAADDVX, match_opcode, 0 },
+{"th.vaadd.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_TH_VAADDVI, MASK_TH_VAADDVI, match_opcode, 0 },
+{"th.vasub.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VASUBVV, MASK_TH_VASUBVV, match_opcode, 0 },
+{"th.vasub.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VASUBVX, MASK_TH_VASUBVX, match_opcode, 0 },
+{"th.vsmul.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VSMULVV, MASK_VSMULVV, match_opcode, 0 },
+{"th.vsmul.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VSMULVX, MASK_VSMULVX, match_opcode, 0 },
+{"th.vwsmaccu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VQMACCUVV, MASK_VQMACCUVV, match_opcode, 0 },
+{"th.vwsmaccu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s,VtVm", MATCH_VQMACCUVX, MASK_VQMACCUVX, match_opcode, 0 },
+{"th.vwsmacc.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_VQMACCVV, MASK_VQMACCVV, match_opcode, 0 },
+{"th.vwsmacc.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s,VtVm", MATCH_VQMACCVX, MASK_VQMACCVX, match_opcode, 0 },
+{"th.vwsmaccsu.vv",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VWSMACCSUVV, MASK_TH_VWSMACCSUVV, match_opcode, 0 },
+{"th.vwsmaccsu.vx",0, INSN_CLASS_XTHEADVECTOR, "Vd,s,VtVm", MATCH_VQMACCUSVX, MASK_VQMACCUSVX, match_opcode, 0 },
+{"th.vwsmaccus.vx",0, INSN_CLASS_XTHEADVECTOR, "Vd,s,VtVm", MATCH_VQMACCSUVX, MASK_VQMACCSUVX, match_opcode, 0 },
+{"th.vssrl.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VSSRLVV, MASK_VSSRLVV, match_opcode, 0 },
+{"th.vssrl.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VSSRLVX, MASK_VSSRLVX, match_opcode, 0 },
+{"th.vssrl.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_VSSRLVI, MASK_VSSRLVI, match_opcode, 0 },
+{"th.vssra.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VSSRAVV, MASK_VSSRAVV, match_opcode, 0 },
+{"th.vssra.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VSSRAVX, MASK_VSSRAVX, match_opcode, 0 },
+{"th.vssra.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_VSSRAVI, MASK_VSSRAVI, match_opcode, 0 },
+{"th.vnclipu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VNCLIPUWV, MASK_VNCLIPUWV, match_opcode, 0 },
+{"th.vnclipu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VNCLIPUWX, MASK_VNCLIPUWX, match_opcode, 0 },
+{"th.vnclipu.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_VNCLIPUWI, MASK_VNCLIPUWI, match_opcode, 0 },
+{"th.vnclip.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VNCLIPWV, MASK_VNCLIPWV, match_opcode, 0 },
+{"th.vnclip.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VNCLIPWX, MASK_VNCLIPWX, match_opcode, 0 },
+{"th.vnclip.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_VNCLIPWI, MASK_VNCLIPWI, match_opcode, 0 },
/* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
{"vt.maskc", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },
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2023-11-23 2:09 [binutils-gdb] RISC-V: Add fixed-point arithmetic instructions for T-Head VECTOR vendor extension Nelson Chu
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