From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7803) id CA5673871012; Thu, 23 Nov 2023 02:09:39 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org CA5673871012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Nelson Chu To: bfd-cvs@sourceware.org Subject: [binutils-gdb] RISC-V: Add vector permutation instructions for T-Head VECTOR vendor extension X-Act-Checkin: binutils-gdb X-Git-Author: Jin Ma X-Git-Refname: refs/heads/master X-Git-Oldrev: 832cdeeccb063073ba2893ec63060773fc8b98ae X-Git-Newrev: d95ba7227e2185ed83e5d62975f2ca76f445146c Message-Id: <20231123020939.CA5673871012@sourceware.org> Date: Thu, 23 Nov 2023 02:09:39 +0000 (GMT) X-BeenThere: binutils-cvs@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 23 Nov 2023 02:09:39 -0000 https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3Dd95ba7227e21= 85ed83e5d62975f2ca76f445146c commit d95ba7227e2185ed83e5d62975f2ca76f445146c Author: Jin Ma Date: Sat Nov 18 15:08:59 2023 +0800 RISC-V: Add vector permutation instructions for T-Head VECTOR vendor ex= tension =20 T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. =20 This patch adds permutation instructions for the "XTheadVector" extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). =20 [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 =20 Co-developed-by: Lifang Xia Co-developed-by: Christoph M=C3=BCllner =20 gas/ChangeLog: =20 * testsuite/gas/riscv/x-thead-vector.d: Add tests for permutation instructions. * testsuite/gas/riscv/x-thead-vector.s: Likewise. =20 include/ChangeLog: =20 * opcode/riscv-opc.h (MATCH_TH_VMVXS): New. =20 opcodes/ChangeLog: =20 * riscv-opc.c: Likewise. Diff: --- gas/testsuite/gas/riscv/x-thead-vector.d | 30 +++++++++++++++++++++++++ gas/testsuite/gas/riscv/x-thead-vector.s | 38 ++++++++++++++++++++++++++++= ++++ include/opcode/riscv-opc.h | 10 +++++++++ opcodes/riscv-opc.c | 15 +++++++++++++ 4 files changed, 93 insertions(+) diff --git a/gas/testsuite/gas/riscv/x-thead-vector.d b/gas/testsuite/gas/r= iscv/x-thead-vector.d index 03d8ede7c77..014c2fdb80d 100644 --- a/gas/testsuite/gas/riscv/x-thead-vector.d +++ b/gas/testsuite/gas/riscv/x-thead-vector.d @@ -1618,3 +1618,33 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+58812257[ ]+th.vmsof.m[ ]+v4,v8,v0.t [ ]+[0-9a-f]+:[ ]+58882257[ ]+th.viota.m[ ]+v4,v8,v0.t [ ]+[0-9a-f]+:[ ]+5808a257[ ]+th.vid.v[ ]+v4,v0.t +[ ]+[0-9a-f]+:[ ]+32c02557[ ]+th.vmv.x.s[ ]+a0,v12 +[ ]+[0-9a-f]+:[ ]+32c62557[ ]+th.vext.x.v[ ]+a0,v12,a2 +[ ]+[0-9a-f]+:[ ]+36056257[ ]+th.vmv.s.x[ ]+v4,a0 +[ ]+[0-9a-f]+:[ ]+32801557[ ]+th.vfmv.f.s[ ]+fa0,v8 +[ ]+[0-9a-f]+:[ ]+3605d257[ ]+th.vfmv.s.f[ ]+v4,fa1 +[ ]+[0-9a-f]+:[ ]+3a85c257[ ]+th.vslideup.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+3a803257[ ]+th.vslideup.vi[ ]+v4,v8,0 +[ ]+[0-9a-f]+:[ ]+3a8fb257[ ]+th.vslideup.vi[ ]+v4,v8,31 +[ ]+[0-9a-f]+:[ ]+3e85c257[ ]+th.vslidedown.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+3e803257[ ]+th.vslidedown.vi[ ]+v4,v8,0 +[ ]+[0-9a-f]+:[ ]+3e8fb257[ ]+th.vslidedown.vi[ ]+v4,v8,31 +[ ]+[0-9a-f]+:[ ]+3885c257[ ]+th.vslideup.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+38803257[ ]+th.vslideup.vi[ ]+v4,v8,0,v0.t +[ ]+[0-9a-f]+:[ ]+388fb257[ ]+th.vslideup.vi[ ]+v4,v8,31,v0.t +[ ]+[0-9a-f]+:[ ]+3c85c257[ ]+th.vslidedown.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+3c803257[ ]+th.vslidedown.vi[ ]+v4,v8,0,v0.t +[ ]+[0-9a-f]+:[ ]+3c8fb257[ ]+th.vslidedown.vi[ ]+v4,v8,31,v0.t +[ ]+[0-9a-f]+:[ ]+3a85e257[ ]+th.vslide1up.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+3e85e257[ ]+th.vslide1down.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+3885e257[ ]+th.vslide1up.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+3c85e257[ ]+th.vslide1down.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+32860257[ ]+th.vrgather.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+3285c257[ ]+th.vrgather.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+32803257[ ]+th.vrgather.vi[ ]+v4,v8,0 +[ ]+[0-9a-f]+:[ ]+328fb257[ ]+th.vrgather.vi[ ]+v4,v8,31 +[ ]+[0-9a-f]+:[ ]+30860257[ ]+th.vrgather.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+3085c257[ ]+th.vrgather.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+30803257[ ]+th.vrgather.vi[ ]+v4,v8,0,v0.t +[ ]+[0-9a-f]+:[ ]+308fb257[ ]+th.vrgather.vi[ ]+v4,v8,31,v0.t +[ ]+[0-9a-f]+:[ ]+5e862257[ ]+th.vcompress.vm[ ]+v4,v8,v12 diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/r= iscv/x-thead-vector.s index 1c1c27cb6d8..3a4dea38c8b 100644 --- a/gas/testsuite/gas/riscv/x-thead-vector.s +++ b/gas/testsuite/gas/riscv/x-thead-vector.s @@ -1686,3 +1686,41 @@ th.vmsof.m v4, v8, v0.t th.viota.m v4, v8, v0.t th.vid.v v4, v0.t + + # Alias + th.vmv.x.s a0, v12 + + th.vext.x.v a0, v12, a2 + th.vmv.s.x v4, a0 + + th.vfmv.f.s fa0, v8 + th.vfmv.s.f v4, fa1 + + th.vslideup.vx v4, v8, a1 + th.vslideup.vi v4, v8, 0 + th.vslideup.vi v4, v8, 31 + th.vslidedown.vx v4, v8, a1 + th.vslidedown.vi v4, v8, 0 + th.vslidedown.vi v4, v8, 31 + th.vslideup.vx v4, v8, a1, v0.t + th.vslideup.vi v4, v8, 0, v0.t + th.vslideup.vi v4, v8, 31, v0.t + th.vslidedown.vx v4, v8, a1, v0.t + th.vslidedown.vi v4, v8, 0, v0.t + th.vslidedown.vi v4, v8, 31, v0.t + + th.vslide1up.vx v4, v8, a1 + th.vslide1down.vx v4, v8, a1 + th.vslide1up.vx v4, v8, a1, v0.t + th.vslide1down.vx v4, v8, a1, v0.t + + th.vrgather.vv v4, v8, v12 + th.vrgather.vx v4, v8, a1 + th.vrgather.vi v4, v8, 0 + th.vrgather.vi v4, v8, 31 + th.vrgather.vv v4, v8, v12, v0.t + th.vrgather.vx v4, v8, a1, v0.t + th.vrgather.vi v4, v8, 0, v0.t + th.vrgather.vi v4, v8, 31, v0.t + + th.vcompress.vm v4, v8, v12 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 9b4288c8ee2..1e417217b7d 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2959,6 +2959,16 @@ #define MASK_TH_VIOTAM 0xfc0ff07f #define MATCH_TH_VIDV 0x5808a057 #define MASK_TH_VIDV 0xfdfff07f +#define MATCH_TH_VMVXS 0x32002057 +#define MASK_TH_VMVXS 0xfe0ff07f +#define MATCH_TH_VEXTXV 0x32002057 +#define MASK_TH_VEXTXV 0xfe00707f +#define MATCH_TH_VMVSX 0x36006057 +#define MASK_TH_VMVSX 0xfff0707f +#define MATCH_TH_VFMVFS 0x32001057 +#define MASK_TH_VFMVFS 0xfe0ff07f +#define MATCH_TH_VFMVSF 0x36005057 +#define MASK_TH_VFMVSF 0xfff0707f /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ #define MATCH_VT_MASKC 0x607b #define MASK_VT_MASKC 0xfe00707f diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index b9b47cf849e..fcba49972f0 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -2879,6 +2879,21 @@ const struct riscv_opcode riscv_opcodes[] =3D {"th.vmsof.m", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VMSOFM, = MASK_TH_VMSOFM, match_opcode, 0}, {"th.viota.m", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VIOTAM, = MASK_TH_VIOTAM, match_opcode, 0}, {"th.vid.v", 0, INSN_CLASS_XTHEADVECTOR, "VdVm", MATCH_TH_VIDV, MASK_= TH_VIDV, match_opcode, 0}, +{"th.vmv.x.s", 0, INSN_CLASS_XTHEADVECTOR, "d,Vt", MATCH_TH_VMVXS, MASK= _TH_VMVXS, match_opcode, INSN_ALIAS}, +{"th.vext.x.v", 0, INSN_CLASS_XTHEADVECTOR, "d,Vt,s", MATCH_TH_VEXTXV, M= ASK_TH_VEXTXV, match_opcode, 0}, +{"th.vmv.s.x", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s", MATCH_TH_VMVSX, MASK= _TH_VMVSX, match_opcode, 0}, +{"th.vfmv.f.s", 0, INSN_CLASS_XTHEADVECTOR, "D,Vt", MATCH_TH_VFMVFS, MAS= K_TH_VFMVFS, match_opcode, 0}, +{"th.vfmv.s.f", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S", MATCH_TH_VFMVSF, MAS= K_TH_VFMVSF, match_opcode, 0}, +{"th.vslideup.vx",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VSLIDEUPV= X, MASK_VSLIDEUPVX, match_opcode, 0}, +{"th.vslideup.vi",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_VSLIDEUP= VI, MASK_VSLIDEUPVI, match_opcode, 0}, +{"th.vslidedown.vx",0,INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VSLIDEDO= WNVX, MASK_VSLIDEDOWNVX, match_opcode, 0}, +{"th.vslidedown.vi",0,INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_VSLIDED= OWNVI, MASK_VSLIDEDOWNVI, match_opcode, 0}, +{"th.vslide1up.vx",0 ,INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VSLIDE1U= PVX, MASK_VSLIDE1UPVX, match_opcode, 0}, +{"th.vslide1down.vx",0,INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VSLIDE1= DOWNVX, MASK_VSLIDE1DOWNVX, match_opcode, 0}, +{"th.vrgather.vv",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VRGATHER= VV, MASK_VRGATHERVV, match_opcode, 0}, +{"th.vrgather.vx",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VRGATHERV= X, MASK_VRGATHERVX, match_opcode, 0}, +{"th.vrgather.vi",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_VRGATHER= VI, MASK_VRGATHERVI, match_opcode, 0}, +{"th.vcompress.vm",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs", MATCH_VCOMPRESS= VM, MASK_VCOMPRESSVM, match_opcode, 0}, =20 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ {"vt.maskc", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MA= SK_VT_MASKC, match_opcode, 0 },