From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1386) id 5A9833858D33; Fri, 24 Nov 2023 08:54:10 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5A9833858D33 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Jan Beulich To: bfd-cvs@sourceware.org Subject: [binutils-gdb] RISC-V: reduce redundancy in sign/zero extension macro insn handling X-Act-Checkin: binutils-gdb X-Git-Author: Jan Beulich X-Git-Refname: refs/heads/master X-Git-Oldrev: 27b33966b18ed8bf1701a60999448224b1d28273 X-Git-Newrev: eb5e952f95423bc6ae18457ccc359c8b6c0fa387 Message-Id: <20231124085413.5A9833858D33@sourceware.org> Date: Fri, 24 Nov 2023 08:54:10 +0000 (GMT) X-BeenThere: binutils-cvs@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 24 Nov 2023 08:54:13 -0000 https://sourceware.org/git/gitweb.cgi?p=3Dbinutils-gdb.git;h=3Deb5e952f9542= 3bc6ae18457ccc359c8b6c0fa387 commit eb5e952f95423bc6ae18457ccc359c8b6c0fa387 Author: Jan Beulich Date: Fri Nov 24 09:53:55 2023 +0100 RISC-V: reduce redundancy in sign/zero extension macro insn handling =20 Fold M_{S,Z}EXTH, deriving signed-ness from the incoming mnemonic. Fold riscv_ext()'s calls md_assemblef(), the first of which were entirely identical, while the other pair differed in just a single character. =20 Acked-by: Palmer Dabbelt Diff: --- gas/config/tc-riscv.c | 21 +++++---------------- include/opcode/riscv.h | 3 +-- opcodes/riscv-opc.c | 4 ++-- 3 files changed, 8 insertions(+), 20 deletions(-) diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 3222bd1aec7..04738d5e00c 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1960,16 +1960,9 @@ load_const (int reg, expressionS *ep) static void riscv_ext (int destreg, int srcreg, unsigned shift, bool sign) { - if (sign) - { - md_assemblef ("slli x%d, x%d, 0x%x", destreg, srcreg, shift); - md_assemblef ("srai x%d, x%d, 0x%x", destreg, destreg, shift); - } - else - { - md_assemblef ("slli x%d, x%d, 0x%x", destreg, srcreg, shift); - md_assemblef ("srli x%d, x%d, 0x%x", destreg, destreg, shift); - } + md_assemblef ("slli x%d, x%d, %#x", destreg, srcreg, shift); + md_assemblef ("sr%ci x%d, x%d, %#x", + sign ? 'a' : 'l', destreg, destreg, shift); } =20 /* Expand RISC-V Vector macros into one or more instructions. */ @@ -2093,8 +2086,8 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_exp= r, riscv_call (rd, rs1, imm_expr, *imm_reloc); break; =20 - case M_ZEXTH: - riscv_ext (rd, rs1, xlen - 16, false); + case M_EXTH: + riscv_ext (rd, rs1, xlen - 16, *ip->insn_mo->name =3D=3D 's'); break; =20 case M_ZEXTW: @@ -2105,10 +2098,6 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_ex= pr, riscv_ext (rd, rs1, xlen - 8, true); break; =20 - case M_SEXTH: - riscv_ext (rd, rs1, xlen - 16, true); - break; - case M_VMSGE: vector_macro (ip); break; diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 3099c9e256c..25486869606 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -558,10 +558,9 @@ enum M_CALL, M_J, M_LI, - M_ZEXTH, + M_EXTH, M_ZEXTW, M_SEXTB, - M_SEXTH, M_VMSGE, M_NUM_MACROS }; diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 39196e7f2f2..c9ba4c99284 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1044,11 +1044,11 @@ const struct riscv_opcode riscv_opcodes[] =3D {"sext.b", 0, INSN_CLASS_I, "d,s", 0, (int) M_SEXTB, NULL, I= NSN_MACRO }, {"sext.h", 0, INSN_CLASS_ZCB_AND_ZBB, "Cs,Cw", MATCH_C_SEXT_H, MASK_C= _SEXT_H, match_opcode, INSN_ALIAS }, {"sext.h", 0, INSN_CLASS_ZBB, "d,s", MATCH_SEXT_H, MASK_SEXT_H, mat= ch_opcode, 0 }, -{"sext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_SEXTH, NULL, I= NSN_MACRO }, +{"sext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_EXTH, NULL, IN= SN_MACRO }, {"zext.h", 0, INSN_CLASS_ZCB_AND_ZBB, "Cs,Cw", MATCH_C_ZEXT_H, MASK_C= _ZEXT_H, match_opcode, INSN_ALIAS }, {"zext.h", 32, INSN_CLASS_ZBB, "d,s", MATCH_PACK, MASK_PACK | MASK_R= S2, match_opcode, 0 }, {"zext.h", 64, INSN_CLASS_ZBB, "d,s", MATCH_PACKW, MASK_PACKW | MASK= _RS2, match_opcode, 0 }, -{"zext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTH, NULL, I= NSN_MACRO }, +{"zext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_EXTH, NULL, IN= SN_MACRO }, {"orc.b", 0, INSN_CLASS_ZBB, "d,s", MATCH_GORCI | MATCH_SHAMT_ORC_= B, MASK_GORCI | MASK_SHAMT, match_opcode, 0 }, {"clzw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CLZW, MASK_CLZW, match_o= pcode, 0 }, {"ctzw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CTZW, MASK_CTZW, match_o= pcode, 0 },